forked from Minki/linux
338 lines
7.9 KiB
C
338 lines
7.9 KiB
C
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/*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, version 2, as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*
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* Copyright SUSE Linux Products GmbH 2009
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*
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* Authors: Alexander Graf <agraf@suse.de>
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*/
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#include <asm/kvm_ppc.h>
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#include <asm/disassemble.h>
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#include <asm/kvm_book3s.h>
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#include <asm/reg.h>
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#define OP_19_XOP_RFID 18
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#define OP_19_XOP_RFI 50
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#define OP_31_XOP_MFMSR 83
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#define OP_31_XOP_MTMSR 146
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#define OP_31_XOP_MTMSRD 178
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#define OP_31_XOP_MTSRIN 242
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#define OP_31_XOP_TLBIEL 274
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#define OP_31_XOP_TLBIE 306
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#define OP_31_XOP_SLBMTE 402
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#define OP_31_XOP_SLBIE 434
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#define OP_31_XOP_SLBIA 498
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#define OP_31_XOP_MFSRIN 659
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#define OP_31_XOP_SLBMFEV 851
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#define OP_31_XOP_EIOIO 854
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#define OP_31_XOP_SLBMFEE 915
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/* DCBZ is actually 1014, but we patch it to 1010 so we get a trap */
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#define OP_31_XOP_DCBZ 1010
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int kvmppc_core_emulate_op(struct kvm_run *run, struct kvm_vcpu *vcpu,
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unsigned int inst, int *advance)
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{
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int emulated = EMULATE_DONE;
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switch (get_op(inst)) {
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case 19:
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switch (get_xop(inst)) {
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case OP_19_XOP_RFID:
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case OP_19_XOP_RFI:
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vcpu->arch.pc = vcpu->arch.srr0;
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kvmppc_set_msr(vcpu, vcpu->arch.srr1);
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*advance = 0;
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break;
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default:
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emulated = EMULATE_FAIL;
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break;
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}
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break;
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case 31:
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switch (get_xop(inst)) {
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case OP_31_XOP_MFMSR:
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vcpu->arch.gpr[get_rt(inst)] = vcpu->arch.msr;
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break;
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case OP_31_XOP_MTMSRD:
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{
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ulong rs = vcpu->arch.gpr[get_rs(inst)];
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if (inst & 0x10000) {
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vcpu->arch.msr &= ~(MSR_RI | MSR_EE);
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vcpu->arch.msr |= rs & (MSR_RI | MSR_EE);
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} else
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kvmppc_set_msr(vcpu, rs);
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break;
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}
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case OP_31_XOP_MTMSR:
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kvmppc_set_msr(vcpu, vcpu->arch.gpr[get_rs(inst)]);
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break;
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case OP_31_XOP_MFSRIN:
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{
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int srnum;
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srnum = (vcpu->arch.gpr[get_rb(inst)] >> 28) & 0xf;
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if (vcpu->arch.mmu.mfsrin) {
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u32 sr;
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sr = vcpu->arch.mmu.mfsrin(vcpu, srnum);
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vcpu->arch.gpr[get_rt(inst)] = sr;
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}
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break;
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}
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case OP_31_XOP_MTSRIN:
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vcpu->arch.mmu.mtsrin(vcpu,
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(vcpu->arch.gpr[get_rb(inst)] >> 28) & 0xf,
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vcpu->arch.gpr[get_rs(inst)]);
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break;
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case OP_31_XOP_TLBIE:
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case OP_31_XOP_TLBIEL:
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{
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bool large = (inst & 0x00200000) ? true : false;
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ulong addr = vcpu->arch.gpr[get_rb(inst)];
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vcpu->arch.mmu.tlbie(vcpu, addr, large);
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break;
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}
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case OP_31_XOP_EIOIO:
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break;
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case OP_31_XOP_SLBMTE:
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if (!vcpu->arch.mmu.slbmte)
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return EMULATE_FAIL;
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vcpu->arch.mmu.slbmte(vcpu, vcpu->arch.gpr[get_rs(inst)],
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vcpu->arch.gpr[get_rb(inst)]);
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break;
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case OP_31_XOP_SLBIE:
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if (!vcpu->arch.mmu.slbie)
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return EMULATE_FAIL;
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vcpu->arch.mmu.slbie(vcpu, vcpu->arch.gpr[get_rb(inst)]);
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break;
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case OP_31_XOP_SLBIA:
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if (!vcpu->arch.mmu.slbia)
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return EMULATE_FAIL;
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vcpu->arch.mmu.slbia(vcpu);
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break;
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case OP_31_XOP_SLBMFEE:
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if (!vcpu->arch.mmu.slbmfee) {
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emulated = EMULATE_FAIL;
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} else {
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ulong t, rb;
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rb = vcpu->arch.gpr[get_rb(inst)];
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t = vcpu->arch.mmu.slbmfee(vcpu, rb);
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vcpu->arch.gpr[get_rt(inst)] = t;
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}
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break;
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case OP_31_XOP_SLBMFEV:
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if (!vcpu->arch.mmu.slbmfev) {
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emulated = EMULATE_FAIL;
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} else {
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ulong t, rb;
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rb = vcpu->arch.gpr[get_rb(inst)];
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t = vcpu->arch.mmu.slbmfev(vcpu, rb);
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vcpu->arch.gpr[get_rt(inst)] = t;
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}
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break;
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case OP_31_XOP_DCBZ:
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{
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ulong rb = vcpu->arch.gpr[get_rb(inst)];
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ulong ra = 0;
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ulong addr;
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u32 zeros[8] = { 0, 0, 0, 0, 0, 0, 0, 0 };
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if (get_ra(inst))
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ra = vcpu->arch.gpr[get_ra(inst)];
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addr = (ra + rb) & ~31ULL;
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if (!(vcpu->arch.msr & MSR_SF))
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addr &= 0xffffffff;
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if (kvmppc_st(vcpu, addr, 32, zeros)) {
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vcpu->arch.dear = addr;
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vcpu->arch.fault_dear = addr;
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to_book3s(vcpu)->dsisr = DSISR_PROTFAULT |
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DSISR_ISSTORE;
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kvmppc_book3s_queue_irqprio(vcpu,
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BOOK3S_INTERRUPT_DATA_STORAGE);
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kvmppc_mmu_pte_flush(vcpu, addr, ~0xFFFULL);
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}
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break;
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}
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default:
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emulated = EMULATE_FAIL;
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}
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break;
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default:
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emulated = EMULATE_FAIL;
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}
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return emulated;
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}
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static void kvmppc_write_bat(struct kvm_vcpu *vcpu, int sprn, u64 val)
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{
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struct kvmppc_vcpu_book3s *vcpu_book3s = to_book3s(vcpu);
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struct kvmppc_bat *bat;
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switch (sprn) {
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case SPRN_IBAT0U ... SPRN_IBAT3L:
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bat = &vcpu_book3s->ibat[(sprn - SPRN_IBAT0U) / 2];
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break;
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case SPRN_IBAT4U ... SPRN_IBAT7L:
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bat = &vcpu_book3s->ibat[(sprn - SPRN_IBAT4U) / 2];
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break;
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case SPRN_DBAT0U ... SPRN_DBAT3L:
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bat = &vcpu_book3s->dbat[(sprn - SPRN_DBAT0U) / 2];
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break;
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case SPRN_DBAT4U ... SPRN_DBAT7L:
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bat = &vcpu_book3s->dbat[(sprn - SPRN_DBAT4U) / 2];
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break;
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default:
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BUG();
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}
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if (!(sprn % 2)) {
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/* Upper BAT */
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u32 bl = (val >> 2) & 0x7ff;
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bat->bepi_mask = (~bl << 17);
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bat->bepi = val & 0xfffe0000;
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bat->vs = (val & 2) ? 1 : 0;
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bat->vp = (val & 1) ? 1 : 0;
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} else {
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/* Lower BAT */
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bat->brpn = val & 0xfffe0000;
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bat->wimg = (val >> 3) & 0xf;
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bat->pp = val & 3;
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}
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}
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int kvmppc_core_emulate_mtspr(struct kvm_vcpu *vcpu, int sprn, int rs)
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{
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int emulated = EMULATE_DONE;
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switch (sprn) {
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case SPRN_SDR1:
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to_book3s(vcpu)->sdr1 = vcpu->arch.gpr[rs];
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break;
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case SPRN_DSISR:
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to_book3s(vcpu)->dsisr = vcpu->arch.gpr[rs];
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break;
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case SPRN_DAR:
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vcpu->arch.dear = vcpu->arch.gpr[rs];
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break;
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case SPRN_HIOR:
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to_book3s(vcpu)->hior = vcpu->arch.gpr[rs];
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break;
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case SPRN_IBAT0U ... SPRN_IBAT3L:
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case SPRN_IBAT4U ... SPRN_IBAT7L:
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case SPRN_DBAT0U ... SPRN_DBAT3L:
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case SPRN_DBAT4U ... SPRN_DBAT7L:
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kvmppc_write_bat(vcpu, sprn, vcpu->arch.gpr[rs]);
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/* BAT writes happen so rarely that we're ok to flush
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* everything here */
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kvmppc_mmu_pte_flush(vcpu, 0, 0);
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break;
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case SPRN_HID0:
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to_book3s(vcpu)->hid[0] = vcpu->arch.gpr[rs];
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break;
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case SPRN_HID1:
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to_book3s(vcpu)->hid[1] = vcpu->arch.gpr[rs];
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break;
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case SPRN_HID2:
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to_book3s(vcpu)->hid[2] = vcpu->arch.gpr[rs];
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break;
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case SPRN_HID4:
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to_book3s(vcpu)->hid[4] = vcpu->arch.gpr[rs];
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break;
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case SPRN_HID5:
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to_book3s(vcpu)->hid[5] = vcpu->arch.gpr[rs];
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/* guest HID5 set can change is_dcbz32 */
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if (vcpu->arch.mmu.is_dcbz32(vcpu) &&
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(mfmsr() & MSR_HV))
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vcpu->arch.hflags |= BOOK3S_HFLAG_DCBZ32;
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break;
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case SPRN_ICTC:
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case SPRN_THRM1:
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case SPRN_THRM2:
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case SPRN_THRM3:
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case SPRN_CTRLF:
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case SPRN_CTRLT:
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break;
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default:
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printk(KERN_INFO "KVM: invalid SPR write: %d\n", sprn);
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#ifndef DEBUG_SPR
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emulated = EMULATE_FAIL;
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#endif
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break;
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}
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return emulated;
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}
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int kvmppc_core_emulate_mfspr(struct kvm_vcpu *vcpu, int sprn, int rt)
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{
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int emulated = EMULATE_DONE;
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switch (sprn) {
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case SPRN_SDR1:
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vcpu->arch.gpr[rt] = to_book3s(vcpu)->sdr1;
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break;
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case SPRN_DSISR:
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vcpu->arch.gpr[rt] = to_book3s(vcpu)->dsisr;
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break;
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case SPRN_DAR:
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vcpu->arch.gpr[rt] = vcpu->arch.dear;
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break;
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case SPRN_HIOR:
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vcpu->arch.gpr[rt] = to_book3s(vcpu)->hior;
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break;
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case SPRN_HID0:
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vcpu->arch.gpr[rt] = to_book3s(vcpu)->hid[0];
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break;
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case SPRN_HID1:
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vcpu->arch.gpr[rt] = to_book3s(vcpu)->hid[1];
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break;
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case SPRN_HID2:
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vcpu->arch.gpr[rt] = to_book3s(vcpu)->hid[2];
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break;
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case SPRN_HID4:
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vcpu->arch.gpr[rt] = to_book3s(vcpu)->hid[4];
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break;
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case SPRN_HID5:
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vcpu->arch.gpr[rt] = to_book3s(vcpu)->hid[5];
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break;
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case SPRN_THRM1:
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case SPRN_THRM2:
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case SPRN_THRM3:
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case SPRN_CTRLF:
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case SPRN_CTRLT:
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vcpu->arch.gpr[rt] = 0;
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break;
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default:
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printk(KERN_INFO "KVM: invalid SPR read: %d\n", sprn);
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#ifndef DEBUG_SPR
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emulated = EMULATE_FAIL;
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#endif
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break;
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}
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return emulated;
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}
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