forked from Minki/linux
514 lines
14 KiB
C
514 lines
14 KiB
C
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/*
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* Copyright © 2014 Broadcom
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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/**
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* DOC: Shader validator for VC4.
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*
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* The VC4 has no IOMMU between it and system memory, so a user with
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* access to execute shaders could escalate privilege by overwriting
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* system memory (using the VPM write address register in the
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* general-purpose DMA mode) or reading system memory it shouldn't
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* (reading it as a texture, or uniform data, or vertex data).
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*
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* This walks over a shader BO, ensuring that its accesses are
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* appropriately bounded, and recording how many texture accesses are
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* made and where so that we can do relocations for them in the
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* uniform stream.
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*/
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#include "vc4_drv.h"
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#include "vc4_qpu_defines.h"
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struct vc4_shader_validation_state {
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struct vc4_texture_sample_info tmu_setup[2];
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int tmu_write_count[2];
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/* For registers that were last written to by a MIN instruction with
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* one argument being a uniform, the address of the uniform.
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* Otherwise, ~0.
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*
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* This is used for the validation of direct address memory reads.
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*/
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uint32_t live_min_clamp_offsets[32 + 32 + 4];
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bool live_max_clamp_regs[32 + 32 + 4];
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};
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static uint32_t
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waddr_to_live_reg_index(uint32_t waddr, bool is_b)
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{
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if (waddr < 32) {
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if (is_b)
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return 32 + waddr;
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else
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return waddr;
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} else if (waddr <= QPU_W_ACC3) {
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return 64 + waddr - QPU_W_ACC0;
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} else {
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return ~0;
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}
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}
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static uint32_t
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raddr_add_a_to_live_reg_index(uint64_t inst)
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{
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uint32_t sig = QPU_GET_FIELD(inst, QPU_SIG);
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uint32_t add_a = QPU_GET_FIELD(inst, QPU_ADD_A);
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uint32_t raddr_a = QPU_GET_FIELD(inst, QPU_RADDR_A);
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uint32_t raddr_b = QPU_GET_FIELD(inst, QPU_RADDR_B);
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if (add_a == QPU_MUX_A)
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return raddr_a;
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else if (add_a == QPU_MUX_B && sig != QPU_SIG_SMALL_IMM)
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return 32 + raddr_b;
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else if (add_a <= QPU_MUX_R3)
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return 64 + add_a;
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else
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return ~0;
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}
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static bool
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is_tmu_submit(uint32_t waddr)
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{
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return (waddr == QPU_W_TMU0_S ||
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waddr == QPU_W_TMU1_S);
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}
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static bool
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is_tmu_write(uint32_t waddr)
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{
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return (waddr >= QPU_W_TMU0_S &&
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waddr <= QPU_W_TMU1_B);
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}
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static bool
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record_texture_sample(struct vc4_validated_shader_info *validated_shader,
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struct vc4_shader_validation_state *validation_state,
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int tmu)
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{
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uint32_t s = validated_shader->num_texture_samples;
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int i;
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struct vc4_texture_sample_info *temp_samples;
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temp_samples = krealloc(validated_shader->texture_samples,
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(s + 1) * sizeof(*temp_samples),
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GFP_KERNEL);
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if (!temp_samples)
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return false;
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memcpy(&temp_samples[s],
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&validation_state->tmu_setup[tmu],
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sizeof(*temp_samples));
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validated_shader->num_texture_samples = s + 1;
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validated_shader->texture_samples = temp_samples;
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for (i = 0; i < 4; i++)
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validation_state->tmu_setup[tmu].p_offset[i] = ~0;
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return true;
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}
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static bool
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check_tmu_write(uint64_t inst,
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struct vc4_validated_shader_info *validated_shader,
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struct vc4_shader_validation_state *validation_state,
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bool is_mul)
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{
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uint32_t waddr = (is_mul ?
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QPU_GET_FIELD(inst, QPU_WADDR_MUL) :
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QPU_GET_FIELD(inst, QPU_WADDR_ADD));
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uint32_t raddr_a = QPU_GET_FIELD(inst, QPU_RADDR_A);
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uint32_t raddr_b = QPU_GET_FIELD(inst, QPU_RADDR_B);
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int tmu = waddr > QPU_W_TMU0_B;
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bool submit = is_tmu_submit(waddr);
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bool is_direct = submit && validation_state->tmu_write_count[tmu] == 0;
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uint32_t sig = QPU_GET_FIELD(inst, QPU_SIG);
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if (is_direct) {
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uint32_t add_b = QPU_GET_FIELD(inst, QPU_ADD_B);
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uint32_t clamp_reg, clamp_offset;
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if (sig == QPU_SIG_SMALL_IMM) {
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DRM_ERROR("direct TMU read used small immediate\n");
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return false;
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}
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/* Make sure that this texture load is an add of the base
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* address of the UBO to a clamped offset within the UBO.
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*/
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if (is_mul ||
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QPU_GET_FIELD(inst, QPU_OP_ADD) != QPU_A_ADD) {
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DRM_ERROR("direct TMU load wasn't an add\n");
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return false;
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}
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/* We assert that the the clamped address is the first
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* argument, and the UBO base address is the second argument.
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* This is arbitrary, but simpler than supporting flipping the
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* two either way.
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*/
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clamp_reg = raddr_add_a_to_live_reg_index(inst);
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if (clamp_reg == ~0) {
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DRM_ERROR("direct TMU load wasn't clamped\n");
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return false;
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}
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clamp_offset = validation_state->live_min_clamp_offsets[clamp_reg];
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if (clamp_offset == ~0) {
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DRM_ERROR("direct TMU load wasn't clamped\n");
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return false;
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}
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/* Store the clamp value's offset in p1 (see reloc_tex() in
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* vc4_validate.c).
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*/
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validation_state->tmu_setup[tmu].p_offset[1] =
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clamp_offset;
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if (!(add_b == QPU_MUX_A && raddr_a == QPU_R_UNIF) &&
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!(add_b == QPU_MUX_B && raddr_b == QPU_R_UNIF)) {
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DRM_ERROR("direct TMU load didn't add to a uniform\n");
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return false;
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}
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validation_state->tmu_setup[tmu].is_direct = true;
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} else {
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if (raddr_a == QPU_R_UNIF || (sig != QPU_SIG_SMALL_IMM &&
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raddr_b == QPU_R_UNIF)) {
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DRM_ERROR("uniform read in the same instruction as "
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"texture setup.\n");
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return false;
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}
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}
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if (validation_state->tmu_write_count[tmu] >= 4) {
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DRM_ERROR("TMU%d got too many parameters before dispatch\n",
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tmu);
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return false;
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}
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validation_state->tmu_setup[tmu].p_offset[validation_state->tmu_write_count[tmu]] =
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validated_shader->uniforms_size;
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validation_state->tmu_write_count[tmu]++;
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/* Since direct uses a RADDR uniform reference, it will get counted in
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* check_instruction_reads()
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*/
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if (!is_direct)
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validated_shader->uniforms_size += 4;
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if (submit) {
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if (!record_texture_sample(validated_shader,
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validation_state, tmu)) {
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return false;
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}
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validation_state->tmu_write_count[tmu] = 0;
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}
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return true;
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}
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static bool
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check_reg_write(uint64_t inst,
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struct vc4_validated_shader_info *validated_shader,
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struct vc4_shader_validation_state *validation_state,
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bool is_mul)
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{
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uint32_t waddr = (is_mul ?
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QPU_GET_FIELD(inst, QPU_WADDR_MUL) :
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QPU_GET_FIELD(inst, QPU_WADDR_ADD));
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switch (waddr) {
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case QPU_W_UNIFORMS_ADDRESS:
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/* XXX: We'll probably need to support this for reladdr, but
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* it's definitely a security-related one.
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*/
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DRM_ERROR("uniforms address load unsupported\n");
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return false;
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case QPU_W_TLB_COLOR_MS:
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case QPU_W_TLB_COLOR_ALL:
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case QPU_W_TLB_Z:
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/* These only interact with the tile buffer, not main memory,
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* so they're safe.
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*/
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return true;
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case QPU_W_TMU0_S:
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case QPU_W_TMU0_T:
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case QPU_W_TMU0_R:
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case QPU_W_TMU0_B:
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case QPU_W_TMU1_S:
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case QPU_W_TMU1_T:
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case QPU_W_TMU1_R:
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case QPU_W_TMU1_B:
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return check_tmu_write(inst, validated_shader, validation_state,
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is_mul);
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case QPU_W_HOST_INT:
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case QPU_W_TMU_NOSWAP:
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case QPU_W_TLB_ALPHA_MASK:
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case QPU_W_MUTEX_RELEASE:
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/* XXX: I haven't thought about these, so don't support them
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* for now.
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*/
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DRM_ERROR("Unsupported waddr %d\n", waddr);
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return false;
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case QPU_W_VPM_ADDR:
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DRM_ERROR("General VPM DMA unsupported\n");
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return false;
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case QPU_W_VPM:
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case QPU_W_VPMVCD_SETUP:
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/* We allow VPM setup in general, even including VPM DMA
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* configuration setup, because the (unsafe) DMA can only be
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* triggered by QPU_W_VPM_ADDR writes.
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*/
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return true;
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case QPU_W_TLB_STENCIL_SETUP:
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return true;
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}
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return true;
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}
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static void
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track_live_clamps(uint64_t inst,
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struct vc4_validated_shader_info *validated_shader,
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struct vc4_shader_validation_state *validation_state)
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{
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uint32_t op_add = QPU_GET_FIELD(inst, QPU_OP_ADD);
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uint32_t waddr_add = QPU_GET_FIELD(inst, QPU_WADDR_ADD);
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uint32_t waddr_mul = QPU_GET_FIELD(inst, QPU_WADDR_MUL);
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uint32_t cond_add = QPU_GET_FIELD(inst, QPU_COND_ADD);
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uint32_t add_a = QPU_GET_FIELD(inst, QPU_ADD_A);
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uint32_t add_b = QPU_GET_FIELD(inst, QPU_ADD_B);
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uint32_t raddr_a = QPU_GET_FIELD(inst, QPU_RADDR_A);
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uint32_t raddr_b = QPU_GET_FIELD(inst, QPU_RADDR_B);
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uint32_t sig = QPU_GET_FIELD(inst, QPU_SIG);
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bool ws = inst & QPU_WS;
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uint32_t lri_add_a, lri_add, lri_mul;
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bool add_a_is_min_0;
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/* Check whether OP_ADD's A argumennt comes from a live MAX(x, 0),
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* before we clear previous live state.
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*/
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lri_add_a = raddr_add_a_to_live_reg_index(inst);
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add_a_is_min_0 = (lri_add_a != ~0 &&
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validation_state->live_max_clamp_regs[lri_add_a]);
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/* Clear live state for registers written by our instruction. */
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lri_add = waddr_to_live_reg_index(waddr_add, ws);
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lri_mul = waddr_to_live_reg_index(waddr_mul, !ws);
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if (lri_mul != ~0) {
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validation_state->live_max_clamp_regs[lri_mul] = false;
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validation_state->live_min_clamp_offsets[lri_mul] = ~0;
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}
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if (lri_add != ~0) {
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validation_state->live_max_clamp_regs[lri_add] = false;
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validation_state->live_min_clamp_offsets[lri_add] = ~0;
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} else {
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/* Nothing further to do for live tracking, since only ADDs
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* generate new live clamp registers.
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*/
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return;
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}
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/* Now, handle remaining live clamp tracking for the ADD operation. */
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if (cond_add != QPU_COND_ALWAYS)
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return;
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if (op_add == QPU_A_MAX) {
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/* Track live clamps of a value to a minimum of 0 (in either
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* arg).
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*/
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if (sig != QPU_SIG_SMALL_IMM || raddr_b != 0 ||
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(add_a != QPU_MUX_B && add_b != QPU_MUX_B)) {
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|
return;
|
||
|
|
}
|
||
|
|
|
||
|
|
validation_state->live_max_clamp_regs[lri_add] = true;
|
||
|
|
} else if (op_add == QPU_A_MIN) {
|
||
|
|
/* Track live clamps of a value clamped to a minimum of 0 and
|
||
|
|
* a maximum of some uniform's offset.
|
||
|
|
*/
|
||
|
|
if (!add_a_is_min_0)
|
||
|
|
return;
|
||
|
|
|
||
|
|
if (!(add_b == QPU_MUX_A && raddr_a == QPU_R_UNIF) &&
|
||
|
|
!(add_b == QPU_MUX_B && raddr_b == QPU_R_UNIF &&
|
||
|
|
sig != QPU_SIG_SMALL_IMM)) {
|
||
|
|
return;
|
||
|
|
}
|
||
|
|
|
||
|
|
validation_state->live_min_clamp_offsets[lri_add] =
|
||
|
|
validated_shader->uniforms_size;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
static bool
|
||
|
|
check_instruction_writes(uint64_t inst,
|
||
|
|
struct vc4_validated_shader_info *validated_shader,
|
||
|
|
struct vc4_shader_validation_state *validation_state)
|
||
|
|
{
|
||
|
|
uint32_t waddr_add = QPU_GET_FIELD(inst, QPU_WADDR_ADD);
|
||
|
|
uint32_t waddr_mul = QPU_GET_FIELD(inst, QPU_WADDR_MUL);
|
||
|
|
bool ok;
|
||
|
|
|
||
|
|
if (is_tmu_write(waddr_add) && is_tmu_write(waddr_mul)) {
|
||
|
|
DRM_ERROR("ADD and MUL both set up textures\n");
|
||
|
|
return false;
|
||
|
|
}
|
||
|
|
|
||
|
|
ok = (check_reg_write(inst, validated_shader, validation_state,
|
||
|
|
false) &&
|
||
|
|
check_reg_write(inst, validated_shader, validation_state,
|
||
|
|
true));
|
||
|
|
|
||
|
|
track_live_clamps(inst, validated_shader, validation_state);
|
||
|
|
|
||
|
|
return ok;
|
||
|
|
}
|
||
|
|
|
||
|
|
static bool
|
||
|
|
check_instruction_reads(uint64_t inst,
|
||
|
|
struct vc4_validated_shader_info *validated_shader)
|
||
|
|
{
|
||
|
|
uint32_t raddr_a = QPU_GET_FIELD(inst, QPU_RADDR_A);
|
||
|
|
uint32_t raddr_b = QPU_GET_FIELD(inst, QPU_RADDR_B);
|
||
|
|
uint32_t sig = QPU_GET_FIELD(inst, QPU_SIG);
|
||
|
|
|
||
|
|
if (raddr_a == QPU_R_UNIF ||
|
||
|
|
(raddr_b == QPU_R_UNIF && sig != QPU_SIG_SMALL_IMM)) {
|
||
|
|
/* This can't overflow the uint32_t, because we're reading 8
|
||
|
|
* bytes of instruction to increment by 4 here, so we'd
|
||
|
|
* already be OOM.
|
||
|
|
*/
|
||
|
|
validated_shader->uniforms_size += 4;
|
||
|
|
}
|
||
|
|
|
||
|
|
return true;
|
||
|
|
}
|
||
|
|
|
||
|
|
struct vc4_validated_shader_info *
|
||
|
|
vc4_validate_shader(struct drm_gem_cma_object *shader_obj)
|
||
|
|
{
|
||
|
|
bool found_shader_end = false;
|
||
|
|
int shader_end_ip = 0;
|
||
|
|
uint32_t ip, max_ip;
|
||
|
|
uint64_t *shader;
|
||
|
|
struct vc4_validated_shader_info *validated_shader;
|
||
|
|
struct vc4_shader_validation_state validation_state;
|
||
|
|
int i;
|
||
|
|
|
||
|
|
memset(&validation_state, 0, sizeof(validation_state));
|
||
|
|
|
||
|
|
for (i = 0; i < 8; i++)
|
||
|
|
validation_state.tmu_setup[i / 4].p_offset[i % 4] = ~0;
|
||
|
|
for (i = 0; i < ARRAY_SIZE(validation_state.live_min_clamp_offsets); i++)
|
||
|
|
validation_state.live_min_clamp_offsets[i] = ~0;
|
||
|
|
|
||
|
|
shader = shader_obj->vaddr;
|
||
|
|
max_ip = shader_obj->base.size / sizeof(uint64_t);
|
||
|
|
|
||
|
|
validated_shader = kcalloc(1, sizeof(*validated_shader), GFP_KERNEL);
|
||
|
|
if (!validated_shader)
|
||
|
|
return NULL;
|
||
|
|
|
||
|
|
for (ip = 0; ip < max_ip; ip++) {
|
||
|
|
uint64_t inst = shader[ip];
|
||
|
|
uint32_t sig = QPU_GET_FIELD(inst, QPU_SIG);
|
||
|
|
|
||
|
|
switch (sig) {
|
||
|
|
case QPU_SIG_NONE:
|
||
|
|
case QPU_SIG_WAIT_FOR_SCOREBOARD:
|
||
|
|
case QPU_SIG_SCOREBOARD_UNLOCK:
|
||
|
|
case QPU_SIG_COLOR_LOAD:
|
||
|
|
case QPU_SIG_LOAD_TMU0:
|
||
|
|
case QPU_SIG_LOAD_TMU1:
|
||
|
|
case QPU_SIG_PROG_END:
|
||
|
|
case QPU_SIG_SMALL_IMM:
|
||
|
|
if (!check_instruction_writes(inst, validated_shader,
|
||
|
|
&validation_state)) {
|
||
|
|
DRM_ERROR("Bad write at ip %d\n", ip);
|
||
|
|
goto fail;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (!check_instruction_reads(inst, validated_shader))
|
||
|
|
goto fail;
|
||
|
|
|
||
|
|
if (sig == QPU_SIG_PROG_END) {
|
||
|
|
found_shader_end = true;
|
||
|
|
shader_end_ip = ip;
|
||
|
|
}
|
||
|
|
|
||
|
|
break;
|
||
|
|
|
||
|
|
case QPU_SIG_LOAD_IMM:
|
||
|
|
if (!check_instruction_writes(inst, validated_shader,
|
||
|
|
&validation_state)) {
|
||
|
|
DRM_ERROR("Bad LOAD_IMM write at ip %d\n", ip);
|
||
|
|
goto fail;
|
||
|
|
}
|
||
|
|
break;
|
||
|
|
|
||
|
|
default:
|
||
|
|
DRM_ERROR("Unsupported QPU signal %d at "
|
||
|
|
"instruction %d\n", sig, ip);
|
||
|
|
goto fail;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* There are two delay slots after program end is signaled
|
||
|
|
* that are still executed, then we're finished.
|
||
|
|
*/
|
||
|
|
if (found_shader_end && ip == shader_end_ip + 2)
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (ip == max_ip) {
|
||
|
|
DRM_ERROR("shader failed to terminate before "
|
||
|
|
"shader BO end at %zd\n",
|
||
|
|
shader_obj->base.size);
|
||
|
|
goto fail;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Again, no chance of integer overflow here because the worst case
|
||
|
|
* scenario is 8 bytes of uniforms plus handles per 8-byte
|
||
|
|
* instruction.
|
||
|
|
*/
|
||
|
|
validated_shader->uniforms_src_size =
|
||
|
|
(validated_shader->uniforms_size +
|
||
|
|
4 * validated_shader->num_texture_samples);
|
||
|
|
|
||
|
|
return validated_shader;
|
||
|
|
|
||
|
|
fail:
|
||
|
|
if (validated_shader) {
|
||
|
|
kfree(validated_shader->texture_samples);
|
||
|
|
kfree(validated_shader);
|
||
|
|
}
|
||
|
|
return NULL;
|
||
|
|
}
|