2008-07-18 04:55:51 +00:00
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#ifndef _SPARC64_TLB_H
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#define _SPARC64_TLB_H
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#include <linux/swap.h>
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#include <linux/pagemap.h>
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#include <asm/pgalloc.h>
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#include <asm/tlbflush.h>
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#include <asm/mmu_context.h>
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#define TLB_BATCH_NR 192
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/*
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* For UP we don't need to worry about TLB flush
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* and page free order so much..
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*/
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#ifdef CONFIG_SMP
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#define FREE_PTE_NR 506
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#define tlb_fast_mode(bp) ((bp)->pages_nr == ~0U)
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#else
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#define FREE_PTE_NR 1
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#define tlb_fast_mode(bp) 1
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#endif
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struct mmu_gather {
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struct mm_struct *mm;
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unsigned int pages_nr;
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unsigned int need_flush;
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unsigned int fullmm;
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unsigned int tlb_nr;
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unsigned long vaddrs[TLB_BATCH_NR];
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struct page *pages[FREE_PTE_NR];
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};
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DECLARE_PER_CPU(struct mmu_gather, mmu_gathers);
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#ifdef CONFIG_SMP
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extern void smp_flush_tlb_pending(struct mm_struct *,
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unsigned long, unsigned long *);
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#endif
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extern void __flush_tlb_pending(unsigned long, unsigned long, unsigned long *);
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extern void flush_tlb_pending(void);
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static inline struct mmu_gather *tlb_gather_mmu(struct mm_struct *mm, unsigned int full_mm_flush)
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{
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struct mmu_gather *mp = &get_cpu_var(mmu_gathers);
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BUG_ON(mp->tlb_nr);
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mp->mm = mm;
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mp->pages_nr = num_online_cpus() > 1 ? 0U : ~0U;
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mp->fullmm = full_mm_flush;
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return mp;
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}
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static inline void tlb_flush_mmu(struct mmu_gather *mp)
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{
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2009-03-26 08:54:46 +00:00
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if (!mp->fullmm)
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flush_tlb_pending();
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2008-07-18 04:55:51 +00:00
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if (mp->need_flush) {
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free_pages_and_swap_cache(mp->pages, mp->pages_nr);
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mp->pages_nr = 0;
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mp->need_flush = 0;
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}
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}
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#ifdef CONFIG_SMP
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extern void smp_flush_tlb_mm(struct mm_struct *mm);
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#define do_flush_tlb_mm(mm) smp_flush_tlb_mm(mm)
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#else
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#define do_flush_tlb_mm(mm) __flush_tlb_mm(CTX_HWBITS(mm->context), SECONDARY_CONTEXT)
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#endif
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static inline void tlb_finish_mmu(struct mmu_gather *mp, unsigned long start, unsigned long end)
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{
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tlb_flush_mmu(mp);
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if (mp->fullmm)
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mp->fullmm = 0;
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/* keep the page table cache within bounds */
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check_pgt_cache();
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put_cpu_var(mmu_gathers);
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}
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static inline void tlb_remove_page(struct mmu_gather *mp, struct page *page)
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{
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if (tlb_fast_mode(mp)) {
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free_page_and_swap_cache(page);
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return;
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}
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mp->need_flush = 1;
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mp->pages[mp->pages_nr++] = page;
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if (mp->pages_nr >= FREE_PTE_NR)
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tlb_flush_mmu(mp);
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}
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#define tlb_remove_tlb_entry(mp,ptep,addr) do { } while (0)
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mm: Pass virtual address to [__]p{te,ud,md}_free_tlb()
mm: Pass virtual address to [__]p{te,ud,md}_free_tlb()
Upcoming paches to support the new 64-bit "BookE" powerpc architecture
will need to have the virtual address corresponding to PTE page when
freeing it, due to the way the HW table walker works.
Basically, the TLB can be loaded with "large" pages that cover the whole
virtual space (well, sort-of, half of it actually) represented by a PTE
page, and which contain an "indirect" bit indicating that this TLB entry
RPN points to an array of PTEs from which the TLB can then create direct
entries. Thus, in order to invalidate those when PTE pages are deleted,
we need the virtual address to pass to tlbilx or tlbivax instructions.
The old trick of sticking it somewhere in the PTE page struct page sucks
too much, the address is almost readily available in all call sites and
almost everybody implemets these as macros, so we may as well add the
argument everywhere. I added it to the pmd and pud variants for consistency.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Acked-by: David Howells <dhowells@redhat.com> [MN10300 & FRV]
Acked-by: Nick Piggin <npiggin@suse.de>
Acked-by: Martin Schwidefsky <schwidefsky@de.ibm.com> [s390]
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2009-07-22 05:44:28 +00:00
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#define pte_free_tlb(mp, ptepage, addr) pte_free((mp)->mm, ptepage)
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#define pmd_free_tlb(mp, pmdp, addr) pmd_free((mp)->mm, pmdp)
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#define pud_free_tlb(tlb,pudp, addr) __pud_free_tlb(tlb,pudp,addr)
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2008-07-18 04:55:51 +00:00
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#define tlb_migrate_finish(mm) do { } while (0)
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#define tlb_start_vma(tlb, vma) do { } while (0)
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#define tlb_end_vma(tlb, vma) do { } while (0)
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#endif /* _SPARC64_TLB_H */
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