2019-06-03 05:44:50 +00:00
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/* SPDX-License-Identifier: GPL-2.0-only */
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2012-03-05 11:49:28 +00:00
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/*
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* Based on arch/arm/mm/proc.S
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*
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* Copyright (C) 2001 Deep Blue Solutions Ltd.
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* Copyright (C) 2012 ARM Ltd.
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* Author: Catalin Marinas <catalin.marinas@arm.com>
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*/
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#include <linux/init.h>
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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#include <asm/asm-offsets.h>
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#include <asm/hwcap.h>
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#include <asm/pgtable.h>
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2016-04-27 16:47:07 +00:00
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#include <asm/pgtable-hwdef.h>
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2016-02-25 01:44:57 +00:00
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#include <asm/cpufeature.h>
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#include <asm/alternative.h>
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2012-03-05 11:49:28 +00:00
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2014-04-02 16:55:40 +00:00
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#ifdef CONFIG_ARM64_64K_PAGES
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#define TCR_TG_FLAGS TCR_TG0_64K | TCR_TG1_64K
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2015-10-19 13:19:37 +00:00
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#elif defined(CONFIG_ARM64_16K_PAGES)
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#define TCR_TG_FLAGS TCR_TG0_16K | TCR_TG1_16K
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#else /* CONFIG_ARM64_4K_PAGES */
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2014-04-02 16:55:40 +00:00
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#define TCR_TG_FLAGS TCR_TG0_4K | TCR_TG1_4K
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#endif
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2018-02-27 14:15:49 +00:00
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#ifdef CONFIG_RANDOMIZE_BASE
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#define TCR_KASLR_FLAGS TCR_NFD1
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#else
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#define TCR_KASLR_FLAGS 0
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#endif
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2014-04-02 16:55:40 +00:00
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#define TCR_SMP_FLAGS TCR_SHARED
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2012-03-05 11:49:28 +00:00
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2014-04-02 16:55:40 +00:00
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/* PTWs cacheable, inner/outer WBWA */
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#define TCR_CACHE_FLAGS TCR_IRGN_WBWA | TCR_ORGN_WBWA
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2018-12-28 08:30:31 +00:00
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#ifdef CONFIG_KASAN_SW_TAGS
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#define TCR_KASAN_FLAGS TCR_TBI1
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#else
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#define TCR_KASAN_FLAGS 0
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#endif
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2012-03-05 11:49:28 +00:00
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#define MAIR(attr, mt) ((attr) << ((mt) * 8))
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2015-01-26 18:33:44 +00:00
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#ifdef CONFIG_CPU_PM
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2013-07-17 09:14:45 +00:00
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/**
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* cpu_do_suspend - save CPU registers context
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*
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* x0: virtual address of context pointer
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*/
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ENTRY(cpu_do_suspend)
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mrs x2, tpidr_el0
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mrs x3, tpidrro_el0
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mrs x4, contextidr_el1
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2019-04-08 17:17:19 +00:00
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mrs x5, osdlr_el1
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mrs x6, cpacr_el1
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mrs x7, tcr_el1
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mrs x8, vbar_el1
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mrs x9, mdscr_el1
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mrs x10, oslsr_el1
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mrs x11, sctlr_el1
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2018-01-08 15:38:06 +00:00
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alternative_if_not ARM64_HAS_VIRT_HOST_EXTN
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2019-04-08 17:17:19 +00:00
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mrs x12, tpidr_el1
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2018-01-08 15:38:06 +00:00
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alternative_else
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2019-04-08 17:17:19 +00:00
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mrs x12, tpidr_el2
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2018-01-08 15:38:06 +00:00
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alternative_endif
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2019-04-08 17:17:19 +00:00
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mrs x13, sp_el0
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2013-07-17 09:14:45 +00:00
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stp x2, x3, [x0]
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2019-04-08 17:17:19 +00:00
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stp x4, x5, [x0, #16]
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stp x6, x7, [x0, #32]
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stp x8, x9, [x0, #48]
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stp x10, x11, [x0, #64]
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stp x12, x13, [x0, #80]
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2013-07-17 09:14:45 +00:00
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ret
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ENDPROC(cpu_do_suspend)
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/**
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* cpu_do_resume - restore CPU register context
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*
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2016-04-27 16:47:07 +00:00
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* x0: Address of context pointer
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2013-07-17 09:14:45 +00:00
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*/
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2018-01-29 12:00:00 +00:00
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.pushsection ".idmap.text", "awx"
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2013-07-17 09:14:45 +00:00
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ENTRY(cpu_do_resume)
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ldp x2, x3, [x0]
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ldp x4, x5, [x0, #16]
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2016-04-27 16:47:07 +00:00
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ldp x6, x8, [x0, #32]
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ldp x9, x10, [x0, #48]
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ldp x11, x12, [x0, #64]
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2016-11-03 20:23:09 +00:00
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ldp x13, x14, [x0, #80]
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2013-07-17 09:14:45 +00:00
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msr tpidr_el0, x2
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msr tpidrro_el0, x3
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msr contextidr_el1, x4
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msr cpacr_el1, x6
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2016-04-27 16:47:07 +00:00
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/* Don't change t0sz here, mask those bits when restoring */
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2019-04-08 17:17:19 +00:00
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mrs x7, tcr_el1
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bfi x8, x7, TCR_T0SZ_OFFSET, TCR_TxSZ_WIDTH
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2016-04-27 16:47:07 +00:00
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2013-07-17 09:14:45 +00:00
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msr tcr_el1, x8
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msr vbar_el1, x9
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2016-08-26 15:03:42 +00:00
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/*
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* __cpu_setup() cleared MDSCR_EL1.MDE and friends, before unmasking
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* debug exceptions. By restoring MDSCR_EL1 here, we may take a debug
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2017-11-02 12:12:34 +00:00
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* exception. Mask them until local_daif_restore() in cpu_suspend()
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2016-08-26 15:03:42 +00:00
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* resets them.
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*/
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2017-11-02 12:12:34 +00:00
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disable_daif
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2013-07-17 09:14:45 +00:00
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msr mdscr_el1, x10
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2016-08-26 15:03:42 +00:00
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2016-04-27 16:47:07 +00:00
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msr sctlr_el1, x12
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2018-01-08 15:38:06 +00:00
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alternative_if_not ARM64_HAS_VIRT_HOST_EXTN
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2016-11-03 20:23:09 +00:00
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msr tpidr_el1, x13
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2018-01-08 15:38:06 +00:00
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alternative_else
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msr tpidr_el2, x13
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alternative_endif
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2016-11-03 20:23:09 +00:00
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msr sp_el0, x14
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2013-07-17 09:14:45 +00:00
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/*
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* Restore oslsr_el1 by writing oslar_el1
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*/
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2019-04-08 17:17:19 +00:00
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msr osdlr_el1, x5
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2013-07-17 09:14:45 +00:00
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ubfx x11, x11, #1, #1
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msr oslar_el1, x11
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2016-01-13 14:50:03 +00:00
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reset_pmuserenr_el0 x0 // Disable PMU access from EL0
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2018-01-15 19:38:59 +00:00
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alternative_if ARM64_HAS_RAS_EXTN
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msr_s SYS_DISR_EL1, xzr
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alternative_else_nop_endif
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2013-07-17 09:14:45 +00:00
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isb
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ret
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ENDPROC(cpu_do_resume)
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2016-08-24 17:27:29 +00:00
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.popsection
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2013-07-17 09:14:45 +00:00
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#endif
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2012-03-05 11:49:28 +00:00
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/*
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2014-01-27 07:19:32 +00:00
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* cpu_do_switch_mm(pgd_phys, tsk)
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2012-03-05 11:49:28 +00:00
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*
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* Set the translation table base pointer to be pgd_phys.
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*
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* - pgd_phys - physical address of new TTB
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*/
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ENTRY(cpu_do_switch_mm)
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2017-08-10 12:19:09 +00:00
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mrs x2, ttbr1_el1
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2015-10-06 17:46:24 +00:00
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mmid x1, x1 // get mm->context.id
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2018-01-29 11:59:57 +00:00
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phys_to_ttbr x3, x0
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2018-07-31 13:08:56 +00:00
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alternative_if ARM64_HAS_CNP
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cbz x1, 1f // skip CNP for reserved ASID
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orr x3, x3, #TTBR_CNP_BIT
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1:
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alternative_else_nop_endif
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2018-01-10 13:18:30 +00:00
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#ifdef CONFIG_ARM64_SW_TTBR0_PAN
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2018-01-24 08:27:08 +00:00
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bfi x3, x1, #48, #16 // set the ASID field in TTBR0
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2018-01-10 13:18:30 +00:00
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#endif
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2017-08-10 12:19:09 +00:00
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bfi x2, x1, #48, #16 // set the ASID
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msr ttbr1_el1, x2 // in TTBR1 (since TCR.A1 is set)
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isb
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2018-01-24 08:27:08 +00:00
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msr ttbr0_el1, x3 // now update TTBR0
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2012-03-05 11:49:28 +00:00
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isb
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2018-01-02 18:19:39 +00:00
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b post_ttbr_update_workaround // Back to C code...
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2012-03-05 11:49:28 +00:00
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ENDPROC(cpu_do_switch_mm)
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2018-01-29 12:00:00 +00:00
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.pushsection ".idmap.text", "awx"
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2018-02-06 22:22:50 +00:00
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.macro __idmap_cpu_set_reserved_ttbr1, tmp1, tmp2
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adrp \tmp1, empty_zero_page
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2018-01-29 11:59:57 +00:00
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phys_to_ttbr \tmp2, \tmp1
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arm64: mm: Offset TTBR1 to allow 52-bit PTRS_PER_PGD
Enabling 52-bit VAs on arm64 requires that the PGD table expands from 64
entries (for the 48-bit case) to 1024 entries. This quantity,
PTRS_PER_PGD is used as follows to compute which PGD entry corresponds
to a given virtual address, addr:
pgd_index(addr) -> (addr >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1)
Userspace addresses are prefixed by 0's, so for a 48-bit userspace
address, uva, the following is true:
(uva >> PGDIR_SHIFT) & (1024 - 1) == (uva >> PGDIR_SHIFT) & (64 - 1)
In other words, a 48-bit userspace address will have the same pgd_index
when using PTRS_PER_PGD = 64 and 1024.
Kernel addresses are prefixed by 1's so, given a 48-bit kernel address,
kva, we have the following inequality:
(kva >> PGDIR_SHIFT) & (1024 - 1) != (kva >> PGDIR_SHIFT) & (64 - 1)
In other words a 48-bit kernel virtual address will have a different
pgd_index when using PTRS_PER_PGD = 64 and 1024.
If, however, we note that:
kva = 0xFFFF << 48 + lower (where lower[63:48] == 0b)
and, PGDIR_SHIFT = 42 (as we are dealing with 64KB PAGE_SIZE)
We can consider:
(kva >> PGDIR_SHIFT) & (1024 - 1) - (kva >> PGDIR_SHIFT) & (64 - 1)
= (0xFFFF << 6) & 0x3FF - (0xFFFF << 6) & 0x3F // "lower" cancels out
= 0x3C0
In other words, one can switch PTRS_PER_PGD to the 52-bit value globally
provided that they increment ttbr1_el1 by 0x3C0 * 8 = 0x1E00 bytes when
running with 48-bit kernel VAs (TCR_EL1.T1SZ = 16).
For kernel configuration where 52-bit userspace VAs are possible, this
patch offsets ttbr1_el1 and sets PTRS_PER_PGD corresponding to the
52-bit value.
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Suggested-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Steve Capper <steve.capper@arm.com>
[will: added comment to TTBR1_BADDR_4852_OFFSET calculation]
Signed-off-by: Will Deacon <will.deacon@arm.com>
2018-12-06 22:50:39 +00:00
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offset_ttbr1 \tmp2
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2018-02-06 22:22:50 +00:00
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msr ttbr1_el1, \tmp2
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isb
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tlbi vmalle1
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dsb nsh
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isb
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.endm
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arm64: mm: add code to safely replace TTBR1_EL1
If page tables are modified without suitable TLB maintenance, the ARM
architecture permits multiple TLB entries to be allocated for the same
VA. When this occurs, it is permitted that TLB conflict aborts are
raised in response to synchronous data/instruction accesses, and/or and
amalgamation of the TLB entries may be used as a result of a TLB lookup.
The presence of conflicting TLB entries may result in a variety of
behaviours detrimental to the system (e.g. erroneous physical addresses
may be used by I-cache fetches and/or page table walks). Some of these
cases may result in unexpected changes of hardware state, and/or result
in the (asynchronous) delivery of SError.
To avoid these issues, we must avoid situations where conflicting
entries may be allocated into TLBs. For user and module mappings we can
follow a strict break-before-make approach, but this cannot work for
modifications to the swapper page tables that cover the kernel text and
data.
Instead, this patch adds code which is intended to be executed from the
idmap, which can safely unmap the swapper page tables as it only
requires the idmap to be active. This enables us to uninstall the active
TTBR1_EL1 entry, invalidate TLBs, then install a new TTBR1_EL1 entry
without potentially unmapping code or data required for the sequence.
This avoids the risk of conflict, but requires that updates are staged
in a copy of the swapper page tables prior to being installed.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Tested-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Tested-by: Jeremy Linton <jeremy.linton@arm.com>
Cc: Laura Abbott <labbott@fedoraproject.org>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-01-25 11:45:01 +00:00
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/*
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2018-07-31 13:08:56 +00:00
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* void idmap_cpu_replace_ttbr1(phys_addr_t ttbr1)
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arm64: mm: add code to safely replace TTBR1_EL1
If page tables are modified without suitable TLB maintenance, the ARM
architecture permits multiple TLB entries to be allocated for the same
VA. When this occurs, it is permitted that TLB conflict aborts are
raised in response to synchronous data/instruction accesses, and/or and
amalgamation of the TLB entries may be used as a result of a TLB lookup.
The presence of conflicting TLB entries may result in a variety of
behaviours detrimental to the system (e.g. erroneous physical addresses
may be used by I-cache fetches and/or page table walks). Some of these
cases may result in unexpected changes of hardware state, and/or result
in the (asynchronous) delivery of SError.
To avoid these issues, we must avoid situations where conflicting
entries may be allocated into TLBs. For user and module mappings we can
follow a strict break-before-make approach, but this cannot work for
modifications to the swapper page tables that cover the kernel text and
data.
Instead, this patch adds code which is intended to be executed from the
idmap, which can safely unmap the swapper page tables as it only
requires the idmap to be active. This enables us to uninstall the active
TTBR1_EL1 entry, invalidate TLBs, then install a new TTBR1_EL1 entry
without potentially unmapping code or data required for the sequence.
This avoids the risk of conflict, but requires that updates are staged
in a copy of the swapper page tables prior to being installed.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Tested-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Tested-by: Jeremy Linton <jeremy.linton@arm.com>
Cc: Laura Abbott <labbott@fedoraproject.org>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-01-25 11:45:01 +00:00
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*
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* This is the low-level counterpart to cpu_replace_ttbr1, and should not be
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* called by anything else. It can only be executed from a TTBR0 mapping.
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*/
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ENTRY(idmap_cpu_replace_ttbr1)
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2017-11-02 12:12:34 +00:00
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save_and_disable_daif flags=x2
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arm64: mm: add code to safely replace TTBR1_EL1
If page tables are modified without suitable TLB maintenance, the ARM
architecture permits multiple TLB entries to be allocated for the same
VA. When this occurs, it is permitted that TLB conflict aborts are
raised in response to synchronous data/instruction accesses, and/or and
amalgamation of the TLB entries may be used as a result of a TLB lookup.
The presence of conflicting TLB entries may result in a variety of
behaviours detrimental to the system (e.g. erroneous physical addresses
may be used by I-cache fetches and/or page table walks). Some of these
cases may result in unexpected changes of hardware state, and/or result
in the (asynchronous) delivery of SError.
To avoid these issues, we must avoid situations where conflicting
entries may be allocated into TLBs. For user and module mappings we can
follow a strict break-before-make approach, but this cannot work for
modifications to the swapper page tables that cover the kernel text and
data.
Instead, this patch adds code which is intended to be executed from the
idmap, which can safely unmap the swapper page tables as it only
requires the idmap to be active. This enables us to uninstall the active
TTBR1_EL1 entry, invalidate TLBs, then install a new TTBR1_EL1 entry
without potentially unmapping code or data required for the sequence.
This avoids the risk of conflict, but requires that updates are staged
in a copy of the swapper page tables prior to being installed.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Tested-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Tested-by: Jeremy Linton <jeremy.linton@arm.com>
Cc: Laura Abbott <labbott@fedoraproject.org>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-01-25 11:45:01 +00:00
|
|
|
|
2018-02-06 22:22:50 +00:00
|
|
|
__idmap_cpu_set_reserved_ttbr1 x1, x3
|
arm64: mm: add code to safely replace TTBR1_EL1
If page tables are modified without suitable TLB maintenance, the ARM
architecture permits multiple TLB entries to be allocated for the same
VA. When this occurs, it is permitted that TLB conflict aborts are
raised in response to synchronous data/instruction accesses, and/or and
amalgamation of the TLB entries may be used as a result of a TLB lookup.
The presence of conflicting TLB entries may result in a variety of
behaviours detrimental to the system (e.g. erroneous physical addresses
may be used by I-cache fetches and/or page table walks). Some of these
cases may result in unexpected changes of hardware state, and/or result
in the (asynchronous) delivery of SError.
To avoid these issues, we must avoid situations where conflicting
entries may be allocated into TLBs. For user and module mappings we can
follow a strict break-before-make approach, but this cannot work for
modifications to the swapper page tables that cover the kernel text and
data.
Instead, this patch adds code which is intended to be executed from the
idmap, which can safely unmap the swapper page tables as it only
requires the idmap to be active. This enables us to uninstall the active
TTBR1_EL1 entry, invalidate TLBs, then install a new TTBR1_EL1 entry
without potentially unmapping code or data required for the sequence.
This avoids the risk of conflict, but requires that updates are staged
in a copy of the swapper page tables prior to being installed.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Tested-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Tested-by: Jeremy Linton <jeremy.linton@arm.com>
Cc: Laura Abbott <labbott@fedoraproject.org>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-01-25 11:45:01 +00:00
|
|
|
|
arm64: mm: Offset TTBR1 to allow 52-bit PTRS_PER_PGD
Enabling 52-bit VAs on arm64 requires that the PGD table expands from 64
entries (for the 48-bit case) to 1024 entries. This quantity,
PTRS_PER_PGD is used as follows to compute which PGD entry corresponds
to a given virtual address, addr:
pgd_index(addr) -> (addr >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1)
Userspace addresses are prefixed by 0's, so for a 48-bit userspace
address, uva, the following is true:
(uva >> PGDIR_SHIFT) & (1024 - 1) == (uva >> PGDIR_SHIFT) & (64 - 1)
In other words, a 48-bit userspace address will have the same pgd_index
when using PTRS_PER_PGD = 64 and 1024.
Kernel addresses are prefixed by 1's so, given a 48-bit kernel address,
kva, we have the following inequality:
(kva >> PGDIR_SHIFT) & (1024 - 1) != (kva >> PGDIR_SHIFT) & (64 - 1)
In other words a 48-bit kernel virtual address will have a different
pgd_index when using PTRS_PER_PGD = 64 and 1024.
If, however, we note that:
kva = 0xFFFF << 48 + lower (where lower[63:48] == 0b)
and, PGDIR_SHIFT = 42 (as we are dealing with 64KB PAGE_SIZE)
We can consider:
(kva >> PGDIR_SHIFT) & (1024 - 1) - (kva >> PGDIR_SHIFT) & (64 - 1)
= (0xFFFF << 6) & 0x3FF - (0xFFFF << 6) & 0x3F // "lower" cancels out
= 0x3C0
In other words, one can switch PTRS_PER_PGD to the 52-bit value globally
provided that they increment ttbr1_el1 by 0x3C0 * 8 = 0x1E00 bytes when
running with 48-bit kernel VAs (TCR_EL1.T1SZ = 16).
For kernel configuration where 52-bit userspace VAs are possible, this
patch offsets ttbr1_el1 and sets PTRS_PER_PGD corresponding to the
52-bit value.
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Suggested-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Steve Capper <steve.capper@arm.com>
[will: added comment to TTBR1_BADDR_4852_OFFSET calculation]
Signed-off-by: Will Deacon <will.deacon@arm.com>
2018-12-06 22:50:39 +00:00
|
|
|
offset_ttbr1 x0
|
2018-07-31 13:08:56 +00:00
|
|
|
msr ttbr1_el1, x0
|
arm64: mm: add code to safely replace TTBR1_EL1
If page tables are modified without suitable TLB maintenance, the ARM
architecture permits multiple TLB entries to be allocated for the same
VA. When this occurs, it is permitted that TLB conflict aborts are
raised in response to synchronous data/instruction accesses, and/or and
amalgamation of the TLB entries may be used as a result of a TLB lookup.
The presence of conflicting TLB entries may result in a variety of
behaviours detrimental to the system (e.g. erroneous physical addresses
may be used by I-cache fetches and/or page table walks). Some of these
cases may result in unexpected changes of hardware state, and/or result
in the (asynchronous) delivery of SError.
To avoid these issues, we must avoid situations where conflicting
entries may be allocated into TLBs. For user and module mappings we can
follow a strict break-before-make approach, but this cannot work for
modifications to the swapper page tables that cover the kernel text and
data.
Instead, this patch adds code which is intended to be executed from the
idmap, which can safely unmap the swapper page tables as it only
requires the idmap to be active. This enables us to uninstall the active
TTBR1_EL1 entry, invalidate TLBs, then install a new TTBR1_EL1 entry
without potentially unmapping code or data required for the sequence.
This avoids the risk of conflict, but requires that updates are staged
in a copy of the swapper page tables prior to being installed.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Tested-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Tested-by: Jeremy Linton <jeremy.linton@arm.com>
Cc: Laura Abbott <labbott@fedoraproject.org>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-01-25 11:45:01 +00:00
|
|
|
isb
|
|
|
|
|
|
2017-11-02 12:12:34 +00:00
|
|
|
restore_daif x2
|
arm64: mm: add code to safely replace TTBR1_EL1
If page tables are modified without suitable TLB maintenance, the ARM
architecture permits multiple TLB entries to be allocated for the same
VA. When this occurs, it is permitted that TLB conflict aborts are
raised in response to synchronous data/instruction accesses, and/or and
amalgamation of the TLB entries may be used as a result of a TLB lookup.
The presence of conflicting TLB entries may result in a variety of
behaviours detrimental to the system (e.g. erroneous physical addresses
may be used by I-cache fetches and/or page table walks). Some of these
cases may result in unexpected changes of hardware state, and/or result
in the (asynchronous) delivery of SError.
To avoid these issues, we must avoid situations where conflicting
entries may be allocated into TLBs. For user and module mappings we can
follow a strict break-before-make approach, but this cannot work for
modifications to the swapper page tables that cover the kernel text and
data.
Instead, this patch adds code which is intended to be executed from the
idmap, which can safely unmap the swapper page tables as it only
requires the idmap to be active. This enables us to uninstall the active
TTBR1_EL1 entry, invalidate TLBs, then install a new TTBR1_EL1 entry
without potentially unmapping code or data required for the sequence.
This avoids the risk of conflict, but requires that updates are staged
in a copy of the swapper page tables prior to being installed.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Tested-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Tested-by: Jeremy Linton <jeremy.linton@arm.com>
Cc: Laura Abbott <labbott@fedoraproject.org>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-01-25 11:45:01 +00:00
|
|
|
|
|
|
|
|
ret
|
|
|
|
|
ENDPROC(idmap_cpu_replace_ttbr1)
|
|
|
|
|
.popsection
|
|
|
|
|
|
2018-02-06 22:22:50 +00:00
|
|
|
#ifdef CONFIG_UNMAP_KERNEL_AT_EL0
|
2018-01-29 12:00:00 +00:00
|
|
|
.pushsection ".idmap.text", "awx"
|
2018-02-06 22:22:50 +00:00
|
|
|
|
|
|
|
|
.macro __idmap_kpti_get_pgtable_ent, type
|
|
|
|
|
dc cvac, cur_\()\type\()p // Ensure any existing dirty
|
|
|
|
|
dmb sy // lines are written back before
|
|
|
|
|
ldr \type, [cur_\()\type\()p] // loading the entry
|
2018-02-13 13:14:09 +00:00
|
|
|
tbz \type, #0, skip_\()\type // Skip invalid and
|
|
|
|
|
tbnz \type, #11, skip_\()\type // non-global entries
|
2018-02-06 22:22:50 +00:00
|
|
|
.endm
|
|
|
|
|
|
|
|
|
|
.macro __idmap_kpti_put_pgtable_ent_ng, type
|
|
|
|
|
orr \type, \type, #PTE_NG // Same bit for blocks and pages
|
2018-06-22 15:23:45 +00:00
|
|
|
str \type, [cur_\()\type\()p] // Update the entry and ensure
|
|
|
|
|
dmb sy // that it is visible to all
|
|
|
|
|
dc civac, cur_\()\type\()p // CPUs.
|
2018-02-06 22:22:50 +00:00
|
|
|
.endm
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* void __kpti_install_ng_mappings(int cpu, int num_cpus, phys_addr_t swapper)
|
|
|
|
|
*
|
|
|
|
|
* Called exactly once from stop_machine context by each CPU found during boot.
|
|
|
|
|
*/
|
|
|
|
|
__idmap_kpti_flag:
|
|
|
|
|
.long 1
|
|
|
|
|
ENTRY(idmap_kpti_install_ng_mappings)
|
|
|
|
|
cpu .req w0
|
|
|
|
|
num_cpus .req w1
|
|
|
|
|
swapper_pa .req x2
|
|
|
|
|
swapper_ttb .req x3
|
|
|
|
|
flag_ptr .req x4
|
|
|
|
|
cur_pgdp .req x5
|
|
|
|
|
end_pgdp .req x6
|
|
|
|
|
pgd .req x7
|
|
|
|
|
cur_pudp .req x8
|
|
|
|
|
end_pudp .req x9
|
|
|
|
|
pud .req x10
|
|
|
|
|
cur_pmdp .req x11
|
|
|
|
|
end_pmdp .req x12
|
|
|
|
|
pmd .req x13
|
|
|
|
|
cur_ptep .req x14
|
|
|
|
|
end_ptep .req x15
|
|
|
|
|
pte .req x16
|
|
|
|
|
|
|
|
|
|
mrs swapper_ttb, ttbr1_el1
|
arm64: mm: Offset TTBR1 to allow 52-bit PTRS_PER_PGD
Enabling 52-bit VAs on arm64 requires that the PGD table expands from 64
entries (for the 48-bit case) to 1024 entries. This quantity,
PTRS_PER_PGD is used as follows to compute which PGD entry corresponds
to a given virtual address, addr:
pgd_index(addr) -> (addr >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1)
Userspace addresses are prefixed by 0's, so for a 48-bit userspace
address, uva, the following is true:
(uva >> PGDIR_SHIFT) & (1024 - 1) == (uva >> PGDIR_SHIFT) & (64 - 1)
In other words, a 48-bit userspace address will have the same pgd_index
when using PTRS_PER_PGD = 64 and 1024.
Kernel addresses are prefixed by 1's so, given a 48-bit kernel address,
kva, we have the following inequality:
(kva >> PGDIR_SHIFT) & (1024 - 1) != (kva >> PGDIR_SHIFT) & (64 - 1)
In other words a 48-bit kernel virtual address will have a different
pgd_index when using PTRS_PER_PGD = 64 and 1024.
If, however, we note that:
kva = 0xFFFF << 48 + lower (where lower[63:48] == 0b)
and, PGDIR_SHIFT = 42 (as we are dealing with 64KB PAGE_SIZE)
We can consider:
(kva >> PGDIR_SHIFT) & (1024 - 1) - (kva >> PGDIR_SHIFT) & (64 - 1)
= (0xFFFF << 6) & 0x3FF - (0xFFFF << 6) & 0x3F // "lower" cancels out
= 0x3C0
In other words, one can switch PTRS_PER_PGD to the 52-bit value globally
provided that they increment ttbr1_el1 by 0x3C0 * 8 = 0x1E00 bytes when
running with 48-bit kernel VAs (TCR_EL1.T1SZ = 16).
For kernel configuration where 52-bit userspace VAs are possible, this
patch offsets ttbr1_el1 and sets PTRS_PER_PGD corresponding to the
52-bit value.
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Suggested-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Steve Capper <steve.capper@arm.com>
[will: added comment to TTBR1_BADDR_4852_OFFSET calculation]
Signed-off-by: Will Deacon <will.deacon@arm.com>
2018-12-06 22:50:39 +00:00
|
|
|
restore_ttbr1 swapper_ttb
|
2018-02-06 22:22:50 +00:00
|
|
|
adr flag_ptr, __idmap_kpti_flag
|
|
|
|
|
|
|
|
|
|
cbnz cpu, __idmap_kpti_secondary
|
|
|
|
|
|
|
|
|
|
/* We're the boot CPU. Wait for the others to catch up */
|
|
|
|
|
sevl
|
|
|
|
|
1: wfe
|
|
|
|
|
ldaxr w18, [flag_ptr]
|
|
|
|
|
eor w18, w18, num_cpus
|
|
|
|
|
cbnz w18, 1b
|
|
|
|
|
|
|
|
|
|
/* We need to walk swapper, so turn off the MMU. */
|
|
|
|
|
pre_disable_mmu_workaround
|
|
|
|
|
mrs x18, sctlr_el1
|
|
|
|
|
bic x18, x18, #SCTLR_ELx_M
|
|
|
|
|
msr sctlr_el1, x18
|
|
|
|
|
isb
|
|
|
|
|
|
|
|
|
|
/* Everybody is enjoying the idmap, so we can rewrite swapper. */
|
|
|
|
|
/* PGD */
|
|
|
|
|
mov cur_pgdp, swapper_pa
|
|
|
|
|
add end_pgdp, cur_pgdp, #(PTRS_PER_PGD * 8)
|
|
|
|
|
do_pgd: __idmap_kpti_get_pgtable_ent pgd
|
|
|
|
|
tbnz pgd, #1, walk_puds
|
|
|
|
|
next_pgd:
|
2018-02-13 13:14:09 +00:00
|
|
|
__idmap_kpti_put_pgtable_ent_ng pgd
|
|
|
|
|
skip_pgd:
|
2018-02-06 22:22:50 +00:00
|
|
|
add cur_pgdp, cur_pgdp, #8
|
|
|
|
|
cmp cur_pgdp, end_pgdp
|
|
|
|
|
b.ne do_pgd
|
|
|
|
|
|
|
|
|
|
/* Publish the updated tables and nuke all the TLBs */
|
|
|
|
|
dsb sy
|
|
|
|
|
tlbi vmalle1is
|
|
|
|
|
dsb ish
|
|
|
|
|
isb
|
|
|
|
|
|
|
|
|
|
/* We're done: fire up the MMU again */
|
|
|
|
|
mrs x18, sctlr_el1
|
|
|
|
|
orr x18, x18, #SCTLR_ELx_M
|
|
|
|
|
msr sctlr_el1, x18
|
|
|
|
|
isb
|
|
|
|
|
|
|
|
|
|
/* Set the flag to zero to indicate that we're all done */
|
|
|
|
|
str wzr, [flag_ptr]
|
|
|
|
|
ret
|
|
|
|
|
|
|
|
|
|
/* PUD */
|
|
|
|
|
walk_puds:
|
|
|
|
|
.if CONFIG_PGTABLE_LEVELS > 3
|
|
|
|
|
pte_to_phys cur_pudp, pgd
|
|
|
|
|
add end_pudp, cur_pudp, #(PTRS_PER_PUD * 8)
|
|
|
|
|
do_pud: __idmap_kpti_get_pgtable_ent pud
|
|
|
|
|
tbnz pud, #1, walk_pmds
|
|
|
|
|
next_pud:
|
2018-02-13 13:14:09 +00:00
|
|
|
__idmap_kpti_put_pgtable_ent_ng pud
|
|
|
|
|
skip_pud:
|
2018-02-06 22:22:50 +00:00
|
|
|
add cur_pudp, cur_pudp, 8
|
|
|
|
|
cmp cur_pudp, end_pudp
|
|
|
|
|
b.ne do_pud
|
|
|
|
|
b next_pgd
|
|
|
|
|
.else /* CONFIG_PGTABLE_LEVELS <= 3 */
|
|
|
|
|
mov pud, pgd
|
|
|
|
|
b walk_pmds
|
|
|
|
|
next_pud:
|
|
|
|
|
b next_pgd
|
|
|
|
|
.endif
|
|
|
|
|
|
|
|
|
|
/* PMD */
|
|
|
|
|
walk_pmds:
|
|
|
|
|
.if CONFIG_PGTABLE_LEVELS > 2
|
|
|
|
|
pte_to_phys cur_pmdp, pud
|
|
|
|
|
add end_pmdp, cur_pmdp, #(PTRS_PER_PMD * 8)
|
|
|
|
|
do_pmd: __idmap_kpti_get_pgtable_ent pmd
|
|
|
|
|
tbnz pmd, #1, walk_ptes
|
|
|
|
|
next_pmd:
|
2018-02-13 13:14:09 +00:00
|
|
|
__idmap_kpti_put_pgtable_ent_ng pmd
|
|
|
|
|
skip_pmd:
|
2018-02-06 22:22:50 +00:00
|
|
|
add cur_pmdp, cur_pmdp, #8
|
|
|
|
|
cmp cur_pmdp, end_pmdp
|
|
|
|
|
b.ne do_pmd
|
|
|
|
|
b next_pud
|
|
|
|
|
.else /* CONFIG_PGTABLE_LEVELS <= 2 */
|
|
|
|
|
mov pmd, pud
|
|
|
|
|
b walk_ptes
|
|
|
|
|
next_pmd:
|
|
|
|
|
b next_pud
|
|
|
|
|
.endif
|
|
|
|
|
|
|
|
|
|
/* PTE */
|
|
|
|
|
walk_ptes:
|
|
|
|
|
pte_to_phys cur_ptep, pmd
|
|
|
|
|
add end_ptep, cur_ptep, #(PTRS_PER_PTE * 8)
|
|
|
|
|
do_pte: __idmap_kpti_get_pgtable_ent pte
|
|
|
|
|
__idmap_kpti_put_pgtable_ent_ng pte
|
2018-02-13 13:14:09 +00:00
|
|
|
skip_pte:
|
2018-02-06 22:22:50 +00:00
|
|
|
add cur_ptep, cur_ptep, #8
|
|
|
|
|
cmp cur_ptep, end_ptep
|
|
|
|
|
b.ne do_pte
|
|
|
|
|
b next_pmd
|
|
|
|
|
|
|
|
|
|
/* Secondary CPUs end up here */
|
|
|
|
|
__idmap_kpti_secondary:
|
|
|
|
|
/* Uninstall swapper before surgery begins */
|
|
|
|
|
__idmap_cpu_set_reserved_ttbr1 x18, x17
|
|
|
|
|
|
|
|
|
|
/* Increment the flag to let the boot CPU we're ready */
|
|
|
|
|
1: ldxr w18, [flag_ptr]
|
|
|
|
|
add w18, w18, #1
|
|
|
|
|
stxr w17, w18, [flag_ptr]
|
|
|
|
|
cbnz w17, 1b
|
|
|
|
|
|
|
|
|
|
/* Wait for the boot CPU to finish messing around with swapper */
|
|
|
|
|
sevl
|
|
|
|
|
1: wfe
|
|
|
|
|
ldxr w18, [flag_ptr]
|
|
|
|
|
cbnz w18, 1b
|
|
|
|
|
|
|
|
|
|
/* All done, act like nothing happened */
|
arm64: mm: Offset TTBR1 to allow 52-bit PTRS_PER_PGD
Enabling 52-bit VAs on arm64 requires that the PGD table expands from 64
entries (for the 48-bit case) to 1024 entries. This quantity,
PTRS_PER_PGD is used as follows to compute which PGD entry corresponds
to a given virtual address, addr:
pgd_index(addr) -> (addr >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1)
Userspace addresses are prefixed by 0's, so for a 48-bit userspace
address, uva, the following is true:
(uva >> PGDIR_SHIFT) & (1024 - 1) == (uva >> PGDIR_SHIFT) & (64 - 1)
In other words, a 48-bit userspace address will have the same pgd_index
when using PTRS_PER_PGD = 64 and 1024.
Kernel addresses are prefixed by 1's so, given a 48-bit kernel address,
kva, we have the following inequality:
(kva >> PGDIR_SHIFT) & (1024 - 1) != (kva >> PGDIR_SHIFT) & (64 - 1)
In other words a 48-bit kernel virtual address will have a different
pgd_index when using PTRS_PER_PGD = 64 and 1024.
If, however, we note that:
kva = 0xFFFF << 48 + lower (where lower[63:48] == 0b)
and, PGDIR_SHIFT = 42 (as we are dealing with 64KB PAGE_SIZE)
We can consider:
(kva >> PGDIR_SHIFT) & (1024 - 1) - (kva >> PGDIR_SHIFT) & (64 - 1)
= (0xFFFF << 6) & 0x3FF - (0xFFFF << 6) & 0x3F // "lower" cancels out
= 0x3C0
In other words, one can switch PTRS_PER_PGD to the 52-bit value globally
provided that they increment ttbr1_el1 by 0x3C0 * 8 = 0x1E00 bytes when
running with 48-bit kernel VAs (TCR_EL1.T1SZ = 16).
For kernel configuration where 52-bit userspace VAs are possible, this
patch offsets ttbr1_el1 and sets PTRS_PER_PGD corresponding to the
52-bit value.
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Suggested-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Steve Capper <steve.capper@arm.com>
[will: added comment to TTBR1_BADDR_4852_OFFSET calculation]
Signed-off-by: Will Deacon <will.deacon@arm.com>
2018-12-06 22:50:39 +00:00
|
|
|
offset_ttbr1 swapper_ttb
|
2018-02-06 22:22:50 +00:00
|
|
|
msr ttbr1_el1, swapper_ttb
|
|
|
|
|
isb
|
|
|
|
|
ret
|
|
|
|
|
|
|
|
|
|
.unreq cpu
|
|
|
|
|
.unreq num_cpus
|
|
|
|
|
.unreq swapper_pa
|
|
|
|
|
.unreq swapper_ttb
|
|
|
|
|
.unreq flag_ptr
|
|
|
|
|
.unreq cur_pgdp
|
|
|
|
|
.unreq end_pgdp
|
|
|
|
|
.unreq pgd
|
|
|
|
|
.unreq cur_pudp
|
|
|
|
|
.unreq end_pudp
|
|
|
|
|
.unreq pud
|
|
|
|
|
.unreq cur_pmdp
|
|
|
|
|
.unreq end_pmdp
|
|
|
|
|
.unreq pmd
|
|
|
|
|
.unreq cur_ptep
|
|
|
|
|
.unreq end_ptep
|
|
|
|
|
.unreq pte
|
|
|
|
|
ENDPROC(idmap_kpti_install_ng_mappings)
|
|
|
|
|
.popsection
|
|
|
|
|
#endif
|
|
|
|
|
|
2012-03-05 11:49:28 +00:00
|
|
|
/*
|
|
|
|
|
* __cpu_setup
|
|
|
|
|
*
|
|
|
|
|
* Initialise the processor for turning the MMU on. Return in x0 the
|
|
|
|
|
* value of the SCTLR_EL1 register.
|
|
|
|
|
*/
|
2018-01-29 12:00:00 +00:00
|
|
|
.pushsection ".idmap.text", "awx"
|
2012-03-05 11:49:28 +00:00
|
|
|
ENTRY(__cpu_setup)
|
2015-10-06 17:46:22 +00:00
|
|
|
tlbi vmalle1 // Invalidate local TLB
|
|
|
|
|
dsb nsh
|
2012-03-05 11:49:28 +00:00
|
|
|
|
|
|
|
|
mov x0, #3 << 20
|
|
|
|
|
msr cpacr_el1, x0 // Enable FP/ASIMD
|
2015-08-20 10:47:13 +00:00
|
|
|
mov x0, #1 << 12 // Reset mdscr_el1 and disable
|
|
|
|
|
msr mdscr_el1, x0 // access to the DCC from EL0
|
arm64: debug: unmask PSTATE.D earlier
Clearing PSTATE.D is one of the requirements for generating a debug
exception. The arm64 booting protocol requires that PSTATE.D is set,
since many of the debug registers (for example, the hw_breakpoint
registers) are UNKNOWN out of reset and could potentially generate
spurious, fatal debug exceptions in early boot code if PSTATE.D was
clear. Once the debug registers have been safely initialised, PSTATE.D
is cleared, however this is currently broken for two reasons:
(1) The boot CPU clears PSTATE.D in a postcore_initcall and secondary
CPUs clear PSTATE.D in secondary_start_kernel. Since the initcall
runs after SMP (and the scheduler) have been initialised, there is
no guarantee that it is actually running on the boot CPU. In this
case, the boot CPU is left with PSTATE.D set and is not capable of
generating debug exceptions.
(2) In a preemptible kernel, we may explicitly schedule on the IRQ
return path to EL1. If an IRQ occurs with PSTATE.D set in the idle
thread, then we may schedule the kthread_init thread, run the
postcore_initcall to clear PSTATE.D and then context switch back
to the idle thread before returning from the IRQ. The exception
return path will then restore PSTATE.D from the stack, and set it
again.
This patch fixes the problem by moving the clearing of PSTATE.D earlier
to proc.S. This has the desirable effect of clearing it in one place for
all CPUs, long before we have to worry about the scheduler or any
exception handling. We ensure that the previous reset of MDSCR_EL1 has
completed before unmasking the exception, so that any spurious
exceptions resulting from UNKNOWN debug registers are not generated.
Without this patch applied, the kprobes selftests have been seen to fail
under KVM, where we end up attempting to step the OOL instruction buffer
with PSTATE.D set and therefore fail to complete the step.
Cc: <stable@vger.kernel.org>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Reported-by: Catalin Marinas <catalin.marinas@arm.com>
Tested-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Tested-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-07-19 14:07:37 +00:00
|
|
|
isb // Unmask debug exceptions now,
|
|
|
|
|
enable_dbg // since this is per-cpu
|
2016-01-13 14:50:03 +00:00
|
|
|
reset_pmuserenr_el0 x0 // Disable PMU access from EL0
|
2012-03-05 11:49:28 +00:00
|
|
|
/*
|
|
|
|
|
* Memory region attributes for LPAE:
|
|
|
|
|
*
|
|
|
|
|
* n = AttrIndx[2:0]
|
|
|
|
|
* n MAIR
|
|
|
|
|
* DEVICE_nGnRnE 000 00000000
|
|
|
|
|
* DEVICE_nGnRE 001 00000100
|
|
|
|
|
* DEVICE_GRE 010 00001100
|
|
|
|
|
* NORMAL_NC 011 01000100
|
|
|
|
|
* NORMAL 100 11111111
|
2015-08-07 08:36:59 +00:00
|
|
|
* NORMAL_WT 101 10111011
|
2012-03-05 11:49:28 +00:00
|
|
|
*/
|
|
|
|
|
ldr x5, =MAIR(0x00, MT_DEVICE_nGnRnE) | \
|
|
|
|
|
MAIR(0x04, MT_DEVICE_nGnRE) | \
|
|
|
|
|
MAIR(0x0c, MT_DEVICE_GRE) | \
|
|
|
|
|
MAIR(0x44, MT_NORMAL_NC) | \
|
2015-08-07 08:36:59 +00:00
|
|
|
MAIR(0xff, MT_NORMAL) | \
|
|
|
|
|
MAIR(0xbb, MT_NORMAL_WT)
|
2012-03-05 11:49:28 +00:00
|
|
|
msr mair_el1, x5
|
|
|
|
|
/*
|
|
|
|
|
* Prepare SCTLR
|
|
|
|
|
*/
|
2018-01-15 19:38:55 +00:00
|
|
|
mov_q x0, SCTLR_EL1_SET
|
2012-03-05 11:49:28 +00:00
|
|
|
/*
|
|
|
|
|
* Set/prepare TCR and TTBR. We use 512GB (39-bit) address range for
|
|
|
|
|
* both user and kernel.
|
|
|
|
|
*/
|
2014-04-02 16:55:40 +00:00
|
|
|
ldr x10, =TCR_TxSZ(VA_BITS) | TCR_CACHE_FLAGS | TCR_SMP_FLAGS | \
|
2018-02-27 14:15:49 +00:00
|
|
|
TCR_TG_FLAGS | TCR_KASLR_FLAGS | TCR_ASID16 | \
|
2018-12-28 08:30:31 +00:00
|
|
|
TCR_TBI0 | TCR_A1 | TCR_KASAN_FLAGS
|
2019-02-26 18:43:41 +00:00
|
|
|
tcr_clear_errata_bits x10, x9, x5
|
2018-12-06 22:50:41 +00:00
|
|
|
|
2018-12-10 14:15:15 +00:00
|
|
|
#ifdef CONFIG_ARM64_USER_VA_BITS_52
|
|
|
|
|
ldr_l x9, vabits_user
|
2018-12-06 22:50:41 +00:00
|
|
|
sub x9, xzr, x9
|
|
|
|
|
add x9, x9, #64
|
|
|
|
|
#else
|
|
|
|
|
ldr_l x9, idmap_t0sz
|
|
|
|
|
#endif
|
|
|
|
|
tcr_set_t0sz x10, x9
|
arm64: mm: increase VA range of identity map
The page size and the number of translation levels, and hence the supported
virtual address range, are build-time configurables on arm64 whose optimal
values are use case dependent. However, in the current implementation, if
the system's RAM is located at a very high offset, the virtual address range
needs to reflect that merely because the identity mapping, which is only used
to enable or disable the MMU, requires the extended virtual range to map the
physical memory at an equal virtual offset.
This patch relaxes that requirement, by increasing the number of translation
levels for the identity mapping only, and only when actually needed, i.e.,
when system RAM's offset is found to be out of reach at runtime.
Tested-by: Laura Abbott <lauraa@codeaurora.org>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Tested-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2015-03-19 16:42:27 +00:00
|
|
|
|
2014-03-07 08:49:25 +00:00
|
|
|
/*
|
2017-12-13 17:07:17 +00:00
|
|
|
* Set the IPS bits in TCR_EL1.
|
2014-03-07 08:49:25 +00:00
|
|
|
*/
|
2017-12-13 17:07:17 +00:00
|
|
|
tcr_compute_pa_size x10, #TCR_IPS_SHIFT, x5, x6
|
2015-07-10 16:24:28 +00:00
|
|
|
#ifdef CONFIG_ARM64_HW_AFDBM
|
|
|
|
|
/*
|
2018-03-26 14:12:48 +00:00
|
|
|
* Enable hardware update of the Access Flags bit.
|
|
|
|
|
* Hardware dirty bit management is enabled later,
|
|
|
|
|
* via capabilities.
|
2015-07-10 16:24:28 +00:00
|
|
|
*/
|
|
|
|
|
mrs x9, ID_AA64MMFR1_EL1
|
|
|
|
|
and x9, x9, #0xf
|
2018-03-26 14:12:48 +00:00
|
|
|
cbz x9, 1f
|
|
|
|
|
orr x10, x10, #TCR_HA // hardware Access flag update
|
|
|
|
|
1:
|
2015-07-10 16:24:28 +00:00
|
|
|
#endif /* CONFIG_ARM64_HW_AFDBM */
|
2012-03-05 11:49:28 +00:00
|
|
|
msr tcr_el1, x10
|
|
|
|
|
ret // return to head.S
|
|
|
|
|
ENDPROC(__cpu_setup)
|
