linux/drivers/clk/qcom/Makefile

obj-$(CONFIG_COMMON_CLK_QCOM) += clk-qcom.o

clk-qcom-$(CONFIG_COMMON_CLK_QCOM) += clk-regmap.o
clk-qcom-$(CONFIG_COMMON_CLK_QCOM) += clk-pll.o
clk-qcom-$(CONFIG_COMMON_CLK_QCOM) += clk-rcg.o
clk-qcom-$(CONFIG_COMMON_CLK_QCOM) += clk-rcg2.o
clk-qcom-$(CONFIG_COMMON_CLK_QCOM) += clk-branch.o
clk-qcom-$(CONFIG_COMMON_CLK_QCOM) += reset.o
clk: qcom: Add a regmap type clock struct Add a clock type that associates a regmap pointer and some enable/disable bits with a clk_hw struct. This will be the struct that a hw specific implementation wraps if it wants to use the regmap helper functions. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Mike Turquette <mturquette@linaro.org> 2014-01-15 18:47:23 +00:00			`obj-$(CONFIG_COMMON_CLK_QCOM) += clk-qcom.o`

			`clk-qcom-$(CONFIG_COMMON_CLK_QCOM) += clk-regmap.o`
clk: qcom: Add support for phase locked loops (PLLs) Add support for Qualcomm's PLLs (phase locked loops). This is sufficient enough to be able to determine the rate the PLL is running at. We can add rate setting support later when it's needed. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Mike Turquette <mturquette@linaro.org> 2014-01-15 18:47:24 +00:00			`clk-qcom-$(CONFIG_COMMON_CLK_QCOM) += clk-pll.o`
clk: qcom: Add support for root clock generators (RCGs) Add support for the root clock generators on Qualcomm devices. RCGs are highly customizable mux/divider/counter clocks that can be used to generate almost any rate desired given some input source that is faster than the desired rate. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Mike Turquette <mturquette@linaro.org> 2014-01-15 18:47:25 +00:00			`clk-qcom-$(CONFIG_COMMON_CLK_QCOM) += clk-rcg.o`
			`clk-qcom-$(CONFIG_COMMON_CLK_QCOM) += clk-rcg2.o`
clk: qcom: Add support for branches/gate clocks Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Mike Turquette <mturquette@linaro.org> 2014-01-15 18:47:26 +00:00			`clk-qcom-$(CONFIG_COMMON_CLK_QCOM) += clk-branch.o`
clk: qcom: Add reset controller support Reset controllers and clock controllers are combined into one IP block on Qualcomm chipsets. Usually a reset signal is associated with each clock branch but sometimes a reset signal is associated with a handful of clocks. Either way the register interface is the same; set a bit to assert a reset and clear a bit to deassert a reset. Add support for these types of resets signals. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Mike Turquette <mturquette@linaro.org> 2014-01-15 18:47:27 +00:00			`clk-qcom-$(CONFIG_COMMON_CLK_QCOM) += reset.o`