2014-09-25 09:02:45 +00:00
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/*
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* Copyright (c) 2011-2014 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* EXYNOS - Suspend support
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*
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* Based on arch/arm/mach-s3c2410/pm.c
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* Copyright (c) 2006 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/suspend.h>
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#include <linux/syscore_ops.h>
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#include <linux/cpu_pm.h>
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#include <linux/io.h>
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#include <linux/irqchip/arm-gic.h>
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#include <linux/err.h>
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#include <asm/cacheflush.h>
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#include <asm/hardware/cache-l2x0.h>
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#include <asm/firmware.h>
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#include <asm/smp_scu.h>
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#include <asm/suspend.h>
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#include <plat/pm-common.h>
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#include <plat/regs-srom.h>
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#include "common.h"
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#include "regs-pmu.h"
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#include "regs-sys.h"
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2014-11-07 00:26:47 +00:00
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#include "exynos-pmu.h"
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2014-09-25 09:02:45 +00:00
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#define S5P_CHECK_SLEEP 0x00000BAD
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#define REG_TABLE_END (-1U)
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/**
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* struct exynos_wkup_irq - Exynos GIC to PMU IRQ mapping
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* @hwirq: Hardware IRQ signal of the GIC
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* @mask: Mask in PMU wake-up mask register
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*/
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struct exynos_wkup_irq {
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unsigned int hwirq;
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u32 mask;
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};
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static struct sleep_save exynos5_sys_save[] = {
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SAVE_ITEM(EXYNOS5_SYS_I2C_CFG),
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};
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static struct sleep_save exynos_core_save[] = {
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/* SROM side */
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SAVE_ITEM(S5P_SROM_BW),
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SAVE_ITEM(S5P_SROM_BC0),
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SAVE_ITEM(S5P_SROM_BC1),
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SAVE_ITEM(S5P_SROM_BC2),
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SAVE_ITEM(S5P_SROM_BC3),
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};
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struct exynos_pm_data {
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const struct exynos_wkup_irq *wkup_irq;
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struct sleep_save *extra_save;
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int num_extra_save;
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unsigned int wake_disable_mask;
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unsigned int *release_ret_regs;
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void (*pm_prepare)(void);
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void (*pm_resume)(void);
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int (*pm_suspend)(void);
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int (*cpu_suspend)(unsigned long);
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};
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struct exynos_pm_data *pm_data;
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/*
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* GIC wake-up support
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*/
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static u32 exynos_irqwake_intmask = 0xffffffff;
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static const struct exynos_wkup_irq exynos4_wkup_irq[] = {
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{ 76, BIT(1) }, /* RTC alarm */
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{ 77, BIT(2) }, /* RTC tick */
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{ /* sentinel */ },
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};
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static const struct exynos_wkup_irq exynos5250_wkup_irq[] = {
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{ 75, BIT(1) }, /* RTC alarm */
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{ 76, BIT(2) }, /* RTC tick */
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{ /* sentinel */ },
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};
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unsigned int exynos_release_ret_regs[] = {
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S5P_PAD_RET_MAUDIO_OPTION,
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S5P_PAD_RET_GPIO_OPTION,
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S5P_PAD_RET_UART_OPTION,
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S5P_PAD_RET_MMCA_OPTION,
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S5P_PAD_RET_MMCB_OPTION,
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S5P_PAD_RET_EBIA_OPTION,
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S5P_PAD_RET_EBIB_OPTION,
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REG_TABLE_END,
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};
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static int exynos_irq_set_wake(struct irq_data *data, unsigned int state)
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{
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const struct exynos_wkup_irq *wkup_irq;
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if (!pm_data->wkup_irq)
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return -ENOENT;
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wkup_irq = pm_data->wkup_irq;
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while (wkup_irq->mask) {
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if (wkup_irq->hwirq == data->hwirq) {
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if (!state)
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exynos_irqwake_intmask |= wkup_irq->mask;
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else
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exynos_irqwake_intmask &= ~wkup_irq->mask;
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return 0;
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}
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++wkup_irq;
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}
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return -ENOENT;
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}
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static int exynos_cpu_do_idle(void)
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{
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/* issue the standby signal into the pm unit. */
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cpu_do_idle();
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pr_info("Failed to suspend the system\n");
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return 1; /* Aborting suspend */
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}
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static int exynos_cpu_suspend(unsigned long arg)
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{
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flush_cache_all();
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outer_flush_all();
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return exynos_cpu_do_idle();
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}
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static void exynos_pm_set_wakeup_mask(void)
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{
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/* Set wake-up mask registers */
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pmu_raw_writel(exynos_get_eint_wake_mask(), S5P_EINT_WAKEUP_MASK);
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pmu_raw_writel(exynos_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK);
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}
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static void exynos_pm_enter_sleep_mode(void)
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{
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/* Set value of power down register for sleep mode */
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exynos_sys_powerdown_conf(SYS_SLEEP);
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pmu_raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1);
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/* ensure at least INFORM0 has the resume address */
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pmu_raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0);
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}
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static void exynos_pm_prepare(void)
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{
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/* Set wake-up mask registers */
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exynos_pm_set_wakeup_mask();
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s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save));
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if (pm_data->extra_save)
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s3c_pm_do_save(pm_data->extra_save,
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pm_data->num_extra_save);
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exynos_pm_enter_sleep_mode();
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}
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static int exynos_pm_suspend(void)
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{
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exynos_pm_central_suspend();
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if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
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exynos_cpu_save_register();
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return 0;
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}
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static void exynos_pm_release_retention(void)
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{
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unsigned int i;
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for (i = 0; (pm_data->release_ret_regs[i] != REG_TABLE_END); i++)
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pmu_raw_writel(EXYNOS_WAKEUP_FROM_LOWPWR,
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pm_data->release_ret_regs[i]);
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}
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static void exynos_pm_resume(void)
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{
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u32 cpuid = read_cpuid_part();
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if (exynos_pm_central_resume())
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goto early_wakeup;
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/* For release retention */
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exynos_pm_release_retention();
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if (pm_data->extra_save)
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s3c_pm_do_restore_core(pm_data->extra_save,
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pm_data->num_extra_save);
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s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save));
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if (cpuid == ARM_CPU_PART_CORTEX_A9)
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scu_enable(S5P_VA_SCU);
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if (call_firmware_op(resume) == -ENOSYS
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&& cpuid == ARM_CPU_PART_CORTEX_A9)
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exynos_cpu_restore_register();
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early_wakeup:
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/* Clear SLEEP mode set in INFORM1 */
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pmu_raw_writel(0x0, S5P_INFORM1);
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}
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/*
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* Suspend Ops
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*/
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static int exynos_suspend_enter(suspend_state_t state)
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{
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int ret;
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s3c_pm_debug_init();
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S3C_PMDBG("%s: suspending the system...\n", __func__);
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S3C_PMDBG("%s: wakeup masks: %08x,%08x\n", __func__,
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exynos_irqwake_intmask, exynos_get_eint_wake_mask());
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if (exynos_irqwake_intmask == -1U
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&& exynos_get_eint_wake_mask() == -1U) {
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pr_err("%s: No wake-up sources!\n", __func__);
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pr_err("%s: Aborting sleep\n", __func__);
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return -EINVAL;
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}
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s3c_pm_save_uarts();
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if (pm_data->pm_prepare)
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pm_data->pm_prepare();
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flush_cache_all();
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s3c_pm_check_store();
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ret = call_firmware_op(suspend);
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if (ret == -ENOSYS)
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ret = cpu_suspend(0, pm_data->cpu_suspend);
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if (ret)
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return ret;
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s3c_pm_restore_uarts();
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S3C_PMDBG("%s: wakeup stat: %08x\n", __func__,
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pmu_raw_readl(S5P_WAKEUP_STAT));
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s3c_pm_check_restore();
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S3C_PMDBG("%s: resuming the system...\n", __func__);
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return 0;
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}
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static int exynos_suspend_prepare(void)
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{
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s3c_pm_check_prepare();
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return 0;
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}
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static void exynos_suspend_finish(void)
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{
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s3c_pm_check_cleanup();
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}
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static const struct platform_suspend_ops exynos_suspend_ops = {
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.enter = exynos_suspend_enter,
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.prepare = exynos_suspend_prepare,
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.finish = exynos_suspend_finish,
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.valid = suspend_valid_only_mem,
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};
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static const struct exynos_pm_data exynos4_pm_data = {
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.wkup_irq = exynos4_wkup_irq,
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.wake_disable_mask = ((0xFF << 8) | (0x1F << 1)),
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.release_ret_regs = exynos_release_ret_regs,
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.pm_suspend = exynos_pm_suspend,
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.pm_resume = exynos_pm_resume,
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.pm_prepare = exynos_pm_prepare,
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.cpu_suspend = exynos_cpu_suspend,
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};
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static const struct exynos_pm_data exynos5250_pm_data = {
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.wkup_irq = exynos5250_wkup_irq,
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.wake_disable_mask = ((0xFF << 8) | (0x1F << 1)),
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.release_ret_regs = exynos_release_ret_regs,
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.extra_save = exynos5_sys_save,
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.num_extra_save = ARRAY_SIZE(exynos5_sys_save),
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.pm_suspend = exynos_pm_suspend,
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.pm_resume = exynos_pm_resume,
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.pm_prepare = exynos_pm_prepare,
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.cpu_suspend = exynos_cpu_suspend,
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};
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static struct of_device_id exynos_pmu_of_device_ids[] = {
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{
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.compatible = "samsung,exynos4210-pmu",
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.data = &exynos4_pm_data,
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}, {
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.compatible = "samsung,exynos4212-pmu",
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.data = &exynos4_pm_data,
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}, {
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.compatible = "samsung,exynos4412-pmu",
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.data = &exynos4_pm_data,
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}, {
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.compatible = "samsung,exynos5250-pmu",
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.data = &exynos5250_pm_data,
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},
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{ /*sentinel*/ },
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};
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static struct syscore_ops exynos_pm_syscore_ops;
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void __init exynos_pm_init(void)
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{
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const struct of_device_id *match;
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u32 tmp;
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of_find_matching_node_and_match(NULL, exynos_pmu_of_device_ids, &match);
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if (!match) {
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pr_err("Failed to find PMU node\n");
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return;
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}
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pm_data = (struct exynos_pm_data *) match->data;
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/* Platform-specific GIC callback */
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gic_arch_extn.irq_set_wake = exynos_irq_set_wake;
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/* All wakeup disable */
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tmp = pmu_raw_readl(S5P_WAKEUP_MASK);
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tmp |= pm_data->wake_disable_mask;
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pmu_raw_writel(tmp, S5P_WAKEUP_MASK);
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exynos_pm_syscore_ops.suspend = pm_data->pm_suspend;
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exynos_pm_syscore_ops.resume = pm_data->pm_resume;
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register_syscore_ops(&exynos_pm_syscore_ops);
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suspend_set_ops(&exynos_suspend_ops);
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}
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