2005-09-26 06:04:21 +00:00
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#
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# Makefile for the linux kernel.
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#
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2007-12-20 11:58:00 +00:00
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CFLAGS_ptrace.o += -DUTS_MACHINE='"$(UTS_MACHINE)"'
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2009-06-09 20:48:51 +00:00
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subdir-ccflags-$(CONFIG_PPC_WERROR) := -Werror
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2005-09-30 03:51:25 +00:00
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ifeq ($(CONFIG_PPC64),y)
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2007-11-07 05:13:29 +00:00
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CFLAGS_prom_init.o += -mno-minimal-toc
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2005-09-30 03:51:25 +00:00
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endif
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2005-09-30 06:16:52 +00:00
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ifeq ($(CONFIG_PPC32),y)
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2005-10-06 02:06:20 +00:00
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CFLAGS_prom_init.o += -fPIC
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2005-10-06 03:24:50 +00:00
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CFLAGS_btext.o += -fPIC
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2005-09-30 06:16:52 +00:00
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endif
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2005-10-06 02:06:20 +00:00
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2008-10-06 23:06:12 +00:00
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ifdef CONFIG_FUNCTION_TRACER
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2008-05-15 03:49:44 +00:00
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# Do not trace early boot code
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2008-09-02 06:50:38 +00:00
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CFLAGS_REMOVE_cputable.o = -pg -mno-sched-epilog
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CFLAGS_REMOVE_prom_init.o = -pg -mno-sched-epilog
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CFLAGS_REMOVE_btext.o = -pg -mno-sched-epilog
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2008-11-26 20:54:46 +00:00
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CFLAGS_REMOVE_prom.o = -pg -mno-sched-epilog
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2009-02-10 05:10:27 +00:00
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# do not trace tracer code
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2008-09-02 06:50:38 +00:00
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CFLAGS_REMOVE_ftrace.o = -pg -mno-sched-epilog
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2009-02-10 05:10:27 +00:00
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# timers used by tracing
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CFLAGS_REMOVE_time.o = -pg -mno-sched-epilog
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2008-05-15 03:49:44 +00:00
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endif
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2008-03-08 02:55:58 +00:00
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obj-y := cputable.o ptrace.o syscalls.o \
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2006-01-12 10:22:34 +00:00
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irq.o align.o signal_32.o pmc.o vdso.o \
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2007-06-04 05:15:49 +00:00
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init_task.o process.o systbl.o idle.o \
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2008-12-23 18:55:54 +00:00
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signal.o sysfs.o cacheinfo.o
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2005-11-11 10:15:21 +00:00
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obj-y += vdso32/
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2008-01-03 01:03:11 +00:00
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obj-$(CONFIG_PPC64) += setup_64.o sys_ppc32.o \
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2006-02-10 05:02:20 +00:00
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signal_64.o ptrace32.o \
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2009-07-23 23:15:59 +00:00
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paca.o nvram_64.o firmware.o
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obj-$(CONFIG_PPC_BOOK3S_64) += cpu_setup_ppc970.o cpu_setup_pa6t.o
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powerpc: Make the 64-bit kernel as a position-independent executable
This implements CONFIG_RELOCATABLE for 64-bit by making the kernel as
a position-independent executable (PIE) when it is set. This involves
processing the dynamic relocations in the image in the early stages of
booting, even if the kernel is being run at the address it is linked at,
since the linker does not necessarily fill in words in the image for
which there are dynamic relocations. (In fact the linker does fill in
such words for 64-bit executables, though not for 32-bit executables,
so in principle we could avoid calling relocate() entirely when we're
running a 64-bit kernel at the linked address.)
The dynamic relocations are processed by a new function relocate(addr),
where the addr parameter is the virtual address where the image will be
run. In fact we call it twice; once before calling prom_init, and again
when starting the main kernel. This means that reloc_offset() returns
0 in prom_init (since it has been relocated to the address it is running
at), which necessitated a few adjustments.
This also changes __va and __pa to use an equivalent definition that is
simpler. With the relocatable kernel, PAGE_OFFSET and MEMORY_START are
constants (for 64-bit) whereas PHYSICAL_START is a variable (and
KERNELBASE ideally should be too, but isn't yet).
With this, relocatable kernels still copy themselves down to physical
address 0 and run there.
Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-08-30 01:43:47 +00:00
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obj64-$(CONFIG_RELOCATABLE) += reloc_64.o
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2009-07-23 23:15:59 +00:00
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obj-$(CONFIG_PPC_BOOK3E_64) += exceptions-64e.o
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2005-11-11 10:15:21 +00:00
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obj-$(CONFIG_PPC64) += vdso64/
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2009-06-02 21:17:37 +00:00
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obj-$(CONFIG_ALTIVEC) += vecemu.o
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2006-04-18 11:49:11 +00:00
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obj-$(CONFIG_PPC_970_NAP) += idle_power4.o
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2006-11-11 06:24:59 +00:00
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obj-$(CONFIG_PPC_OF) += of_device.o of_platform.o prom_parse.o
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2007-09-20 14:00:11 +00:00
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obj-$(CONFIG_PPC_CLOCK) += clock.o
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2005-11-10 04:26:20 +00:00
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procfs-$(CONFIG_PPC64) := proc_ppc64.o
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obj-$(CONFIG_PROC_FS) += $(procfs-y)
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2007-03-04 06:04:44 +00:00
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rtaspci-$(CONFIG_PPC64)-$(CONFIG_PCI) := rtas_pci.o
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obj-$(CONFIG_PPC_RTAS) += rtas.o rtas-rtc.o $(rtaspci-y-y)
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2005-11-03 03:41:19 +00:00
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obj-$(CONFIG_RTAS_FLASH) += rtas_flash.o
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obj-$(CONFIG_RTAS_PROC) += rtas-proc.o
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2005-11-10 04:26:20 +00:00
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obj-$(CONFIG_LPARCFG) += lparcfg.o
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2005-10-24 04:22:37 +00:00
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obj-$(CONFIG_IBMVIO) += vio.o
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2005-11-16 07:56:43 +00:00
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obj-$(CONFIG_IBMEBUS) += ibmebus.o
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2005-11-04 02:28:58 +00:00
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obj-$(CONFIG_GENERIC_TBSYNC) += smp-tbsync.o
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2005-12-04 07:39:37 +00:00
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obj-$(CONFIG_CRASH_DUMP) += crash_dump.o
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2008-06-18 21:26:52 +00:00
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obj-$(CONFIG_E500) += idle_e500.o
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2006-03-27 08:15:26 +00:00
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obj-$(CONFIG_6xx) += idle_6xx.o l2cr_6xx.o cpu_setup_6xx.o
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obj-$(CONFIG_TAU) += tau_6xx.o
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2007-09-21 00:16:20 +00:00
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obj-$(CONFIG_HIBERNATION) += swsusp.o suspend.o \
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swsusp_$(CONFIG_WORD_SIZE).o
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obj64-$(CONFIG_HIBERNATION) += swsusp_asm64.o
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2008-06-20 16:31:01 +00:00
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obj-$(CONFIG_MODULES) += module.o module_$(CONFIG_WORD_SIZE).o
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2007-10-04 01:02:09 +00:00
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obj-$(CONFIG_44x) += cpu_setup_44x.o
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2009-02-12 13:54:53 +00:00
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obj-$(CONFIG_FSL_BOOKE) += cpu_setup_fsl_booke.o dbell.o
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2005-10-10 12:50:37 +00:00
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2009-07-23 23:15:59 +00:00
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extra-y := head_$(CONFIG_WORD_SIZE).o
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extra-$(CONFIG_PPC_BOOK3E_32) := head_new_booke.o
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2007-08-20 12:27:07 +00:00
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extra-$(CONFIG_40x) := head_40x.o
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2005-09-26 06:04:21 +00:00
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extra-$(CONFIG_44x) := head_44x.o
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extra-$(CONFIG_FSL_BOOKE) := head_fsl_booke.o
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extra-$(CONFIG_8xx) := head_8xx.o
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extra-y += vmlinux.lds
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2006-06-28 01:55:49 +00:00
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obj-y += time.o prom.o traps.o setup-common.o \
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powerpc: Merge 32 and 64-bit dma code
We essentially adopt the 64-bit dma code, with some changes to support
32-bit systems, including HIGHMEM. dma functions on 32-bit are now
invoked via accessor functions which call the correct op for a device based
on archdata dma_ops. If there is no archdata dma_ops, this defaults
to dma_direct_ops.
In addition, the dma_map/unmap_page functions are added to dma_ops
because we can't just fall back on map/unmap_single when HIGHMEM is
enabled. In the case of dma_direct_*, we stop using map/unmap_single
and just use the page version - this saves a lot of ugly
ifdeffing. We leave map/unmap_single in the dma_ops definition,
though, because they are needed by the iommu code, which does not
implement map/unmap_page. Ideally, going forward, we will completely
eliminate map/unmap_single and just have map/unmap_page, if it's
workable for 64-bit.
Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-09-12 10:34:46 +00:00
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udbg.o misc.o io.o dma.o \
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2007-09-21 00:16:20 +00:00
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misc_$(CONFIG_WORD_SIZE).o
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obj-$(CONFIG_PPC32) += entry_32.o setup_32.o
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powerpc: Merge 32 and 64-bit dma code
We essentially adopt the 64-bit dma code, with some changes to support
32-bit systems, including HIGHMEM. dma functions on 32-bit are now
invoked via accessor functions which call the correct op for a device based
on archdata dma_ops. If there is no archdata dma_ops, this defaults
to dma_direct_ops.
In addition, the dma_map/unmap_page functions are added to dma_ops
because we can't just fall back on map/unmap_single when HIGHMEM is
enabled. In the case of dma_direct_*, we stop using map/unmap_single
and just use the page version - this saves a lot of ugly
ifdeffing. We leave map/unmap_single in the dma_ops definition,
though, because they are needed by the iommu code, which does not
implement map/unmap_page. Ideally, going forward, we will completely
eliminate map/unmap_single and just have map/unmap_page, if it's
workable for 64-bit.
Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-09-12 10:34:46 +00:00
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obj-$(CONFIG_PPC64) += dma-iommu.o iommu.o
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2008-07-23 16:30:15 +00:00
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obj-$(CONFIG_KGDB) += kgdb.o
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2009-03-10 17:53:27 +00:00
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obj-$(CONFIG_PPC_OF_BOOT_TRAMPOLINE) += prom_init.o
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2005-09-28 10:28:14 +00:00
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obj-$(CONFIG_MODULES) += ppc_ksyms.o
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2005-10-06 02:06:20 +00:00
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obj-$(CONFIG_BOOTX_TEXT) += btext.o
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2005-11-04 23:33:55 +00:00
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obj-$(CONFIG_SMP) += smp.o
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2005-11-14 06:30:17 +00:00
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obj-$(CONFIG_KPROBES) += kprobes.o
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2006-01-10 05:19:05 +00:00
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obj-$(CONFIG_PPC_UDBG_16550) += legacy_serial.o udbg_16550.o
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2008-04-17 04:35:00 +00:00
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obj-$(CONFIG_STACKTRACE) += stacktrace.o
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2009-05-14 12:42:28 +00:00
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obj-$(CONFIG_SWIOTLB) += dma-swiotlb.o
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2006-11-11 06:24:53 +00:00
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2007-09-21 00:16:20 +00:00
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pci64-$(CONFIG_PPC64) += pci_dn.o isa-bridge.o
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obj-$(CONFIG_PCI) += pci_$(CONFIG_WORD_SIZE).o $(pci64-y) \
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pci-common.o
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2007-05-08 02:58:34 +00:00
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obj-$(CONFIG_PCI_MSI) += msi.o
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2007-09-21 00:16:20 +00:00
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obj-$(CONFIG_KEXEC) += machine_kexec.o crash.o \
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machine_kexec_$(CONFIG_WORD_SIZE).o
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2006-08-31 23:02:42 +00:00
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obj-$(CONFIG_AUDIT) += audit.o
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obj64-$(CONFIG_AUDIT) += compat_audit.o
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2005-09-30 06:16:52 +00:00
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2008-05-15 03:49:44 +00:00
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obj-$(CONFIG_DYNAMIC_FTRACE) += ftrace.o
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2009-02-10 05:10:27 +00:00
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obj-$(CONFIG_FUNCTION_GRAPH_TRACER) += ftrace.o
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perf_counter: powerpc: Add callchain support
This adds support for tracing callchains for powerpc, both 32-bit
and 64-bit, and both in the kernel and userspace, from PMU interrupt
context.
The first three entries stored for each callchain are the NIP (next
instruction pointer), LR (link register), and the contents of the LR
save area in the second stack frame (the first is ignored because the
ABI convention on powerpc is that functions save their return address
in their caller's stack frame). Because leaf functions don't have to
save their return address (LR value) and don't have to establish a
stack frame, it's possible for either or both of LR and the second
stack frame's LR save area to have valid return addresses in them.
This is basically impossible to disambiguate without either reading
the code or looking at auxiliary information such as CFI tables.
Since we don't want to do either of those things at interrupt time,
we store both LR and the second stack frame's LR save area.
Once we get past the second stack frame, there is no ambiguity; all
return addresses we get are reliable.
For kernel traces, we check whether they are valid kernel instruction
addresses and store zero instead if they are not (rather than
omitting them, which would make it impossible for userspace to know
which was which). We also store zero instead of the second stack
frame's LR save area value if it is the same as LR.
For kernel traces, we check for interrupt frames, and for user traces,
we check for signal frames. In each case, since we're starting a new
trace, we store a PERF_CONTEXT_KERNEL/USER marker so that userspace
knows that the next three entries are NIP, LR and the second stack frame
for the interrupted context.
We read user memory with __get_user_inatomic. On 64-bit, if this
PMU interrupt occurred while interrupts are soft-disabled, and
there is no MMU hash table entry for the page, we will get an
-EFAULT return from __get_user_inatomic even if there is a valid
Linux PTE for the page, since hash_page isn't reentrant. Thus we
have code here to read the Linux PTE and access the page via the
kernel linear mapping. Since 64-bit doesn't use (or need) highmem
there is no need to do kmap_atomic. On 32-bit, we don't do soft
interrupt disabling, so this complication doesn't occur and there
is no need to fall back to reading the Linux PTE, since hash_page
(or the TLB miss handler) will get called automatically if necessary.
Note that we cannot get PMU interrupts in the interval during
context switch between switch_mm (which switches the user address
space) and switch_to (which actually changes current to the new
process). On 64-bit this is because interrupts are hard-disabled
in switch_mm and stay hard-disabled until they are soft-enabled
later, after switch_to has returned. So there is no possibility
of trying to do a user stack trace when the user address space is
not current's address space.
Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2009-08-17 22:25:32 +00:00
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obj-$(CONFIG_PPC_PERF_CTRS) += perf_counter.o perf_callchain.o
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2009-06-17 11:50:04 +00:00
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obj64-$(CONFIG_PPC_PERF_CTRS) += power4-pmu.o ppc970-pmu.o power5-pmu.o \
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power5+-pmu.o power6-pmu.o power7-pmu.o
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perf_counter: powerpc: Add processor back-end for MPC7450 family
This adds support for the performance monitor hardware on the
MPC7450 family of processors (7450, 7451, 7455, 7447/7457, 7447A,
7448), used in the later Apple G4 powermacs/powerbooks and other
machines. These machines have 6 hardware counters with a unique
set of events which can be counted on each counter, with some
events being available on multiple counters.
Raw event codes for these processors are (PMC << 8) + PMCSEL.
If PMC is non-zero then the event is that selected by the given
PMCSEL value for that PMC (hardware counter). If PMC is zero
then the event selected is one of the low-numbered ones that are
common to several PMCs. In this case PMCSEL must be <= 22 and
the event is what that PMCSEL value would select on PMC1 (but
it may be placed any other PMC that has the same event for that
PMCSEL value).
For events that count cycles or occurrences that exceed a threshold,
the threshold requested can be specified in the 0x3f000 bits of the
raw event codes. If the event uses the threshold multiplier bit
and that bit should be set, that is indicated with the 0x40000 bit
of the raw event code.
This fills in some of the generic cache events. Unfortunately there
are quite a few blank spaces in the table, partly because these
processors tend to count cache hits rather than cache accesses.
Signed-off-by: Paul Mackerras <paulus@samba.org>
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: linuxppc-dev@ozlabs.org
Cc: benh@kernel.crashing.org
LKML-Reference: <19000.55631.802122.696927@cargo.ozlabs.ibm.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2009-06-17 11:53:51 +00:00
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obj32-$(CONFIG_PPC_PERF_CTRS) += mpc7450-pmu.o
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2008-05-15 03:49:44 +00:00
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2007-09-18 20:29:35 +00:00
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obj-$(CONFIG_8XX_MINIMAL_FPEMU) += softemu8xx.o
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[POWERPC] Allow hooking of PCI MMIO & PIO accessors on 64 bits
This patch reworks the way iSeries hooks on PCI IO operations (both MMIO
and PIO) and provides a generic way for other platforms to do so (we
have need to do that for various other platforms).
While reworking the IO ops, I ended up doing some spring cleaning in
io.h and eeh.h which I might want to split into 2 or 3 patches (among
others, eeh.h had a lot of useless stuff in it).
A side effect is that EEH for PIO should work now (it used to pass IO
ports down to the eeh address check functions which is bogus).
Also, new are MMIO "repeat" ops, which other archs like ARM already had,
and that we have too now: readsb, readsw, readsl, writesb, writesw,
writesl.
In the long run, I might also make EEH use the hooks instead
of wrapping at the toplevel, which would make things even cleaner and
relegate EEH completely in platforms/iseries, but we have to measure the
performance impact there (though it's really only on MMIO reads)
Since I also need to hook on ioremap, I shuffled the functions a bit
there. I introduced ioremap_flags() to use by drivers who want to pass
explicit flags to ioremap (and it can be hooked). The old __ioremap() is
still there as a low level and cannot be hooked, thus drivers who use it
should migrate unless they know they want the low level version.
The patch "arch provides generic iomap missing accessors" (should be
number 4 in this series) is a pre-requisite to provide full iomap
API support with this patch.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-11-11 06:25:10 +00:00
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ifneq ($(CONFIG_PPC_INDIRECT_IO),y)
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2006-11-12 22:27:39 +00:00
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obj-y += iomap.o
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[POWERPC] Allow hooking of PCI MMIO & PIO accessors on 64 bits
This patch reworks the way iSeries hooks on PCI IO operations (both MMIO
and PIO) and provides a generic way for other platforms to do so (we
have need to do that for various other platforms).
While reworking the IO ops, I ended up doing some spring cleaning in
io.h and eeh.h which I might want to split into 2 or 3 patches (among
others, eeh.h had a lot of useless stuff in it).
A side effect is that EEH for PIO should work now (it used to pass IO
ports down to the eeh address check functions which is bogus).
Also, new are MMIO "repeat" ops, which other archs like ARM already had,
and that we have too now: readsb, readsw, readsl, writesb, writesw,
writesl.
In the long run, I might also make EEH use the hooks instead
of wrapping at the toplevel, which would make things even cleaner and
relegate EEH completely in platforms/iseries, but we have to measure the
performance impact there (though it's really only on MMIO reads)
Since I also need to hook on ioremap, I shuffled the functions a bit
there. I introduced ioremap_flags() to use by drivers who want to pass
explicit flags to ioremap (and it can be hooked). The old __ioremap() is
still there as a low level and cannot be hooked, thus drivers who use it
should migrate unless they know they want the low level version.
The patch "arch provides generic iomap missing accessors" (should be
number 4 in this series) is a pre-requisite to provide full iomap
API support with this patch.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-11-11 06:25:10 +00:00
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endif
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2005-11-18 04:43:34 +00:00
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obj-$(CONFIG_PPC64) += $(obj64-y)
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perf_counter: powerpc: Add processor back-end for MPC7450 family
This adds support for the performance monitor hardware on the
MPC7450 family of processors (7450, 7451, 7455, 7447/7457, 7447A,
7448), used in the later Apple G4 powermacs/powerbooks and other
machines. These machines have 6 hardware counters with a unique
set of events which can be counted on each counter, with some
events being available on multiple counters.
Raw event codes for these processors are (PMC << 8) + PMCSEL.
If PMC is non-zero then the event is that selected by the given
PMCSEL value for that PMC (hardware counter). If PMC is zero
then the event selected is one of the low-numbered ones that are
common to several PMCs. In this case PMCSEL must be <= 22 and
the event is what that PMCSEL value would select on PMC1 (but
it may be placed any other PMC that has the same event for that
PMCSEL value).
For events that count cycles or occurrences that exceed a threshold,
the threshold requested can be specified in the 0x3f000 bits of the
raw event codes. If the event uses the threshold multiplier bit
and that bit should be set, that is indicated with the 0x40000 bit
of the raw event code.
This fills in some of the generic cache events. Unfortunately there
are quite a few blank spaces in the table, partly because these
processors tend to count cache hits rather than cache accesses.
Signed-off-by: Paul Mackerras <paulus@samba.org>
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: linuxppc-dev@ozlabs.org
Cc: benh@kernel.crashing.org
LKML-Reference: <19000.55631.802122.696927@cargo.ozlabs.ibm.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2009-06-17 11:53:51 +00:00
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|
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obj-$(CONFIG_PPC32) += $(obj32-y)
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2005-11-18 04:43:34 +00:00
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|
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2008-12-17 10:09:01 +00:00
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|
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ifneq ($(CONFIG_XMON)$(CONFIG_KEXEC),)
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2008-12-17 10:08:55 +00:00
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|
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obj-y += ppc_save_regs.o
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|
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endif
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2009-08-09 19:02:51 +00:00
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|
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# Disable GCOV in odd or sensitive code
|
|
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GCOV_PROFILE_prom_init.o := n
|
|
|
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GCOV_PROFILE_ftrace.o := n
|
|
|
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GCOV_PROFILE_machine_kexec_64.o := n
|
|
|
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GCOV_PROFILE_machine_kexec_32.o := n
|
|
|
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GCOV_PROFILE_kprobes.o := n
|
|
|
|
|
[PATCH] powerpc: Fix handling of fpscr on 64-bit
The recent merge of fpu.S broken the handling of fpscr for
ARCH=powerpc and CONFIG_PPC64=y. FP registers could be corrupted,
leading to strange random application crashes.
The confusion arises, because the thread_struct has (and requires) a
64-bit area to save the fpscr, because we use load/store double
instructions to get it in to/out of the FPU. However, only the low
32-bits are actually used, so we want to treat it as a 32-bit quantity
when manipulating its bits to avoid extra load/stores on 32-bit. This
patch replaces the current definition with a structure of two 32-bit
quantities (pad and val), to clarify things as much as is possible.
The 'val' field is used when manipulating bits, the structure itself
is used when obtaining the address for loading/unloading the value
from the FPU.
While we're at it, consolidate the 4 (!) almost identical versions of
cvt_fd() and cvt_df() (arch/ppc/kernel/misc.S,
arch/ppc64/kernel/misc.S, arch/powerpc/kernel/misc_32.S,
arch/powerpc/kernel/misc_64.S) into a single version in fpu.S. The
new version takes a pointer to thread_struct and applies the correct
offset itself, rather than a pointer to the fpscr field itself, again
to avoid confusion as to which is the correct field to use.
Finally, this patch makes ARCH=ppc64 also use the consolidated fpu.S
code, which it previously did not.
Built for G5 (ARCH=ppc64 and ARCH=powerpc), 32-bit powermac (ARCH=ppc
and ARCH=powerpc) and Walnut (ARCH=ppc, CONFIG_MATH_EMULATION=y).
Booted on G5 (ARCH=powerpc) and things which previously fell over no
longer do.
Signed-off-by: David Gibson <dwg@au1.ibm.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2005-10-27 06:27:25 +00:00
|
|
|
extra-$(CONFIG_PPC_FPU) += fpu.o
|
2009-06-02 21:17:37 +00:00
|
|
|
extra-$(CONFIG_ALTIVEC) += vector.o
|
2005-10-28 02:51:45 +00:00
|
|
|
extra-$(CONFIG_PPC64) += entry_64.o
|
2008-01-07 05:12:44 +00:00
|
|
|
|
|
|
|
extra-y += systbl_chk.i
|
|
|
|
$(obj)/systbl.o: systbl_chk
|
|
|
|
|
|
|
|
quiet_cmd_systbl_chk = CALL $<
|
|
|
|
cmd_systbl_chk = $(CONFIG_SHELL) $< $(obj)/systbl_chk.i
|
|
|
|
|
|
|
|
PHONY += systbl_chk
|
|
|
|
systbl_chk: $(src)/systbl_chk.sh $(obj)/systbl_chk.i
|
|
|
|
$(call cmd,systbl_chk)
|
2008-02-11 15:32:00 +00:00
|
|
|
|
2009-06-11 02:12:28 +00:00
|
|
|
ifeq ($(CONFIG_PPC_OF_BOOT_TRAMPOLINE),y)
|
2008-04-24 02:08:22 +00:00
|
|
|
$(obj)/built-in.o: prom_init_check
|
|
|
|
|
|
|
|
quiet_cmd_prom_init_check = CALL $<
|
|
|
|
cmd_prom_init_check = $(CONFIG_SHELL) $< "$(NM)" "$(obj)/prom_init.o"
|
|
|
|
|
|
|
|
PHONY += prom_init_check
|
|
|
|
prom_init_check: $(src)/prom_init_check.sh $(obj)/prom_init.o
|
|
|
|
$(call cmd,prom_init_check)
|
2009-06-11 02:12:28 +00:00
|
|
|
endif
|
2008-04-24 02:08:22 +00:00
|
|
|
|
2008-02-11 15:32:00 +00:00
|
|
|
clean-files := vmlinux.lds
|