2018-12-28 08:32:28 +00:00
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/* SPDX-License-Identifier: GPL-2.0+ WITH GCC-exception-2.0
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*
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* Copyright (C) 2006 Free Software Foundation, Inc.
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*/
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2008-11-18 08:33:48 +00:00
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/* Moderately Space-optimized libgcc routines for the Renesas SH /
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STMicroelectronics ST40 CPUs.
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Contributed by J"orn Rennecke joern.rennecke@st.com. */
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/* Size: 186 bytes jointly for udivsi3_i4i and sdivsi3_i4i
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sh4-200 run times:
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udiv small divisor: 55 cycles
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udiv large divisor: 52 cycles
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sdiv small divisor, positive result: 59 cycles
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sdiv large divisor, positive result: 56 cycles
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sdiv small divisor, negative result: 65 cycles (*)
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sdiv large divisor, negative result: 62 cycles (*)
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(*): r2 is restored in the rts delay slot and has a lingering latency
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of two more cycles. */
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.balign 4
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.global __udivsi3_i4i
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2008-11-20 06:26:35 +00:00
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.global __udivsi3_i4
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.set __udivsi3_i4, __udivsi3_i4i
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2008-11-18 08:33:48 +00:00
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.type __udivsi3_i4i, @function
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.type __sdivsi3_i4i, @function
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__udivsi3_i4i:
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sts pr,r1
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mov.l r4,@-r15
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extu.w r5,r0
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cmp/eq r5,r0
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swap.w r4,r0
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shlr16 r4
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bf/s large_divisor
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div0u
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mov.l r5,@-r15
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shll16 r5
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sdiv_small_divisor:
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div1 r5,r4
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bsr div6
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div1 r5,r4
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div1 r5,r4
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bsr div6
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div1 r5,r4
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xtrct r4,r0
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xtrct r0,r4
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bsr div7
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swap.w r4,r4
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div1 r5,r4
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bsr div7
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div1 r5,r4
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xtrct r4,r0
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mov.l @r15+,r5
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swap.w r0,r0
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mov.l @r15+,r4
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jmp @r1
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rotcl r0
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div7:
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div1 r5,r4
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div6:
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div1 r5,r4; div1 r5,r4; div1 r5,r4
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div1 r5,r4; div1 r5,r4; rts; div1 r5,r4
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divx3:
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rotcl r0
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div1 r5,r4
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rotcl r0
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div1 r5,r4
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rotcl r0
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rts
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div1 r5,r4
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large_divisor:
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mov.l r5,@-r15
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sdiv_large_divisor:
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xor r4,r0
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.rept 4
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rotcl r0
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bsr divx3
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div1 r5,r4
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.endr
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mov.l @r15+,r5
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mov.l @r15+,r4
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jmp @r1
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rotcl r0
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.global __sdivsi3_i4i
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2008-11-20 06:26:35 +00:00
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.global __sdivsi3_i4
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2008-11-18 08:33:48 +00:00
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.global __sdivsi3
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2008-11-20 06:26:35 +00:00
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.set __sdivsi3_i4, __sdivsi3_i4i
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2008-11-18 08:33:48 +00:00
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.set __sdivsi3, __sdivsi3_i4i
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__sdivsi3_i4i:
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mov.l r4,@-r15
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cmp/pz r5
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mov.l r5,@-r15
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bt/s pos_divisor
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cmp/pz r4
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neg r5,r5
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extu.w r5,r0
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bt/s neg_result
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cmp/eq r5,r0
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neg r4,r4
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pos_result:
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swap.w r4,r0
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bra sdiv_check_divisor
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sts pr,r1
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pos_divisor:
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extu.w r5,r0
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bt/s pos_result
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cmp/eq r5,r0
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neg r4,r4
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neg_result:
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mova negate_result,r0
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;
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mov r0,r1
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swap.w r4,r0
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lds r2,macl
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sts pr,r2
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sdiv_check_divisor:
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shlr16 r4
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bf/s sdiv_large_divisor
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div0u
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bra sdiv_small_divisor
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shll16 r5
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.balign 4
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negate_result:
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neg r0,r0
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jmp @r2
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sts macl,r2
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