2019-03-29 04:14:03 +00:00
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Phy provider for USB 3.0 controller on HiSilicon 3660 platform
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*
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* Copyright (C) 2017-2018 Hilisicon Electronics Co., Ltd.
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* http://www.huawei.com
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*
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* Authors: Yu Chen <chenyu56@huawei.com>
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*/
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#include <linux/kernel.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#define PERI_CRG_CLK_EN4 0x40
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#define PERI_CRG_CLK_DIS4 0x44
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#define GT_CLK_USB3OTG_REF BIT(0)
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#define GT_ACLK_USB3OTG BIT(1)
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#define PERI_CRG_RSTEN4 0x90
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#define PERI_CRG_RSTDIS4 0x94
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#define IP_RST_USB3OTGPHY_POR BIT(3)
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#define IP_RST_USB3OTG BIT(5)
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#define PERI_CRG_ISODIS 0x148
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#define USB_REFCLK_ISO_EN BIT(25)
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#define PCTRL_PERI_CTRL3 0x10
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#define PCTRL_PERI_CTRL3_MSK_START 16
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#define USB_TCXO_EN BIT(1)
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#define PCTRL_PERI_CTRL24 0x64
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#define SC_CLK_USB3PHY_3MUX1_SEL BIT(25)
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#define USBOTG3_CTRL0 0x00
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#define SC_USB3PHY_ABB_GT_EN BIT(15)
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#define USBOTG3_CTRL2 0x08
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#define USBOTG3CTRL2_POWERDOWN_HSP BIT(0)
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#define USBOTG3CTRL2_POWERDOWN_SSP BIT(1)
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#define USBOTG3_CTRL3 0x0C
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#define USBOTG3_CTRL3_VBUSVLDEXT BIT(6)
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#define USBOTG3_CTRL3_VBUSVLDEXTSEL BIT(5)
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#define USBOTG3_CTRL4 0x10
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#define USBOTG3_CTRL7 0x1c
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#define REF_SSP_EN BIT(16)
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/* This value config the default txtune parameter of the usb 2.0 phy */
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#define HI3660_USB_DEFAULT_PHY_PARAM 0x1c466e3
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struct hi3660_priv {
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struct device *dev;
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struct regmap *peri_crg;
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struct regmap *pctrl;
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struct regmap *otg_bc;
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u32 eye_diagram_param;
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};
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static int hi3660_phy_init(struct phy *phy)
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{
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struct hi3660_priv *priv = phy_get_drvdata(phy);
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u32 val, mask;
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int ret;
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/* usb refclk iso disable */
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ret = regmap_write(priv->peri_crg, PERI_CRG_ISODIS, USB_REFCLK_ISO_EN);
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if (ret)
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goto out;
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/* enable usb_tcxo_en */
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val = USB_TCXO_EN | (USB_TCXO_EN << PCTRL_PERI_CTRL3_MSK_START);
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ret = regmap_write(priv->pctrl, PCTRL_PERI_CTRL3, val);
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if (ret)
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goto out;
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/* assert phy */
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val = IP_RST_USB3OTGPHY_POR | IP_RST_USB3OTG;
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ret = regmap_write(priv->peri_crg, PERI_CRG_RSTEN4, val);
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if (ret)
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goto out;
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/* enable phy ref clk */
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val = SC_USB3PHY_ABB_GT_EN;
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mask = val;
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ret = regmap_update_bits(priv->otg_bc, USBOTG3_CTRL0, mask, val);
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if (ret)
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goto out;
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val = REF_SSP_EN;
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mask = val;
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ret = regmap_update_bits(priv->otg_bc, USBOTG3_CTRL7, mask, val);
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if (ret)
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goto out;
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/* exit from IDDQ mode */
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mask = USBOTG3CTRL2_POWERDOWN_HSP | USBOTG3CTRL2_POWERDOWN_SSP;
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ret = regmap_update_bits(priv->otg_bc, USBOTG3_CTRL2, mask, 0);
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if (ret)
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goto out;
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/* delay for exit from IDDQ mode */
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usleep_range(100, 120);
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/* deassert phy */
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val = IP_RST_USB3OTGPHY_POR | IP_RST_USB3OTG;
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ret = regmap_write(priv->peri_crg, PERI_CRG_RSTDIS4, val);
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if (ret)
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goto out;
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/* delay for phy deasserted */
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usleep_range(10000, 15000);
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/* fake vbus valid signal */
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val = USBOTG3_CTRL3_VBUSVLDEXT | USBOTG3_CTRL3_VBUSVLDEXTSEL;
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mask = val;
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ret = regmap_update_bits(priv->otg_bc, USBOTG3_CTRL3, mask, val);
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if (ret)
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goto out;
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/* delay for vbus valid */
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usleep_range(100, 120);
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ret = regmap_write(priv->otg_bc, USBOTG3_CTRL4,
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priv->eye_diagram_param);
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if (ret)
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goto out;
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return 0;
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out:
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dev_err(priv->dev, "failed to init phy ret: %d\n", ret);
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return ret;
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}
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static int hi3660_phy_exit(struct phy *phy)
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{
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struct hi3660_priv *priv = phy_get_drvdata(phy);
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u32 val;
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int ret;
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/* assert phy */
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val = IP_RST_USB3OTGPHY_POR;
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ret = regmap_write(priv->peri_crg, PERI_CRG_RSTEN4, val);
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if (ret)
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goto out;
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/* disable usb_tcxo_en */
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val = USB_TCXO_EN << PCTRL_PERI_CTRL3_MSK_START;
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ret = regmap_write(priv->pctrl, PCTRL_PERI_CTRL3, val);
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if (ret)
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goto out;
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return 0;
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out:
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dev_err(priv->dev, "failed to exit phy ret: %d\n", ret);
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return ret;
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}
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2020-08-23 22:00:20 +00:00
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static const struct phy_ops hi3660_phy_ops = {
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2019-03-29 04:14:03 +00:00
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.init = hi3660_phy_init,
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.exit = hi3660_phy_exit,
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.owner = THIS_MODULE,
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};
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static int hi3660_phy_probe(struct platform_device *pdev)
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{
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struct phy_provider *phy_provider;
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struct device *dev = &pdev->dev;
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struct phy *phy;
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struct hi3660_priv *priv;
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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priv->dev = dev;
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priv->peri_crg = syscon_regmap_lookup_by_phandle(dev->of_node,
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"hisilicon,pericrg-syscon");
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if (IS_ERR(priv->peri_crg)) {
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dev_err(dev, "no hisilicon,pericrg-syscon\n");
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return PTR_ERR(priv->peri_crg);
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}
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priv->pctrl = syscon_regmap_lookup_by_phandle(dev->of_node,
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"hisilicon,pctrl-syscon");
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if (IS_ERR(priv->pctrl)) {
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dev_err(dev, "no hisilicon,pctrl-syscon\n");
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return PTR_ERR(priv->pctrl);
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}
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/* node of hi3660 phy is a sub-node of usb3_otg_bc */
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priv->otg_bc = syscon_node_to_regmap(dev->parent->of_node);
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if (IS_ERR(priv->otg_bc)) {
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dev_err(dev, "no hisilicon,usb3-otg-bc-syscon\n");
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return PTR_ERR(priv->otg_bc);
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}
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if (of_property_read_u32(dev->of_node, "hisilicon,eye-diagram-param",
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&(priv->eye_diagram_param)))
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priv->eye_diagram_param = HI3660_USB_DEFAULT_PHY_PARAM;
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phy = devm_phy_create(dev, NULL, &hi3660_phy_ops);
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if (IS_ERR(phy))
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return PTR_ERR(phy);
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phy_set_drvdata(phy, priv);
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phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
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return PTR_ERR_OR_ZERO(phy_provider);
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}
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static const struct of_device_id hi3660_phy_of_match[] = {
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{.compatible = "hisilicon,hi3660-usb-phy",},
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{ }
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};
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MODULE_DEVICE_TABLE(of, hi3660_phy_of_match);
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static struct platform_driver hi3660_phy_driver = {
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.probe = hi3660_phy_probe,
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.driver = {
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.name = "hi3660-usb-phy",
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.of_match_table = hi3660_phy_of_match,
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}
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};
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module_platform_driver(hi3660_phy_driver);
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MODULE_AUTHOR("Yu Chen <chenyu56@huawei.com>");
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MODULE_LICENSE("GPL v2");
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MODULE_DESCRIPTION("Hilisicon Hi3660 USB3 PHY Driver");
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