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linux/arch/sparc/kernel/pci_fire.c

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License cleanup: add SPDX GPL-2.0 license identifier to files with no license Many source files in the tree are missing licensing information, which makes it harder for compliance tools to determine the correct license. By default all files without license information are under the default license of the kernel, which is GPL version 2. Update the files which contain no license information with the 'GPL-2.0' SPDX license identifier. The SPDX identifier is a legally binding shorthand, which can be used instead of the full boiler plate text. This patch is based on work done by Thomas Gleixner and Kate Stewart and Philippe Ombredanne. How this work was done: Patches were generated and checked against linux-4.14-rc6 for a subset of the use cases: - file had no licensing information it it. - file was a */uapi/* one with no licensing information in it, - file was a */uapi/* one with existing licensing information, Further patches will be generated in subsequent months to fix up cases where non-standard license headers were used, and references to license had to be inferred by heuristics based on keywords. The analysis to determine which SPDX License Identifier to be applied to a file was done in a spreadsheet of side by side results from of the output of two independent scanners (ScanCode & Windriver) producing SPDX tag:value files created by Philippe Ombredanne. Philippe prepared the base worksheet, and did an initial spot review of a few 1000 files. The 4.13 kernel was the starting point of the analysis with 60,537 files assessed. Kate Stewart did a file by file comparison of the scanner results in the spreadsheet to determine which SPDX license identifier(s) to be applied to the file. She confirmed any determination that was not immediately clear with lawyers working with the Linux Foundation. Criteria used to select files for SPDX license identifier tagging was: - Files considered eligible had to be source code files. - Make and config files were included as candidates if they contained >5 lines of source - File already had some variant of a license header in it (even if <5 lines). All documentation files were explicitly excluded. The following heuristics were used to determine which SPDX license identifiers to apply. - when both scanners couldn't find any license traces, file was considered to have no license information in it, and the top level COPYING file license applied. For non */uapi/* files that summary was: SPDX license identifier # files ---------------------------------------------------|------- GPL-2.0 11139 and resulted in the first patch in this series. If that file was a */uapi/* path one, it was "GPL-2.0 WITH Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was: SPDX license identifier # files ---------------------------------------------------|------- GPL-2.0 WITH Linux-syscall-note 930 and resulted in the second patch in this series. - if a file had some form of licensing information in it, and was one of the */uapi/* ones, it was denoted with the Linux-syscall-note if any GPL family license was found in the file or had no licensing in it (per prior point). Results summary: SPDX license identifier # files ---------------------------------------------------|------ GPL-2.0 WITH Linux-syscall-note 270 GPL-2.0+ WITH Linux-syscall-note 169 ((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21 ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17 LGPL-2.1+ WITH Linux-syscall-note 15 GPL-1.0+ WITH Linux-syscall-note 14 ((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5 LGPL-2.0+ WITH Linux-syscall-note 4 LGPL-2.1 WITH Linux-syscall-note 3 ((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3 ((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1 and that resulted in the third patch in this series. - when the two scanners agreed on the detected license(s), that became the concluded license(s). - when there was disagreement between the two scanners (one detected a license but the other didn't, or they both detected different licenses) a manual inspection of the file occurred. - In most cases a manual inspection of the information in the file resulted in a clear resolution of the license that should apply (and which scanner probably needed to revisit its heuristics). - When it was not immediately clear, the license identifier was confirmed with lawyers working with the Linux Foundation. - If there was any question as to the appropriate license identifier, the file was flagged for further research and to be revisited later in time. In total, over 70 hours of logged manual review was done on the spreadsheet to determine the SPDX license identifiers to apply to the source files by Kate, Philippe, Thomas and, in some cases, confirmation by lawyers working with the Linux Foundation. Kate also obtained a third independent scan of the 4.13 code base from FOSSology, and compared selected files where the other two scanners disagreed against that SPDX file, to see if there was new insights. The Windriver scanner is based on an older version of FOSSology in part, so they are related. Thomas did random spot checks in about 500 files from the spreadsheets for the uapi headers and agreed with SPDX license identifier in the files he inspected. For the non-uapi files Thomas did random spot checks in about 15000 files. In initial set of patches against 4.14-rc6, 3 files were found to have copy/paste license identifier errors, and have been fixed to reflect the correct identifier. Additionally Philippe spent 10 hours this week doing a detailed manual inspection and review of the 12,461 patched files from the initial patch version early this week with: - a full scancode scan run, collecting the matched texts, detected license ids and scores - reviewing anything where there was a license detected (about 500+ files) to ensure that the applied SPDX license was correct - reviewing anything where there was no detection but the patch license was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied SPDX license was correct This produced a worksheet with 20 files needing minor correction. This worksheet was then exported into 3 different .csv files for the different types of files to be modified. These .csv files were then reviewed by Greg. Thomas wrote a script to parse the csv files and add the proper SPDX tag to the file, in the format that the file expected. This script was further refined by Greg based on the output to detect more types of files automatically and to distinguish between header and source .c files (which need different comment types.) Finally Greg ran the script using the .csv files to generate the patches. Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-11-01 14:07:57 +00:00
// SPDX-License-Identifier: GPL-2.0
[SPARC64]: SUN4U PCI-E controller support. Some minor refactoring in the generic code was necessary for this: 1) This controller requires 8-byte access to the interrupt map and clear register. They are 64-bits on all the other SBUS and PCI controllers anyways, so this was easy to cure. 2) The IMAP register has a different layout and some bits that we need to preserve, so use a read/modify/write when making changes to the IMAP register in generic code. 3) Flushing the entire IOMMU TLB is best done with a single write to a register on this PCI controller, add a iommu->iommu_flushinv for this. Still lacks MSI support, that will come later. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-05-03 00:31:36 +00:00
/* pci_fire.c: Sun4u platform PCI-E controller support.
*
* Copyright (C) 2007 David S. Miller (davem@davemloft.net)
*/
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/slab.h>
#include <linux/init.h>
[SPARC64]: Enable MSI on sun4u Fire PCI-E controllers. The support code is identical to the hypervisor sun4v stuff, just replacing the hypervisor calls with register reads and writes in the Fire controller. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-08-31 05:33:25 +00:00
#include <linux/msi.h>
sparc: add export.h to arch/sparc files as required These files are only exporting symbols, so they don't need the full module.h header file. Previously they were getting access to EXPORT_SYMBOL implicitly via overuse of module.h from within other .h files, but that is being cleaned up. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
2011-07-18 19:57:46 +00:00
#include <linux/export.h>
[SPARC64]: Enable MSI on sun4u Fire PCI-E controllers. The support code is identical to the hypervisor sun4v stuff, just replacing the hypervisor calls with register reads and writes in the Fire controller. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-08-31 05:33:25 +00:00
#include <linux/irq.h>
sparc64: Convert FIRE PCI controller driver into a real driver. And now all the by-hand PCI controller probing junk in pci.c can die too. Signed-off-by: David S. Miller <davem@davemloft.net>
2008-08-30 10:12:38 +00:00
#include <linux/of_device.h>
[SPARC64]: SUN4U PCI-E controller support. Some minor refactoring in the generic code was necessary for this: 1) This controller requires 8-byte access to the interrupt map and clear register. They are 64-bits on all the other SBUS and PCI controllers anyways, so this was easy to cure. 2) The IMAP register has a different layout and some bits that we need to preserve, so use a read/modify/write when making changes to the IMAP register in generic code. 3) Flushing the entire IOMMU TLB is best done with a single write to a register on this PCI controller, add a iommu->iommu_flushinv for this. Still lacks MSI support, that will come later. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-05-03 00:31:36 +00:00
#include <asm/prom.h>
[SPARC64]: Enable MSI on sun4u Fire PCI-E controllers. The support code is identical to the hypervisor sun4v stuff, just replacing the hypervisor calls with register reads and writes in the Fire controller. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-08-31 05:33:25 +00:00
#include <asm/irq.h>
sparc64: Kill hand-crafted I/O accessors in PCI controller drivers. Use existing upa_{read,write}q() interfaces instead. Signed-off-by: David S. Miller <davem@davemloft.net>
2008-09-10 11:13:10 +00:00
#include <asm/upa.h>
[SPARC64]: SUN4U PCI-E controller support. Some minor refactoring in the generic code was necessary for this: 1) This controller requires 8-byte access to the interrupt map and clear register. They are 64-bits on all the other SBUS and PCI controllers anyways, so this was easy to cure. 2) The IMAP register has a different layout and some bits that we need to preserve, so use a read/modify/write when making changes to the IMAP register in generic code. 3) Flushing the entire IOMMU TLB is best done with a single write to a register on this PCI controller, add a iommu->iommu_flushinv for this. Still lacks MSI support, that will come later. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-05-03 00:31:36 +00:00
#include "pci_impl.h"
sparc64: Convert FIRE PCI controller driver into a real driver. And now all the by-hand PCI controller probing junk in pci.c can die too. Signed-off-by: David S. Miller <davem@davemloft.net>
2008-08-30 10:12:38 +00:00
#define DRIVER_NAME "fire"
#define PFX DRIVER_NAME ": "
[SPARC64]: SUN4U PCI-E controller support. Some minor refactoring in the generic code was necessary for this: 1) This controller requires 8-byte access to the interrupt map and clear register. They are 64-bits on all the other SBUS and PCI controllers anyways, so this was easy to cure. 2) The IMAP register has a different layout and some bits that we need to preserve, so use a read/modify/write when making changes to the IMAP register in generic code. 3) Flushing the entire IOMMU TLB is best done with a single write to a register on this PCI controller, add a iommu->iommu_flushinv for this. Still lacks MSI support, that will come later. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-05-03 00:31:36 +00:00
#define FIRE_IOMMU_CONTROL 0x40000UL
#define FIRE_IOMMU_TSBBASE 0x40008UL
#define FIRE_IOMMU_FLUSH 0x40100UL
[SPARC64]: Correct FIRE_IOMMU_FLUSHINV register offset. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-05-12 04:02:09 +00:00
#define FIRE_IOMMU_FLUSHINV 0x40108UL
[SPARC64]: SUN4U PCI-E controller support. Some minor refactoring in the generic code was necessary for this: 1) This controller requires 8-byte access to the interrupt map and clear register. They are 64-bits on all the other SBUS and PCI controllers anyways, so this was easy to cure. 2) The IMAP register has a different layout and some bits that we need to preserve, so use a read/modify/write when making changes to the IMAP register in generic code. 3) Flushing the entire IOMMU TLB is best done with a single write to a register on this PCI controller, add a iommu->iommu_flushinv for this. Still lacks MSI support, that will come later. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-05-03 00:31:36 +00:00
[SPARC64]: Fix conflicts in SBUS/PCI/EBUS/ISA DMA handling. Fully unify all of the DMA ops so that subordinate bus types to the DMA operation providers (such as ebus, isa, of_device) can work transparently. Basically, we just make sure that for every system device we create, the dev->archdata 'iommu' and 'stc' fields are filled in. Then we have two platform variants of the DMA ops, one for SUN4U which actually programs the real hardware, and one for SUN4V which makes hypervisor calls. This also fixes the crashes in parport_pc on sparc64, reported by Meelis Roos. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-07-28 05:39:14 +00:00
static int pci_fire_pbm_iommu_init(struct pci_pbm_info *pbm)
[SPARC64]: SUN4U PCI-E controller support. Some minor refactoring in the generic code was necessary for this: 1) This controller requires 8-byte access to the interrupt map and clear register. They are 64-bits on all the other SBUS and PCI controllers anyways, so this was easy to cure. 2) The IMAP register has a different layout and some bits that we need to preserve, so use a read/modify/write when making changes to the IMAP register in generic code. 3) Flushing the entire IOMMU TLB is best done with a single write to a register on this PCI controller, add a iommu->iommu_flushinv for this. Still lacks MSI support, that will come later. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-05-03 00:31:36 +00:00
{
struct iommu *iommu = pbm->iommu;
u32 vdma[2], dma_mask;
u64 control;
[SPARC64]: Fix conflicts in SBUS/PCI/EBUS/ISA DMA handling. Fully unify all of the DMA ops so that subordinate bus types to the DMA operation providers (such as ebus, isa, of_device) can work transparently. Basically, we just make sure that for every system device we create, the dev->archdata 'iommu' and 'stc' fields are filled in. Then we have two platform variants of the DMA ops, one for SUN4U which actually programs the real hardware, and one for SUN4V which makes hypervisor calls. This also fixes the crashes in parport_pc on sparc64, reported by Meelis Roos. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-07-28 05:39:14 +00:00
int tsbsize, err;
[SPARC64]: SUN4U PCI-E controller support. Some minor refactoring in the generic code was necessary for this: 1) This controller requires 8-byte access to the interrupt map and clear register. They are 64-bits on all the other SBUS and PCI controllers anyways, so this was easy to cure. 2) The IMAP register has a different layout and some bits that we need to preserve, so use a read/modify/write when making changes to the IMAP register in generic code. 3) Flushing the entire IOMMU TLB is best done with a single write to a register on this PCI controller, add a iommu->iommu_flushinv for this. Still lacks MSI support, that will come later. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-05-03 00:31:36 +00:00
/* No virtual-dma property on these guys, use largest size. */
vdma[0] = 0xc0000000; /* base */
vdma[1] = 0x40000000; /* size */
dma_mask = 0xffffffff;
tsbsize = 128;
/* Register addresses. */
iommu->iommu_control = pbm->pbm_regs + FIRE_IOMMU_CONTROL;
iommu->iommu_tsbbase = pbm->pbm_regs + FIRE_IOMMU_TSBBASE;
iommu->iommu_flush = pbm->pbm_regs + FIRE_IOMMU_FLUSH;
iommu->iommu_flushinv = pbm->pbm_regs + FIRE_IOMMU_FLUSHINV;
/* We use the main control/status register of FIRE as the write
* completion register.
*/
iommu->write_complete_reg = pbm->controller_regs + 0x410000UL;
/*
* Invalidate TLB Entries.
*/
sparc64: Kill hand-crafted I/O accessors in PCI controller drivers. Use existing upa_{read,write}q() interfaces instead. Signed-off-by: David S. Miller <davem@davemloft.net>
2008-09-10 11:13:10 +00:00
upa_writeq(~(u64)0, iommu->iommu_flushinv);
[SPARC64]: SUN4U PCI-E controller support. Some minor refactoring in the generic code was necessary for this: 1) This controller requires 8-byte access to the interrupt map and clear register. They are 64-bits on all the other SBUS and PCI controllers anyways, so this was easy to cure. 2) The IMAP register has a different layout and some bits that we need to preserve, so use a read/modify/write when making changes to the IMAP register in generic code. 3) Flushing the entire IOMMU TLB is best done with a single write to a register on this PCI controller, add a iommu->iommu_flushinv for this. Still lacks MSI support, that will come later. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-05-03 00:31:36 +00:00
[SPARC64]: NUMA device infrastructure. Record and propagate NUMA information for devices. Signed-off-by: David S. Miller <davem@davemloft.net>
2008-03-19 11:52:48 +00:00
err = iommu_table_init(iommu, tsbsize * 8 * 1024, vdma[0], dma_mask,
pbm->numa_node);
[SPARC64]: Fix conflicts in SBUS/PCI/EBUS/ISA DMA handling. Fully unify all of the DMA ops so that subordinate bus types to the DMA operation providers (such as ebus, isa, of_device) can work transparently. Basically, we just make sure that for every system device we create, the dev->archdata 'iommu' and 'stc' fields are filled in. Then we have two platform variants of the DMA ops, one for SUN4U which actually programs the real hardware, and one for SUN4V which makes hypervisor calls. This also fixes the crashes in parport_pc on sparc64, reported by Meelis Roos. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-07-28 05:39:14 +00:00
if (err)
return err;
[SPARC64]: SUN4U PCI-E controller support. Some minor refactoring in the generic code was necessary for this: 1) This controller requires 8-byte access to the interrupt map and clear register. They are 64-bits on all the other SBUS and PCI controllers anyways, so this was easy to cure. 2) The IMAP register has a different layout and some bits that we need to preserve, so use a read/modify/write when making changes to the IMAP register in generic code. 3) Flushing the entire IOMMU TLB is best done with a single write to a register on this PCI controller, add a iommu->iommu_flushinv for this. Still lacks MSI support, that will come later. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-05-03 00:31:36 +00:00
sparc64: Kill hand-crafted I/O accessors in PCI controller drivers. Use existing upa_{read,write}q() interfaces instead. Signed-off-by: David S. Miller <davem@davemloft.net>
2008-09-10 11:13:10 +00:00
upa_writeq(__pa(iommu->page_table) | 0x7UL, iommu->iommu_tsbbase);
[SPARC64]: SUN4U PCI-E controller support. Some minor refactoring in the generic code was necessary for this: 1) This controller requires 8-byte access to the interrupt map and clear register. They are 64-bits on all the other SBUS and PCI controllers anyways, so this was easy to cure. 2) The IMAP register has a different layout and some bits that we need to preserve, so use a read/modify/write when making changes to the IMAP register in generic code. 3) Flushing the entire IOMMU TLB is best done with a single write to a register on this PCI controller, add a iommu->iommu_flushinv for this. Still lacks MSI support, that will come later. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-05-03 00:31:36 +00:00
sparc64: Kill hand-crafted I/O accessors in PCI controller drivers. Use existing upa_{read,write}q() interfaces instead. Signed-off-by: David S. Miller <davem@davemloft.net>
2008-09-10 11:13:10 +00:00
control = upa_readq(iommu->iommu_control);
[SPARC64]: SUN4U PCI-E controller support. Some minor refactoring in the generic code was necessary for this: 1) This controller requires 8-byte access to the interrupt map and clear register. They are 64-bits on all the other SBUS and PCI controllers anyways, so this was easy to cure. 2) The IMAP register has a different layout and some bits that we need to preserve, so use a read/modify/write when making changes to the IMAP register in generic code. 3) Flushing the entire IOMMU TLB is best done with a single write to a register on this PCI controller, add a iommu->iommu_flushinv for this. Still lacks MSI support, that will come later. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-05-03 00:31:36 +00:00
control |= (0x00000400 /* TSB cache snoop enable */ |
0x00000300 /* Cache mode */ |
0x00000002 /* Bypass enable */ |
0x00000001 /* Translation enable */);
sparc64: Kill hand-crafted I/O accessors in PCI controller drivers. Use existing upa_{read,write}q() interfaces instead. Signed-off-by: David S. Miller <davem@davemloft.net>
2008-09-10 11:13:10 +00:00
upa_writeq(control, iommu->iommu_control);
[SPARC64]: Fix conflicts in SBUS/PCI/EBUS/ISA DMA handling. Fully unify all of the DMA ops so that subordinate bus types to the DMA operation providers (such as ebus, isa, of_device) can work transparently. Basically, we just make sure that for every system device we create, the dev->archdata 'iommu' and 'stc' fields are filled in. Then we have two platform variants of the DMA ops, one for SUN4U which actually programs the real hardware, and one for SUN4V which makes hypervisor calls. This also fixes the crashes in parport_pc on sparc64, reported by Meelis Roos. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-07-28 05:39:14 +00:00
return 0;
[SPARC64]: SUN4U PCI-E controller support. Some minor refactoring in the generic code was necessary for this: 1) This controller requires 8-byte access to the interrupt map and clear register. They are 64-bits on all the other SBUS and PCI controllers anyways, so this was easy to cure. 2) The IMAP register has a different layout and some bits that we need to preserve, so use a read/modify/write when making changes to the IMAP register in generic code. 3) Flushing the entire IOMMU TLB is best done with a single write to a register on this PCI controller, add a iommu->iommu_flushinv for this. Still lacks MSI support, that will come later. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-05-03 00:31:36 +00:00
}
[SPARC64]: Enable MSI on sun4u Fire PCI-E controllers. The support code is identical to the hypervisor sun4v stuff, just replacing the hypervisor calls with register reads and writes in the Fire controller. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-08-31 05:33:25 +00:00
#ifdef CONFIG_PCI_MSI
struct pci_msiq_entry {
u64 word0;
#define MSIQ_WORD0_RESV 0x8000000000000000UL
#define MSIQ_WORD0_FMT_TYPE 0x7f00000000000000UL
#define MSIQ_WORD0_FMT_TYPE_SHIFT 56
#define MSIQ_WORD0_LEN 0x00ffc00000000000UL
#define MSIQ_WORD0_LEN_SHIFT 46
#define MSIQ_WORD0_ADDR0 0x00003fff00000000UL
#define MSIQ_WORD0_ADDR0_SHIFT 32
#define MSIQ_WORD0_RID 0x00000000ffff0000UL
#define MSIQ_WORD0_RID_SHIFT 16
#define MSIQ_WORD0_DATA0 0x000000000000ffffUL
#define MSIQ_WORD0_DATA0_SHIFT 0
#define MSIQ_TYPE_MSG 0x6
#define MSIQ_TYPE_MSI32 0xb
#define MSIQ_TYPE_MSI64 0xf
u64 word1;
#define MSIQ_WORD1_ADDR1 0xffffffffffff0000UL
#define MSIQ_WORD1_ADDR1_SHIFT 16
#define MSIQ_WORD1_DATA1 0x000000000000ffffUL
#define MSIQ_WORD1_DATA1_SHIFT 0
u64 resv[6];
};
/* All MSI registers are offset from pbm->pbm_regs */
#define EVENT_QUEUE_BASE_ADDR_REG 0x010000UL
#define EVENT_QUEUE_BASE_ADDR_ALL_ONES 0xfffc000000000000UL
#define EVENT_QUEUE_CONTROL_SET(EQ) (0x011000UL + (EQ) * 0x8UL)
#define EVENT_QUEUE_CONTROL_SET_OFLOW 0x0200000000000000UL
#define EVENT_QUEUE_CONTROL_SET_EN 0x0000100000000000UL
#define EVENT_QUEUE_CONTROL_CLEAR(EQ) (0x011200UL + (EQ) * 0x8UL)
#define EVENT_QUEUE_CONTROL_CLEAR_OF 0x0200000000000000UL
#define EVENT_QUEUE_CONTROL_CLEAR_E2I 0x0000800000000000UL
#define EVENT_QUEUE_CONTROL_CLEAR_DIS 0x0000100000000000UL
#define EVENT_QUEUE_STATE(EQ) (0x011400UL + (EQ) * 0x8UL)
#define EVENT_QUEUE_STATE_MASK 0x0000000000000007UL
#define EVENT_QUEUE_STATE_IDLE 0x0000000000000001UL
#define EVENT_QUEUE_STATE_ACTIVE 0x0000000000000002UL
#define EVENT_QUEUE_STATE_ERROR 0x0000000000000004UL
#define EVENT_QUEUE_TAIL(EQ) (0x011600UL + (EQ) * 0x8UL)
#define EVENT_QUEUE_TAIL_OFLOW 0x0200000000000000UL
#define EVENT_QUEUE_TAIL_VAL 0x000000000000007fUL
#define EVENT_QUEUE_HEAD(EQ) (0x011800UL + (EQ) * 0x8UL)
#define EVENT_QUEUE_HEAD_VAL 0x000000000000007fUL
#define MSI_MAP(MSI) (0x020000UL + (MSI) * 0x8UL)
#define MSI_MAP_VALID 0x8000000000000000UL
#define MSI_MAP_EQWR_N 0x4000000000000000UL
#define MSI_MAP_EQNUM 0x000000000000003fUL
#define MSI_CLEAR(MSI) (0x028000UL + (MSI) * 0x8UL)
#define MSI_CLEAR_EQWR_N 0x4000000000000000UL
#define IMONDO_DATA0 0x02C000UL
#define IMONDO_DATA0_DATA 0xffffffffffffffc0UL
#define IMONDO_DATA1 0x02C008UL
#define IMONDO_DATA1_DATA 0xffffffffffffffffUL
#define MSI_32BIT_ADDR 0x034000UL
#define MSI_32BIT_ADDR_VAL 0x00000000ffff0000UL
#define MSI_64BIT_ADDR 0x034008UL
#define MSI_64BIT_ADDR_VAL 0xffffffffffff0000UL
[SPARC64]: Consolidate MSI support code. This also makes us use the MSI queues correctly. Each MSI queue is serviced by a normal sun4u/sun4v INO interrupt handler. This handler runs the MSI queue and dispatches the virtual interrupts indicated by arriving MSIs in that MSI queue. All of the common logic is placed in pci_msi.c, with callbacks to handle the PCI controller specific aspects of the operations. This common infrastructure will make it much easier to add MSG support. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-10-11 10:16:13 +00:00
static int pci_fire_get_head(struct pci_pbm_info *pbm, unsigned long msiqid,
unsigned long *head)
{
sparc64: Kill hand-crafted I/O accessors in PCI controller drivers. Use existing upa_{read,write}q() interfaces instead. Signed-off-by: David S. Miller <davem@davemloft.net>
2008-09-10 11:13:10 +00:00
*head = upa_readq(pbm->pbm_regs + EVENT_QUEUE_HEAD(msiqid));
[SPARC64]: Consolidate MSI support code. This also makes us use the MSI queues correctly. Each MSI queue is serviced by a normal sun4u/sun4v INO interrupt handler. This handler runs the MSI queue and dispatches the virtual interrupts indicated by arriving MSIs in that MSI queue. All of the common logic is placed in pci_msi.c, with callbacks to handle the PCI controller specific aspects of the operations. This common infrastructure will make it much easier to add MSG support. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-10-11 10:16:13 +00:00
return 0;
}
static int pci_fire_dequeue_msi(struct pci_pbm_info *pbm, unsigned long msiqid,
unsigned long *head, unsigned long *msi)
[SPARC64]: Enable MSI on sun4u Fire PCI-E controllers. The support code is identical to the hypervisor sun4v stuff, just replacing the hypervisor calls with register reads and writes in the Fire controller. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-08-31 05:33:25 +00:00
{
[SPARC64]: Consolidate MSI support code. This also makes us use the MSI queues correctly. Each MSI queue is serviced by a normal sun4u/sun4v INO interrupt handler. This handler runs the MSI queue and dispatches the virtual interrupts indicated by arriving MSIs in that MSI queue. All of the common logic is placed in pci_msi.c, with callbacks to handle the PCI controller specific aspects of the operations. This common infrastructure will make it much easier to add MSG support. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-10-11 10:16:13 +00:00
unsigned long type_fmt, type, msi_num;
[SPARC64]: Enable MSI on sun4u Fire PCI-E controllers. The support code is identical to the hypervisor sun4v stuff, just replacing the hypervisor calls with register reads and writes in the Fire controller. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-08-31 05:33:25 +00:00
struct pci_msiq_entry *base, *ep;
[SPARC64]: Consolidate MSI support code. This also makes us use the MSI queues correctly. Each MSI queue is serviced by a normal sun4u/sun4v INO interrupt handler. This handler runs the MSI queue and dispatches the virtual interrupts indicated by arriving MSIs in that MSI queue. All of the common logic is placed in pci_msi.c, with callbacks to handle the PCI controller specific aspects of the operations. This common infrastructure will make it much easier to add MSG support. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-10-11 10:16:13 +00:00
base = (pbm->msi_queues + ((msiqid - pbm->msiq_first) * 8192));
ep = &base[*head];
[SPARC64]: Enable MSI on sun4u Fire PCI-E controllers. The support code is identical to the hypervisor sun4v stuff, just replacing the hypervisor calls with register reads and writes in the Fire controller. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-08-31 05:33:25 +00:00
[SPARC64]: Consolidate MSI support code. This also makes us use the MSI queues correctly. Each MSI queue is serviced by a normal sun4u/sun4v INO interrupt handler. This handler runs the MSI queue and dispatches the virtual interrupts indicated by arriving MSIs in that MSI queue. All of the common logic is placed in pci_msi.c, with callbacks to handle the PCI controller specific aspects of the operations. This common infrastructure will make it much easier to add MSG support. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-10-11 10:16:13 +00:00
if ((ep->word0 & MSIQ_WORD0_FMT_TYPE) == 0)
return 0;
[SPARC64]: Enable MSI on sun4u Fire PCI-E controllers. The support code is identical to the hypervisor sun4v stuff, just replacing the hypervisor calls with register reads and writes in the Fire controller. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-08-31 05:33:25 +00:00
[SPARC64]: Consolidate MSI support code. This also makes us use the MSI queues correctly. Each MSI queue is serviced by a normal sun4u/sun4v INO interrupt handler. This handler runs the MSI queue and dispatches the virtual interrupts indicated by arriving MSIs in that MSI queue. All of the common logic is placed in pci_msi.c, with callbacks to handle the PCI controller specific aspects of the operations. This common infrastructure will make it much easier to add MSG support. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-10-11 10:16:13 +00:00
type_fmt = ((ep->word0 & MSIQ_WORD0_FMT_TYPE) >>
MSIQ_WORD0_FMT_TYPE_SHIFT);
type = (type_fmt >> 3);
if (unlikely(type != MSIQ_TYPE_MSI32 &&
type != MSIQ_TYPE_MSI64))
return -EINVAL;
[SPARC64]: Enable MSI on sun4u Fire PCI-E controllers. The support code is identical to the hypervisor sun4v stuff, just replacing the hypervisor calls with register reads and writes in the Fire controller. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-08-31 05:33:25 +00:00
[SPARC64]: Consolidate MSI support code. This also makes us use the MSI queues correctly. Each MSI queue is serviced by a normal sun4u/sun4v INO interrupt handler. This handler runs the MSI queue and dispatches the virtual interrupts indicated by arriving MSIs in that MSI queue. All of the common logic is placed in pci_msi.c, with callbacks to handle the PCI controller specific aspects of the operations. This common infrastructure will make it much easier to add MSG support. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-10-11 10:16:13 +00:00
*msi = msi_num = ((ep->word0 & MSIQ_WORD0_DATA0) >>
MSIQ_WORD0_DATA0_SHIFT);
[SPARC64]: Enable MSI on sun4u Fire PCI-E controllers. The support code is identical to the hypervisor sun4v stuff, just replacing the hypervisor calls with register reads and writes in the Fire controller. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-08-31 05:33:25 +00:00
sparc64: Kill hand-crafted I/O accessors in PCI controller drivers. Use existing upa_{read,write}q() interfaces instead. Signed-off-by: David S. Miller <davem@davemloft.net>
2008-09-10 11:13:10 +00:00
upa_writeq(MSI_CLEAR_EQWR_N, pbm->pbm_regs + MSI_CLEAR(msi_num));
[SPARC64]: Consolidate MSI support code. This also makes us use the MSI queues correctly. Each MSI queue is serviced by a normal sun4u/sun4v INO interrupt handler. This handler runs the MSI queue and dispatches the virtual interrupts indicated by arriving MSIs in that MSI queue. All of the common logic is placed in pci_msi.c, with callbacks to handle the PCI controller specific aspects of the operations. This common infrastructure will make it much easier to add MSG support. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-10-11 10:16:13 +00:00
/* Clear the entry. */
ep->word0 &= ~MSIQ_WORD0_FMT_TYPE;
/* Go to next entry in ring. */
(*head)++;
if (*head >= pbm->msiq_ent_count)
*head = 0;
return 1;
[SPARC64]: Enable MSI on sun4u Fire PCI-E controllers. The support code is identical to the hypervisor sun4v stuff, just replacing the hypervisor calls with register reads and writes in the Fire controller. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-08-31 05:33:25 +00:00
}
[SPARC64]: Consolidate MSI support code. This also makes us use the MSI queues correctly. Each MSI queue is serviced by a normal sun4u/sun4v INO interrupt handler. This handler runs the MSI queue and dispatches the virtual interrupts indicated by arriving MSIs in that MSI queue. All of the common logic is placed in pci_msi.c, with callbacks to handle the PCI controller specific aspects of the operations. This common infrastructure will make it much easier to add MSG support. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-10-11 10:16:13 +00:00
static int pci_fire_set_head(struct pci_pbm_info *pbm, unsigned long msiqid,
unsigned long head)
[SPARC64]: Enable MSI on sun4u Fire PCI-E controllers. The support code is identical to the hypervisor sun4v stuff, just replacing the hypervisor calls with register reads and writes in the Fire controller. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-08-31 05:33:25 +00:00
{
sparc64: Kill hand-crafted I/O accessors in PCI controller drivers. Use existing upa_{read,write}q() interfaces instead. Signed-off-by: David S. Miller <davem@davemloft.net>
2008-09-10 11:13:10 +00:00
upa_writeq(head, pbm->pbm_regs + EVENT_QUEUE_HEAD(msiqid));
[SPARC64]: Consolidate MSI support code. This also makes us use the MSI queues correctly. Each MSI queue is serviced by a normal sun4u/sun4v INO interrupt handler. This handler runs the MSI queue and dispatches the virtual interrupts indicated by arriving MSIs in that MSI queue. All of the common logic is placed in pci_msi.c, with callbacks to handle the PCI controller specific aspects of the operations. This common infrastructure will make it much easier to add MSG support. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-10-11 10:16:13 +00:00
return 0;
}
[SPARC64]: Enable MSI on sun4u Fire PCI-E controllers. The support code is identical to the hypervisor sun4v stuff, just replacing the hypervisor calls with register reads and writes in the Fire controller. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-08-31 05:33:25 +00:00
[SPARC64]: Consolidate MSI support code. This also makes us use the MSI queues correctly. Each MSI queue is serviced by a normal sun4u/sun4v INO interrupt handler. This handler runs the MSI queue and dispatches the virtual interrupts indicated by arriving MSIs in that MSI queue. All of the common logic is placed in pci_msi.c, with callbacks to handle the PCI controller specific aspects of the operations. This common infrastructure will make it much easier to add MSG support. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-10-11 10:16:13 +00:00
static int pci_fire_msi_setup(struct pci_pbm_info *pbm, unsigned long msiqid,
unsigned long msi, int is_msi64)
{
u64 val;
[SPARC64]: Enable MSI on sun4u Fire PCI-E controllers. The support code is identical to the hypervisor sun4v stuff, just replacing the hypervisor calls with register reads and writes in the Fire controller. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-08-31 05:33:25 +00:00
sparc64: Kill hand-crafted I/O accessors in PCI controller drivers. Use existing upa_{read,write}q() interfaces instead. Signed-off-by: David S. Miller <davem@davemloft.net>
2008-09-10 11:13:10 +00:00
val = upa_readq(pbm->pbm_regs + MSI_MAP(msi));
[SPARC64]: Consolidate MSI support code. This also makes us use the MSI queues correctly. Each MSI queue is serviced by a normal sun4u/sun4v INO interrupt handler. This handler runs the MSI queue and dispatches the virtual interrupts indicated by arriving MSIs in that MSI queue. All of the common logic is placed in pci_msi.c, with callbacks to handle the PCI controller specific aspects of the operations. This common infrastructure will make it much easier to add MSG support. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-10-11 10:16:13 +00:00
val &= ~(MSI_MAP_EQNUM);
val |= msiqid;
sparc64: Kill hand-crafted I/O accessors in PCI controller drivers. Use existing upa_{read,write}q() interfaces instead. Signed-off-by: David S. Miller <davem@davemloft.net>
2008-09-10 11:13:10 +00:00
upa_writeq(val, pbm->pbm_regs + MSI_MAP(msi));
[SPARC64]: Consolidate MSI support code. This also makes us use the MSI queues correctly. Each MSI queue is serviced by a normal sun4u/sun4v INO interrupt handler. This handler runs the MSI queue and dispatches the virtual interrupts indicated by arriving MSIs in that MSI queue. All of the common logic is placed in pci_msi.c, with callbacks to handle the PCI controller specific aspects of the operations. This common infrastructure will make it much easier to add MSG support. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-10-11 10:16:13 +00:00
sparc64: Kill hand-crafted I/O accessors in PCI controller drivers. Use existing upa_{read,write}q() interfaces instead. Signed-off-by: David S. Miller <davem@davemloft.net>
2008-09-10 11:13:10 +00:00
upa_writeq(MSI_CLEAR_EQWR_N, pbm->pbm_regs + MSI_CLEAR(msi));
[SPARC64]: Consolidate MSI support code. This also makes us use the MSI queues correctly. Each MSI queue is serviced by a normal sun4u/sun4v INO interrupt handler. This handler runs the MSI queue and dispatches the virtual interrupts indicated by arriving MSIs in that MSI queue. All of the common logic is placed in pci_msi.c, with callbacks to handle the PCI controller specific aspects of the operations. This common infrastructure will make it much easier to add MSG support. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-10-11 10:16:13 +00:00
sparc64: Kill hand-crafted I/O accessors in PCI controller drivers. Use existing upa_{read,write}q() interfaces instead. Signed-off-by: David S. Miller <davem@davemloft.net>
2008-09-10 11:13:10 +00:00
val = upa_readq(pbm->pbm_regs + MSI_MAP(msi));
[SPARC64]: Consolidate MSI support code. This also makes us use the MSI queues correctly. Each MSI queue is serviced by a normal sun4u/sun4v INO interrupt handler. This handler runs the MSI queue and dispatches the virtual interrupts indicated by arriving MSIs in that MSI queue. All of the common logic is placed in pci_msi.c, with callbacks to handle the PCI controller specific aspects of the operations. This common infrastructure will make it much easier to add MSG support. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-10-11 10:16:13 +00:00
val |= MSI_MAP_VALID;
sparc64: Kill hand-crafted I/O accessors in PCI controller drivers. Use existing upa_{read,write}q() interfaces instead. Signed-off-by: David S. Miller <davem@davemloft.net>
2008-09-10 11:13:10 +00:00
upa_writeq(val, pbm->pbm_regs + MSI_MAP(msi));
[SPARC64]: Enable MSI on sun4u Fire PCI-E controllers. The support code is identical to the hypervisor sun4v stuff, just replacing the hypervisor calls with register reads and writes in the Fire controller. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-08-31 05:33:25 +00:00
return 0;
}
[SPARC64]: Consolidate MSI support code. This also makes us use the MSI queues correctly. Each MSI queue is serviced by a normal sun4u/sun4v INO interrupt handler. This handler runs the MSI queue and dispatches the virtual interrupts indicated by arriving MSIs in that MSI queue. All of the common logic is placed in pci_msi.c, with callbacks to handle the PCI controller specific aspects of the operations. This common infrastructure will make it much easier to add MSG support. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-10-11 10:16:13 +00:00
static int pci_fire_msi_teardown(struct pci_pbm_info *pbm, unsigned long msi)
[SPARC64]: Enable MSI on sun4u Fire PCI-E controllers. The support code is identical to the hypervisor sun4v stuff, just replacing the hypervisor calls with register reads and writes in the Fire controller. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-08-31 05:33:25 +00:00
{
[SPARC64]: Consolidate MSI support code. This also makes us use the MSI queues correctly. Each MSI queue is serviced by a normal sun4u/sun4v INO interrupt handler. This handler runs the MSI queue and dispatches the virtual interrupts indicated by arriving MSIs in that MSI queue. All of the common logic is placed in pci_msi.c, with callbacks to handle the PCI controller specific aspects of the operations. This common infrastructure will make it much easier to add MSG support. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-10-11 10:16:13 +00:00
u64 val;
sparc64: Kill hand-crafted I/O accessors in PCI controller drivers. Use existing upa_{read,write}q() interfaces instead. Signed-off-by: David S. Miller <davem@davemloft.net>
2008-09-10 11:13:10 +00:00
val = upa_readq(pbm->pbm_regs + MSI_MAP(msi));
[SPARC64]: Consolidate MSI support code. This also makes us use the MSI queues correctly. Each MSI queue is serviced by a normal sun4u/sun4v INO interrupt handler. This handler runs the MSI queue and dispatches the virtual interrupts indicated by arriving MSIs in that MSI queue. All of the common logic is placed in pci_msi.c, with callbacks to handle the PCI controller specific aspects of the operations. This common infrastructure will make it much easier to add MSG support. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-10-11 10:16:13 +00:00
val &= ~MSI_MAP_VALID;
sparc64: Kill hand-crafted I/O accessors in PCI controller drivers. Use existing upa_{read,write}q() interfaces instead. Signed-off-by: David S. Miller <davem@davemloft.net>
2008-09-10 11:13:10 +00:00
upa_writeq(val, pbm->pbm_regs + MSI_MAP(msi));
[SPARC64]: Consolidate MSI support code. This also makes us use the MSI queues correctly. Each MSI queue is serviced by a normal sun4u/sun4v INO interrupt handler. This handler runs the MSI queue and dispatches the virtual interrupts indicated by arriving MSIs in that MSI queue. All of the common logic is placed in pci_msi.c, with callbacks to handle the PCI controller specific aspects of the operations. This common infrastructure will make it much easier to add MSG support. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-10-11 10:16:13 +00:00
return 0;
[SPARC64]: Enable MSI on sun4u Fire PCI-E controllers. The support code is identical to the hypervisor sun4v stuff, just replacing the hypervisor calls with register reads and writes in the Fire controller. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-08-31 05:33:25 +00:00
}
[SPARC64]: Consolidate MSI support code. This also makes us use the MSI queues correctly. Each MSI queue is serviced by a normal sun4u/sun4v INO interrupt handler. This handler runs the MSI queue and dispatches the virtual interrupts indicated by arriving MSIs in that MSI queue. All of the common logic is placed in pci_msi.c, with callbacks to handle the PCI controller specific aspects of the operations. This common infrastructure will make it much easier to add MSG support. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-10-11 10:16:13 +00:00
static int pci_fire_msiq_alloc(struct pci_pbm_info *pbm)
[SPARC64]: Enable MSI on sun4u Fire PCI-E controllers. The support code is identical to the hypervisor sun4v stuff, just replacing the hypervisor calls with register reads and writes in the Fire controller. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-08-31 05:33:25 +00:00
{
unsigned long pages, order, i;
order = get_order(512 * 1024);
pages = __get_free_pages(GFP_KERNEL | __GFP_COMP, order);
if (pages == 0UL) {
printk(KERN_ERR "MSI: Cannot allocate MSI queues (o=%lu).\n",
order);
return -ENOMEM;
}
memset((char *)pages, 0, PAGE_SIZE << order);
pbm->msi_queues = (void *) pages;
sparc64: Kill hand-crafted I/O accessors in PCI controller drivers. Use existing upa_{read,write}q() interfaces instead. Signed-off-by: David S. Miller <davem@davemloft.net>
2008-09-10 11:13:10 +00:00
upa_writeq((EVENT_QUEUE_BASE_ADDR_ALL_ONES |
__pa(pbm->msi_queues)),
pbm->pbm_regs + EVENT_QUEUE_BASE_ADDR_REG);
[SPARC64]: Enable MSI on sun4u Fire PCI-E controllers. The support code is identical to the hypervisor sun4v stuff, just replacing the hypervisor calls with register reads and writes in the Fire controller. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-08-31 05:33:25 +00:00
sparc64: Kill hand-crafted I/O accessors in PCI controller drivers. Use existing upa_{read,write}q() interfaces instead. Signed-off-by: David S. Miller <davem@davemloft.net>
2008-09-10 11:13:10 +00:00
upa_writeq(pbm->portid << 6, pbm->pbm_regs + IMONDO_DATA0);
upa_writeq(0, pbm->pbm_regs + IMONDO_DATA1);
[SPARC64]: Enable MSI on sun4u Fire PCI-E controllers. The support code is identical to the hypervisor sun4v stuff, just replacing the hypervisor calls with register reads and writes in the Fire controller. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-08-31 05:33:25 +00:00
sparc64: Kill hand-crafted I/O accessors in PCI controller drivers. Use existing upa_{read,write}q() interfaces instead. Signed-off-by: David S. Miller <davem@davemloft.net>
2008-09-10 11:13:10 +00:00
upa_writeq(pbm->msi32_start, pbm->pbm_regs + MSI_32BIT_ADDR);
upa_writeq(pbm->msi64_start, pbm->pbm_regs + MSI_64BIT_ADDR);
[SPARC64]: Enable MSI on sun4u Fire PCI-E controllers. The support code is identical to the hypervisor sun4v stuff, just replacing the hypervisor calls with register reads and writes in the Fire controller. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-08-31 05:33:25 +00:00
for (i = 0; i < pbm->msiq_num; i++) {
sparc64: Kill hand-crafted I/O accessors in PCI controller drivers. Use existing upa_{read,write}q() interfaces instead. Signed-off-by: David S. Miller <davem@davemloft.net>
2008-09-10 11:13:10 +00:00
upa_writeq(0, pbm->pbm_regs + EVENT_QUEUE_HEAD(i));
upa_writeq(0, pbm->pbm_regs + EVENT_QUEUE_TAIL(i));
[SPARC64]: Enable MSI on sun4u Fire PCI-E controllers. The support code is identical to the hypervisor sun4v stuff, just replacing the hypervisor calls with register reads and writes in the Fire controller. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-08-31 05:33:25 +00:00
}
return 0;
}
[SPARC64]: Consolidate MSI support code. This also makes us use the MSI queues correctly. Each MSI queue is serviced by a normal sun4u/sun4v INO interrupt handler. This handler runs the MSI queue and dispatches the virtual interrupts indicated by arriving MSIs in that MSI queue. All of the common logic is placed in pci_msi.c, with callbacks to handle the PCI controller specific aspects of the operations. This common infrastructure will make it much easier to add MSG support. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-10-11 10:16:13 +00:00
static void pci_fire_msiq_free(struct pci_pbm_info *pbm)
[SPARC64]: Enable MSI on sun4u Fire PCI-E controllers. The support code is identical to the hypervisor sun4v stuff, just replacing the hypervisor calls with register reads and writes in the Fire controller. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-08-31 05:33:25 +00:00
{
[SPARC64]: Consolidate MSI support code. This also makes us use the MSI queues correctly. Each MSI queue is serviced by a normal sun4u/sun4v INO interrupt handler. This handler runs the MSI queue and dispatches the virtual interrupts indicated by arriving MSIs in that MSI queue. All of the common logic is placed in pci_msi.c, with callbacks to handle the PCI controller specific aspects of the operations. This common infrastructure will make it much easier to add MSG support. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-10-11 10:16:13 +00:00
unsigned long pages, order;
[SPARC64]: Enable MSI on sun4u Fire PCI-E controllers. The support code is identical to the hypervisor sun4v stuff, just replacing the hypervisor calls with register reads and writes in the Fire controller. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-08-31 05:33:25 +00:00
[SPARC64]: Consolidate MSI support code. This also makes us use the MSI queues correctly. Each MSI queue is serviced by a normal sun4u/sun4v INO interrupt handler. This handler runs the MSI queue and dispatches the virtual interrupts indicated by arriving MSIs in that MSI queue. All of the common logic is placed in pci_msi.c, with callbacks to handle the PCI controller specific aspects of the operations. This common infrastructure will make it much easier to add MSG support. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-10-11 10:16:13 +00:00
order = get_order(512 * 1024);
pages = (unsigned long) pbm->msi_queues;
[SPARC64]: Enable MSI on sun4u Fire PCI-E controllers. The support code is identical to the hypervisor sun4v stuff, just replacing the hypervisor calls with register reads and writes in the Fire controller. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-08-31 05:33:25 +00:00
[SPARC64]: Consolidate MSI support code. This also makes us use the MSI queues correctly. Each MSI queue is serviced by a normal sun4u/sun4v INO interrupt handler. This handler runs the MSI queue and dispatches the virtual interrupts indicated by arriving MSIs in that MSI queue. All of the common logic is placed in pci_msi.c, with callbacks to handle the PCI controller specific aspects of the operations. This common infrastructure will make it much easier to add MSG support. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-10-11 10:16:13 +00:00
free_pages(pages, order);
[SPARC64]: Enable MSI on sun4u Fire PCI-E controllers. The support code is identical to the hypervisor sun4v stuff, just replacing the hypervisor calls with register reads and writes in the Fire controller. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-08-31 05:33:25 +00:00
[SPARC64]: Consolidate MSI support code. This also makes us use the MSI queues correctly. Each MSI queue is serviced by a normal sun4u/sun4v INO interrupt handler. This handler runs the MSI queue and dispatches the virtual interrupts indicated by arriving MSIs in that MSI queue. All of the common logic is placed in pci_msi.c, with callbacks to handle the PCI controller specific aspects of the operations. This common infrastructure will make it much easier to add MSG support. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-10-11 10:16:13 +00:00
pbm->msi_queues = NULL;
[SPARC64]: Enable MSI on sun4u Fire PCI-E controllers. The support code is identical to the hypervisor sun4v stuff, just replacing the hypervisor calls with register reads and writes in the Fire controller. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-08-31 05:33:25 +00:00
}
[SPARC64]: Consolidate MSI support code. This also makes us use the MSI queues correctly. Each MSI queue is serviced by a normal sun4u/sun4v INO interrupt handler. This handler runs the MSI queue and dispatches the virtual interrupts indicated by arriving MSIs in that MSI queue. All of the common logic is placed in pci_msi.c, with callbacks to handle the PCI controller specific aspects of the operations. This common infrastructure will make it much easier to add MSG support. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-10-11 10:16:13 +00:00
static int pci_fire_msiq_build_irq(struct pci_pbm_info *pbm,
unsigned long msiqid,
unsigned long devino)
[SPARC64]: Enable MSI on sun4u Fire PCI-E controllers. The support code is identical to the hypervisor sun4v stuff, just replacing the hypervisor calls with register reads and writes in the Fire controller. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-08-31 05:33:25 +00:00
{
[SPARC64]: Consolidate MSI support code. This also makes us use the MSI queues correctly. Each MSI queue is serviced by a normal sun4u/sun4v INO interrupt handler. This handler runs the MSI queue and dispatches the virtual interrupts indicated by arriving MSIs in that MSI queue. All of the common logic is placed in pci_msi.c, with callbacks to handle the PCI controller specific aspects of the operations. This common infrastructure will make it much easier to add MSG support. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-10-11 10:16:13 +00:00
unsigned long cregs = (unsigned long) pbm->pbm_regs;
unsigned long imap_reg, iclr_reg, int_ctrlr;
sparc64: rename virt_irq => irq - II The generic irq support uses the term 'irq' for the allocated irq number. Fix it so sparc64 use the same term for an irq as the generic irq support does. For a naive reader this is less confusing. Signed-off-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: David S. Miller <davem@davemloft.net>
2011-01-22 11:32:20 +00:00
unsigned int irq;
[SPARC64]: Consolidate MSI support code. This also makes us use the MSI queues correctly. Each MSI queue is serviced by a normal sun4u/sun4v INO interrupt handler. This handler runs the MSI queue and dispatches the virtual interrupts indicated by arriving MSIs in that MSI queue. All of the common logic is placed in pci_msi.c, with callbacks to handle the PCI controller specific aspects of the operations. This common infrastructure will make it much easier to add MSG support. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-10-11 10:16:13 +00:00
int fixup;
[SPARC64]: Enable MSI on sun4u Fire PCI-E controllers. The support code is identical to the hypervisor sun4v stuff, just replacing the hypervisor calls with register reads and writes in the Fire controller. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-08-31 05:33:25 +00:00
u64 val;
[SPARC64]: Consolidate MSI support code. This also makes us use the MSI queues correctly. Each MSI queue is serviced by a normal sun4u/sun4v INO interrupt handler. This handler runs the MSI queue and dispatches the virtual interrupts indicated by arriving MSIs in that MSI queue. All of the common logic is placed in pci_msi.c, with callbacks to handle the PCI controller specific aspects of the operations. This common infrastructure will make it much easier to add MSG support. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-10-11 10:16:13 +00:00
imap_reg = cregs + (0x001000UL + (devino * 0x08UL));
iclr_reg = cregs + (0x001400UL + (devino * 0x08UL));
[SPARC64]: Enable MSI on sun4u Fire PCI-E controllers. The support code is identical to the hypervisor sun4v stuff, just replacing the hypervisor calls with register reads and writes in the Fire controller. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-08-31 05:33:25 +00:00
[SPARC64]: Consolidate MSI support code. This also makes us use the MSI queues correctly. Each MSI queue is serviced by a normal sun4u/sun4v INO interrupt handler. This handler runs the MSI queue and dispatches the virtual interrupts indicated by arriving MSIs in that MSI queue. All of the common logic is placed in pci_msi.c, with callbacks to handle the PCI controller specific aspects of the operations. This common infrastructure will make it much easier to add MSG support. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-10-11 10:16:13 +00:00
/* XXX iterate amongst the 4 IRQ controllers XXX */
int_ctrlr = (1UL << 6);
[SPARC64]: Enable MSI on sun4u Fire PCI-E controllers. The support code is identical to the hypervisor sun4v stuff, just replacing the hypervisor calls with register reads and writes in the Fire controller. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-08-31 05:33:25 +00:00
sparc64: Kill hand-crafted I/O accessors in PCI controller drivers. Use existing upa_{read,write}q() interfaces instead. Signed-off-by: David S. Miller <davem@davemloft.net>
2008-09-10 11:13:10 +00:00
val = upa_readq(imap_reg);
[SPARC64]: Consolidate MSI support code. This also makes us use the MSI queues correctly. Each MSI queue is serviced by a normal sun4u/sun4v INO interrupt handler. This handler runs the MSI queue and dispatches the virtual interrupts indicated by arriving MSIs in that MSI queue. All of the common logic is placed in pci_msi.c, with callbacks to handle the PCI controller specific aspects of the operations. This common infrastructure will make it much easier to add MSG support. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-10-11 10:16:13 +00:00
val |= (1UL << 63) | int_ctrlr;
sparc64: Kill hand-crafted I/O accessors in PCI controller drivers. Use existing upa_{read,write}q() interfaces instead. Signed-off-by: David S. Miller <davem@davemloft.net>
2008-09-10 11:13:10 +00:00
upa_writeq(val, imap_reg);
[SPARC64]: Enable MSI on sun4u Fire PCI-E controllers. The support code is identical to the hypervisor sun4v stuff, just replacing the hypervisor calls with register reads and writes in the Fire controller. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-08-31 05:33:25 +00:00
[SPARC64]: Consolidate MSI support code. This also makes us use the MSI queues correctly. Each MSI queue is serviced by a normal sun4u/sun4v INO interrupt handler. This handler runs the MSI queue and dispatches the virtual interrupts indicated by arriving MSIs in that MSI queue. All of the common logic is placed in pci_msi.c, with callbacks to handle the PCI controller specific aspects of the operations. This common infrastructure will make it much easier to add MSG support. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-10-11 10:16:13 +00:00
fixup = ((pbm->portid << 6) | devino) - int_ctrlr;
[SPARC64]: Enable MSI on sun4u Fire PCI-E controllers. The support code is identical to the hypervisor sun4v stuff, just replacing the hypervisor calls with register reads and writes in the Fire controller. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-08-31 05:33:25 +00:00
sparc64: rename virt_irq => irq - II The generic irq support uses the term 'irq' for the allocated irq number. Fix it so sparc64 use the same term for an irq as the generic irq support does. For a naive reader this is less confusing. Signed-off-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: David S. Miller <davem@davemloft.net>
2011-01-22 11:32:20 +00:00
irq = build_irq(fixup, iclr_reg, imap_reg);
if (!irq)
[SPARC64]: Consolidate MSI support code. This also makes us use the MSI queues correctly. Each MSI queue is serviced by a normal sun4u/sun4v INO interrupt handler. This handler runs the MSI queue and dispatches the virtual interrupts indicated by arriving MSIs in that MSI queue. All of the common logic is placed in pci_msi.c, with callbacks to handle the PCI controller specific aspects of the operations. This common infrastructure will make it much easier to add MSG support. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-10-11 10:16:13 +00:00
return -ENOMEM;
[SPARC64]: Enable MSI on sun4u Fire PCI-E controllers. The support code is identical to the hypervisor sun4v stuff, just replacing the hypervisor calls with register reads and writes in the Fire controller. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-08-31 05:33:25 +00:00
sparc64: Kill hand-crafted I/O accessors in PCI controller drivers. Use existing upa_{read,write}q() interfaces instead. Signed-off-by: David S. Miller <davem@davemloft.net>
2008-09-10 11:13:10 +00:00
upa_writeq(EVENT_QUEUE_CONTROL_SET_EN,
pbm->pbm_regs + EVENT_QUEUE_CONTROL_SET(msiqid));
[SPARC64]: Enable MSI on sun4u Fire PCI-E controllers. The support code is identical to the hypervisor sun4v stuff, just replacing the hypervisor calls with register reads and writes in the Fire controller. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-08-31 05:33:25 +00:00
sparc64: rename virt_irq => irq - II The generic irq support uses the term 'irq' for the allocated irq number. Fix it so sparc64 use the same term for an irq as the generic irq support does. For a naive reader this is less confusing. Signed-off-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: David S. Miller <davem@davemloft.net>
2011-01-22 11:32:20 +00:00
return irq;
[SPARC64]: Enable MSI on sun4u Fire PCI-E controllers. The support code is identical to the hypervisor sun4v stuff, just replacing the hypervisor calls with register reads and writes in the Fire controller. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-08-31 05:33:25 +00:00
}
[SPARC64]: Consolidate MSI support code. This also makes us use the MSI queues correctly. Each MSI queue is serviced by a normal sun4u/sun4v INO interrupt handler. This handler runs the MSI queue and dispatches the virtual interrupts indicated by arriving MSIs in that MSI queue. All of the common logic is placed in pci_msi.c, with callbacks to handle the PCI controller specific aspects of the operations. This common infrastructure will make it much easier to add MSG support. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-10-11 10:16:13 +00:00
static const struct sparc64_msiq_ops pci_fire_msiq_ops = {
.get_head = pci_fire_get_head,
.dequeue_msi = pci_fire_dequeue_msi,
.set_head = pci_fire_set_head,
.msi_setup = pci_fire_msi_setup,
.msi_teardown = pci_fire_msi_teardown,
.msiq_alloc = pci_fire_msiq_alloc,
.msiq_free = pci_fire_msiq_free,
.msiq_build_irq = pci_fire_msiq_build_irq,
};
[SPARC64]: Enable MSI on sun4u Fire PCI-E controllers. The support code is identical to the hypervisor sun4v stuff, just replacing the hypervisor calls with register reads and writes in the Fire controller. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-08-31 05:33:25 +00:00
static void pci_fire_msi_init(struct pci_pbm_info *pbm)
{
[SPARC64]: Consolidate MSI support code. This also makes us use the MSI queues correctly. Each MSI queue is serviced by a normal sun4u/sun4v INO interrupt handler. This handler runs the MSI queue and dispatches the virtual interrupts indicated by arriving MSIs in that MSI queue. All of the common logic is placed in pci_msi.c, with callbacks to handle the PCI controller specific aspects of the operations. This common infrastructure will make it much easier to add MSG support. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-10-11 10:16:13 +00:00
sparc64_pbm_msi_init(pbm, &pci_fire_msiq_ops);
[SPARC64]: Enable MSI on sun4u Fire PCI-E controllers. The support code is identical to the hypervisor sun4v stuff, just replacing the hypervisor calls with register reads and writes in the Fire controller. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-08-31 05:33:25 +00:00
}
#else /* CONFIG_PCI_MSI */
static void pci_fire_msi_init(struct pci_pbm_info *pbm)
{
}
#endif /* !(CONFIG_PCI_MSI) */
[SPARC64]: SUN4U PCI-E controller support. Some minor refactoring in the generic code was necessary for this: 1) This controller requires 8-byte access to the interrupt map and clear register. They are 64-bits on all the other SBUS and PCI controllers anyways, so this was easy to cure. 2) The IMAP register has a different layout and some bits that we need to preserve, so use a read/modify/write when making changes to the IMAP register in generic code. 3) Flushing the entire IOMMU TLB is best done with a single write to a register on this PCI controller, add a iommu->iommu_flushinv for this. Still lacks MSI support, that will come later. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-05-03 00:31:36 +00:00
/* Based at pbm->controller_regs */
#define FIRE_PARITY_CONTROL 0x470010UL
#define FIRE_PARITY_ENAB 0x8000000000000000UL
#define FIRE_FATAL_RESET_CTL 0x471028UL
#define FIRE_FATAL_RESET_SPARE 0x0000000004000000UL
#define FIRE_FATAL_RESET_MB 0x0000000002000000UL
#define FIRE_FATAL_RESET_CPE 0x0000000000008000UL
#define FIRE_FATAL_RESET_APE 0x0000000000004000UL
#define FIRE_FATAL_RESET_PIO 0x0000000000000040UL
#define FIRE_FATAL_RESET_JW 0x0000000000000004UL
#define FIRE_FATAL_RESET_JI 0x0000000000000002UL
#define FIRE_FATAL_RESET_JR 0x0000000000000001UL
#define FIRE_CORE_INTR_ENABLE 0x471800UL
/* Based at pbm->pbm_regs */
#define FIRE_TLU_CTRL 0x80000UL
#define FIRE_TLU_CTRL_TIM 0x00000000da000000UL
#define FIRE_TLU_CTRL_QDET 0x0000000000000100UL
#define FIRE_TLU_CTRL_CFG 0x0000000000000001UL
#define FIRE_TLU_DEV_CTRL 0x90008UL
#define FIRE_TLU_LINK_CTRL 0x90020UL
#define FIRE_TLU_LINK_CTRL_CLK 0x0000000000000040UL
#define FIRE_LPU_RESET 0xe2008UL
#define FIRE_LPU_LLCFG 0xe2200UL
#define FIRE_LPU_LLCFG_VC0 0x0000000000000100UL
#define FIRE_LPU_FCTRL_UCTRL 0xe2240UL
#define FIRE_LPU_FCTRL_UCTRL_N 0x0000000000000002UL
#define FIRE_LPU_FCTRL_UCTRL_P 0x0000000000000001UL
#define FIRE_LPU_TXL_FIFOP 0xe2430UL
#define FIRE_LPU_LTSSM_CFG2 0xe2788UL
#define FIRE_LPU_LTSSM_CFG3 0xe2790UL
#define FIRE_LPU_LTSSM_CFG4 0xe2798UL
#define FIRE_LPU_LTSSM_CFG5 0xe27a0UL
#define FIRE_DMC_IENAB 0x31800UL
#define FIRE_DMC_DBG_SEL_A 0x53000UL
#define FIRE_DMC_DBG_SEL_B 0x53008UL
#define FIRE_PEC_IENAB 0x51800UL
static void pci_fire_hw_init(struct pci_pbm_info *pbm)
{
u64 val;
sparc64: Kill hand-crafted I/O accessors in PCI controller drivers. Use existing upa_{read,write}q() interfaces instead. Signed-off-by: David S. Miller <davem@davemloft.net>
2008-09-10 11:13:10 +00:00
upa_writeq(FIRE_PARITY_ENAB,
pbm->controller_regs + FIRE_PARITY_CONTROL);
[SPARC64]: SUN4U PCI-E controller support. Some minor refactoring in the generic code was necessary for this: 1) This controller requires 8-byte access to the interrupt map and clear register. They are 64-bits on all the other SBUS and PCI controllers anyways, so this was easy to cure. 2) The IMAP register has a different layout and some bits that we need to preserve, so use a read/modify/write when making changes to the IMAP register in generic code. 3) Flushing the entire IOMMU TLB is best done with a single write to a register on this PCI controller, add a iommu->iommu_flushinv for this. Still lacks MSI support, that will come later. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-05-03 00:31:36 +00:00
sparc64: Kill hand-crafted I/O accessors in PCI controller drivers. Use existing upa_{read,write}q() interfaces instead. Signed-off-by: David S. Miller <davem@davemloft.net>
2008-09-10 11:13:10 +00:00
upa_writeq((FIRE_FATAL_RESET_SPARE |
[SPARC64]: SUN4U PCI-E controller support. Some minor refactoring in the generic code was necessary for this: 1) This controller requires 8-byte access to the interrupt map and clear register. They are 64-bits on all the other SBUS and PCI controllers anyways, so this was easy to cure. 2) The IMAP register has a different layout and some bits that we need to preserve, so use a read/modify/write when making changes to the IMAP register in generic code. 3) Flushing the entire IOMMU TLB is best done with a single write to a register on this PCI controller, add a iommu->iommu_flushinv for this. Still lacks MSI support, that will come later. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-05-03 00:31:36 +00:00
FIRE_FATAL_RESET_MB |
FIRE_FATAL_RESET_CPE |
FIRE_FATAL_RESET_APE |
FIRE_FATAL_RESET_PIO |
FIRE_FATAL_RESET_JW |
FIRE_FATAL_RESET_JI |
sparc64: Kill hand-crafted I/O accessors in PCI controller drivers. Use existing upa_{read,write}q() interfaces instead. Signed-off-by: David S. Miller <davem@davemloft.net>
2008-09-10 11:13:10 +00:00
FIRE_FATAL_RESET_JR),
pbm->controller_regs + FIRE_FATAL_RESET_CTL);
[SPARC64]: SUN4U PCI-E controller support. Some minor refactoring in the generic code was necessary for this: 1) This controller requires 8-byte access to the interrupt map and clear register. They are 64-bits on all the other SBUS and PCI controllers anyways, so this was easy to cure. 2) The IMAP register has a different layout and some bits that we need to preserve, so use a read/modify/write when making changes to the IMAP register in generic code. 3) Flushing the entire IOMMU TLB is best done with a single write to a register on this PCI controller, add a iommu->iommu_flushinv for this. Still lacks MSI support, that will come later. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-05-03 00:31:36 +00:00
sparc64: Kill hand-crafted I/O accessors in PCI controller drivers. Use existing upa_{read,write}q() interfaces instead. Signed-off-by: David S. Miller <davem@davemloft.net>
2008-09-10 11:13:10 +00:00
upa_writeq(~(u64)0, pbm->controller_regs + FIRE_CORE_INTR_ENABLE);
[SPARC64]: SUN4U PCI-E controller support. Some minor refactoring in the generic code was necessary for this: 1) This controller requires 8-byte access to the interrupt map and clear register. They are 64-bits on all the other SBUS and PCI controllers anyways, so this was easy to cure. 2) The IMAP register has a different layout and some bits that we need to preserve, so use a read/modify/write when making changes to the IMAP register in generic code. 3) Flushing the entire IOMMU TLB is best done with a single write to a register on this PCI controller, add a iommu->iommu_flushinv for this. Still lacks MSI support, that will come later. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-05-03 00:31:36 +00:00
sparc64: Kill hand-crafted I/O accessors in PCI controller drivers. Use existing upa_{read,write}q() interfaces instead. Signed-off-by: David S. Miller <davem@davemloft.net>
2008-09-10 11:13:10 +00:00
val = upa_readq(pbm->pbm_regs + FIRE_TLU_CTRL);
[SPARC64]: SUN4U PCI-E controller support. Some minor refactoring in the generic code was necessary for this: 1) This controller requires 8-byte access to the interrupt map and clear register. They are 64-bits on all the other SBUS and PCI controllers anyways, so this was easy to cure. 2) The IMAP register has a different layout and some bits that we need to preserve, so use a read/modify/write when making changes to the IMAP register in generic code. 3) Flushing the entire IOMMU TLB is best done with a single write to a register on this PCI controller, add a iommu->iommu_flushinv for this. Still lacks MSI support, that will come later. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-05-03 00:31:36 +00:00
val |= (FIRE_TLU_CTRL_TIM |
FIRE_TLU_CTRL_QDET |
FIRE_TLU_CTRL_CFG);
sparc64: Kill hand-crafted I/O accessors in PCI controller drivers. Use existing upa_{read,write}q() interfaces instead. Signed-off-by: David S. Miller <davem@davemloft.net>
2008-09-10 11:13:10 +00:00
upa_writeq(val, pbm->pbm_regs + FIRE_TLU_CTRL);
upa_writeq(0, pbm->pbm_regs + FIRE_TLU_DEV_CTRL);
upa_writeq(FIRE_TLU_LINK_CTRL_CLK,
pbm->pbm_regs + FIRE_TLU_LINK_CTRL);
upa_writeq(0, pbm->pbm_regs + FIRE_LPU_RESET);
upa_writeq(FIRE_LPU_LLCFG_VC0, pbm->pbm_regs + FIRE_LPU_LLCFG);
upa_writeq((FIRE_LPU_FCTRL_UCTRL_N | FIRE_LPU_FCTRL_UCTRL_P),
pbm->pbm_regs + FIRE_LPU_FCTRL_UCTRL);
upa_writeq(((0xffff << 16) | (0x0000 << 0)),
pbm->pbm_regs + FIRE_LPU_TXL_FIFOP);
upa_writeq(3000000, pbm->pbm_regs + FIRE_LPU_LTSSM_CFG2);
upa_writeq(500000, pbm->pbm_regs + FIRE_LPU_LTSSM_CFG3);
upa_writeq((2 << 16) | (140 << 8),
pbm->pbm_regs + FIRE_LPU_LTSSM_CFG4);
upa_writeq(0, pbm->pbm_regs + FIRE_LPU_LTSSM_CFG5);
upa_writeq(~(u64)0, pbm->pbm_regs + FIRE_DMC_IENAB);
upa_writeq(0, pbm->pbm_regs + FIRE_DMC_DBG_SEL_A);
upa_writeq(0, pbm->pbm_regs + FIRE_DMC_DBG_SEL_B);
upa_writeq(~(u64)0, pbm->pbm_regs + FIRE_PEC_IENAB);
[SPARC64]: SUN4U PCI-E controller support. Some minor refactoring in the generic code was necessary for this: 1) This controller requires 8-byte access to the interrupt map and clear register. They are 64-bits on all the other SBUS and PCI controllers anyways, so this was easy to cure. 2) The IMAP register has a different layout and some bits that we need to preserve, so use a read/modify/write when making changes to the IMAP register in generic code. 3) Flushing the entire IOMMU TLB is best done with a single write to a register on this PCI controller, add a iommu->iommu_flushinv for this. Still lacks MSI support, that will come later. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-05-03 00:31:36 +00:00
}
SPARC: drivers: remove __dev* attributes. CONFIG_HOTPLUG is going away as an option. As a result, the __dev* markings need to be removed. This change removes the use of __devinit, __devexit_p, __devinitdata, and __devexit from these drivers. Based on patches originally written by Bill Pemberton, but redone by me in order to handle some of the coding style issues better, by hand. Cc: Bill Pemberton <wfp5p@virginia.edu> Cc: "David S. Miller" <davem@davemloft.net> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2012-12-21 22:03:26 +00:00
static int pci_fire_pbm_init(struct pci_pbm_info *pbm,
struct platform_device *op, u32 portid)
[SPARC64]: SUN4U PCI-E controller support. Some minor refactoring in the generic code was necessary for this: 1) This controller requires 8-byte access to the interrupt map and clear register. They are 64-bits on all the other SBUS and PCI controllers anyways, so this was easy to cure. 2) The IMAP register has a different layout and some bits that we need to preserve, so use a read/modify/write when making changes to the IMAP register in generic code. 3) Flushing the entire IOMMU TLB is best done with a single write to a register on this PCI controller, add a iommu->iommu_flushinv for this. Still lacks MSI support, that will come later. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-05-03 00:31:36 +00:00
{
const struct linux_prom64_registers *regs;
of: Always use 'struct device.of_node' to get device node pointer. The following structure elements duplicate the information in 'struct device.of_node' and so are being eliminated. This patch makes all readers of these elements use device.of_node instead. (struct of_device *)->node (struct dev_archdata *)->prom_node (sparc) (struct dev_archdata *)->of_node (powerpc & microblaze) Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2010-04-13 23:12:29 +00:00
struct device_node *dp = op->dev.of_node;
[SPARC64]: Enable MSI on sun4u Fire PCI-E controllers. The support code is identical to the hypervisor sun4v stuff, just replacing the hypervisor calls with register reads and writes in the Fire controller. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-08-31 05:33:25 +00:00
int err;
[SPARC64]: SUN4U PCI-E controller support. Some minor refactoring in the generic code was necessary for this: 1) This controller requires 8-byte access to the interrupt map and clear register. They are 64-bits on all the other SBUS and PCI controllers anyways, so this was easy to cure. 2) The IMAP register has a different layout and some bits that we need to preserve, so use a read/modify/write when making changes to the IMAP register in generic code. 3) Flushing the entire IOMMU TLB is best done with a single write to a register on this PCI controller, add a iommu->iommu_flushinv for this. Still lacks MSI support, that will come later. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-05-03 00:31:36 +00:00
[SPARC64]: NUMA device infrastructure. Record and propagate NUMA information for devices. Signed-off-by: David S. Miller <davem@davemloft.net>
2008-03-19 11:52:48 +00:00
pbm->numa_node = -1;
[SPARC64] PCI: Consolidate PCI access code into pci_common.c All the sun4u controllers do the same thing to compute the physical I/O address to poke, and we can move the sun4v code into this common location too. This one needs a bit of testing, in particular the Sabre code had some funny stuff that would break up u16 and/or u32 accesses into pieces and I didn't think that was needed any more. If it is we need to find out why and add back code to do it again. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-05-09 09:35:27 +00:00
pbm->pci_ops = &sun4u_pci_ops;
pbm->config_space_reg_bits = 12;
[SPARC64] PCI: Use root list of pbm's instead of pci_controller_info's The idea is to move more and more things into the pbm, with the eventual goal of eliminating the pci_controller_info entirely as there really isn't any need for it. This stage of the transformations requires some reworking of the PCI error interrupt handling. It might be tricky to get rid of the pci_controller_info parenting for a few reasons: 1) When we get an uncorrectable or correctable error we want to interrogate the IOMMU and streaming cache of both PBMs for error status. These errors come from the UPA front-end which is shared between the two PBM PCI bus segments. Historically speaking this is why I choose the datastructure hierarchy of pci_controller_info-->pci_pbm_info 2) The probing does a portid/devhandle match to look for the 'other' pbm, but this is entirely an artifact and can be eliminated trivially. What we could do to solve #1 is to have a "buddy" pointer from one pbm to another. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-05-08 06:06:27 +00:00
[SPARC64]: Move index info pci_pbm_info. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-05-08 06:49:01 +00:00
pbm->index = pci_num_pbms++;
[SPARC64]: SUN4U PCI-E controller support. Some minor refactoring in the generic code was necessary for this: 1) This controller requires 8-byte access to the interrupt map and clear register. They are 64-bits on all the other SBUS and PCI controllers anyways, so this was easy to cure. 2) The IMAP register has a different layout and some bits that we need to preserve, so use a read/modify/write when making changes to the IMAP register in generic code. 3) Flushing the entire IOMMU TLB is best done with a single write to a register on this PCI controller, add a iommu->iommu_flushinv for this. Still lacks MSI support, that will come later. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-05-03 00:31:36 +00:00
pbm->portid = portid;
sparc64: Record OF device instead of device node pointer in pci_pbm_info. Signed-off-by: David S. Miller <davem@davemloft.net>
2008-09-10 07:19:28 +00:00
pbm->op = op;
[SPARC64]: SUN4U PCI-E controller support. Some minor refactoring in the generic code was necessary for this: 1) This controller requires 8-byte access to the interrupt map and clear register. They are 64-bits on all the other SBUS and PCI controllers anyways, so this was easy to cure. 2) The IMAP register has a different layout and some bits that we need to preserve, so use a read/modify/write when making changes to the IMAP register in generic code. 3) Flushing the entire IOMMU TLB is best done with a single write to a register on this PCI controller, add a iommu->iommu_flushinv for this. Still lacks MSI support, that will come later. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-05-03 00:31:36 +00:00
pbm->name = dp->full_name;
regs = of_get_property(dp, "reg", NULL);
pbm->pbm_regs = regs[0].phys_addr;
pbm->controller_regs = regs[1].phys_addr - 0x410000UL;
printk("%s: SUN4U PCIE Bus Module\n", pbm->name);
pci_determine_mem_io_space(pbm);
[SPARC64] PCI: Use common routine to fetch PBM properties. Namely bus-range and ino-bitmap. This allows us also to eliminate pci_controller_info's pci_{first,last}_busno fields as only the pbm ones are used now. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-05-08 04:51:41 +00:00
pci_get_pbm_props(pbm);
[SPARC64]: SUN4U PCI-E controller support. Some minor refactoring in the generic code was necessary for this: 1) This controller requires 8-byte access to the interrupt map and clear register. They are 64-bits on all the other SBUS and PCI controllers anyways, so this was easy to cure. 2) The IMAP register has a different layout and some bits that we need to preserve, so use a read/modify/write when making changes to the IMAP register in generic code. 3) Flushing the entire IOMMU TLB is best done with a single write to a register on this PCI controller, add a iommu->iommu_flushinv for this. Still lacks MSI support, that will come later. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-05-03 00:31:36 +00:00
pci_fire_hw_init(pbm);
[SPARC64]: Fix conflicts in SBUS/PCI/EBUS/ISA DMA handling. Fully unify all of the DMA ops so that subordinate bus types to the DMA operation providers (such as ebus, isa, of_device) can work transparently. Basically, we just make sure that for every system device we create, the dev->archdata 'iommu' and 'stc' fields are filled in. Then we have two platform variants of the DMA ops, one for SUN4U which actually programs the real hardware, and one for SUN4V which makes hypervisor calls. This also fixes the crashes in parport_pc on sparc64, reported by Meelis Roos. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-07-28 05:39:14 +00:00
[SPARC64]: Enable MSI on sun4u Fire PCI-E controllers. The support code is identical to the hypervisor sun4v stuff, just replacing the hypervisor calls with register reads and writes in the Fire controller. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-08-31 05:33:25 +00:00
err = pci_fire_pbm_iommu_init(pbm);
if (err)
return err;
pci_fire_msi_init(pbm);
sparc64: Pass proper parent device down into root pci_create_bus() call. Signed-off-by: David S. Miller <davem@davemloft.net>
2008-09-02 01:32:22 +00:00
pbm->pci_bus = pci_scan_one_pbm(pbm, &op->dev);
/* XXX register error interrupt handlers XXX */
sparc64: Convert FIRE PCI controller driver into a real driver. And now all the by-hand PCI controller probing junk in pci.c can die too. Signed-off-by: David S. Miller <davem@davemloft.net>
2008-08-30 10:12:38 +00:00
sparc64: Get rid of pci_controller_info. It is just used as a parent to encapsulate two PBM objects. But that layout is only really relevant and necessary for psycho PCI controllers, which unlike all the others share a single IOMMU instance between sibling PCI busses. Signed-off-by: David S. Miller <davem@davemloft.net>
2008-09-10 06:54:02 +00:00
pbm->next = pci_pbm_root;
pci_pbm_root = pbm;
[SPARC64]: SUN4U PCI-E controller support. Some minor refactoring in the generic code was necessary for this: 1) This controller requires 8-byte access to the interrupt map and clear register. They are 64-bits on all the other SBUS and PCI controllers anyways, so this was easy to cure. 2) The IMAP register has a different layout and some bits that we need to preserve, so use a read/modify/write when making changes to the IMAP register in generic code. 3) Flushing the entire IOMMU TLB is best done with a single write to a register on this PCI controller, add a iommu->iommu_flushinv for this. Still lacks MSI support, that will come later. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-05-03 00:31:36 +00:00
return 0;
}
SPARC: drivers: remove __dev* attributes. CONFIG_HOTPLUG is going away as an option. As a result, the __dev* markings need to be removed. This change removes the use of __devinit, __devexit_p, __devinitdata, and __devexit from these drivers. Based on patches originally written by Bill Pemberton, but redone by me in order to handle some of the coding style issues better, by hand. Cc: Bill Pemberton <wfp5p@virginia.edu> Cc: "David S. Miller" <davem@davemloft.net> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2012-12-21 22:03:26 +00:00
static int fire_probe(struct platform_device *op)
[SPARC64]: SUN4U PCI-E controller support. Some minor refactoring in the generic code was necessary for this: 1) This controller requires 8-byte access to the interrupt map and clear register. They are 64-bits on all the other SBUS and PCI controllers anyways, so this was easy to cure. 2) The IMAP register has a different layout and some bits that we need to preserve, so use a read/modify/write when making changes to the IMAP register in generic code. 3) Flushing the entire IOMMU TLB is best done with a single write to a register on this PCI controller, add a iommu->iommu_flushinv for this. Still lacks MSI support, that will come later. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-05-03 00:31:36 +00:00
{
of: Always use 'struct device.of_node' to get device node pointer. The following structure elements duplicate the information in 'struct device.of_node' and so are being eliminated. This patch makes all readers of these elements use device.of_node instead. (struct of_device *)->node (struct dev_archdata *)->prom_node (sparc) (struct dev_archdata *)->of_node (powerpc & microblaze) Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2010-04-13 23:12:29 +00:00
struct device_node *dp = op->dev.of_node;
[SPARC64] PCI: Use root list of pbm's instead of pci_controller_info's The idea is to move more and more things into the pbm, with the eventual goal of eliminating the pci_controller_info entirely as there really isn't any need for it. This stage of the transformations requires some reworking of the PCI error interrupt handling. It might be tricky to get rid of the pci_controller_info parenting for a few reasons: 1) When we get an uncorrectable or correctable error we want to interrogate the IOMMU and streaming cache of both PBMs for error status. These errors come from the UPA front-end which is shared between the two PBM PCI bus segments. Historically speaking this is why I choose the datastructure hierarchy of pci_controller_info-->pci_pbm_info 2) The probing does a portid/devhandle match to look for the 'other' pbm, but this is entirely an artifact and can be eliminated trivially. What we could do to solve #1 is to have a "buddy" pointer from one pbm to another. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-05-08 06:06:27 +00:00
struct pci_pbm_info *pbm;
sparc64: Convert FIRE PCI controller driver into a real driver. And now all the by-hand PCI controller probing junk in pci.c can die too. Signed-off-by: David S. Miller <davem@davemloft.net>
2008-08-30 10:12:38 +00:00
struct iommu *iommu;
u32 portid;
int err;
[SPARC64]: SUN4U PCI-E controller support. Some minor refactoring in the generic code was necessary for this: 1) This controller requires 8-byte access to the interrupt map and clear register. They are 64-bits on all the other SBUS and PCI controllers anyways, so this was easy to cure. 2) The IMAP register has a different layout and some bits that we need to preserve, so use a read/modify/write when making changes to the IMAP register in generic code. 3) Flushing the entire IOMMU TLB is best done with a single write to a register on this PCI controller, add a iommu->iommu_flushinv for this. Still lacks MSI support, that will come later. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-05-03 00:31:36 +00:00
sparc64: Convert FIRE PCI controller driver into a real driver. And now all the by-hand PCI controller probing junk in pci.c can die too. Signed-off-by: David S. Miller <davem@davemloft.net>
2008-08-30 10:12:38 +00:00
portid = of_getintprop_default(dp, "portid", 0xff);
[SPARC64]: SUN4U PCI-E controller support. Some minor refactoring in the generic code was necessary for this: 1) This controller requires 8-byte access to the interrupt map and clear register. They are 64-bits on all the other SBUS and PCI controllers anyways, so this was easy to cure. 2) The IMAP register has a different layout and some bits that we need to preserve, so use a read/modify/write when making changes to the IMAP register in generic code. 3) Flushing the entire IOMMU TLB is best done with a single write to a register on this PCI controller, add a iommu->iommu_flushinv for this. Still lacks MSI support, that will come later. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-05-03 00:31:36 +00:00
sparc64: Convert FIRE PCI controller driver into a real driver. And now all the by-hand PCI controller probing junk in pci.c can die too. Signed-off-by: David S. Miller <davem@davemloft.net>
2008-08-30 10:12:38 +00:00
err = -ENOMEM;
sparc64: Get rid of pci_controller_info. It is just used as a parent to encapsulate two PBM objects. But that layout is only really relevant and necessary for psycho PCI controllers, which unlike all the others share a single IOMMU instance between sibling PCI busses. Signed-off-by: David S. Miller <davem@davemloft.net>
2008-09-10 06:54:02 +00:00
pbm = kzalloc(sizeof(*pbm), GFP_KERNEL);
if (!pbm) {
printk(KERN_ERR PFX "Cannot allocate pci_pbminfo.\n");
sparc64: Simplify error handling in PCI controller probing. Based upon suggestions from Stephen Rothwell. Signed-off-by: David S. Miller <davem@davemloft.net>
2008-08-31 08:33:52 +00:00
goto out_err;
sparc64: Convert FIRE PCI controller driver into a real driver. And now all the by-hand PCI controller probing junk in pci.c can die too. Signed-off-by: David S. Miller <davem@davemloft.net>
2008-08-30 10:12:38 +00:00
}
[SPARC64]: SUN4U PCI-E controller support. Some minor refactoring in the generic code was necessary for this: 1) This controller requires 8-byte access to the interrupt map and clear register. They are 64-bits on all the other SBUS and PCI controllers anyways, so this was easy to cure. 2) The IMAP register has a different layout and some bits that we need to preserve, so use a read/modify/write when making changes to the IMAP register in generic code. 3) Flushing the entire IOMMU TLB is best done with a single write to a register on this PCI controller, add a iommu->iommu_flushinv for this. Still lacks MSI support, that will come later. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-05-03 00:31:36 +00:00
sparc64: Get rid of pci_controller_info. It is just used as a parent to encapsulate two PBM objects. But that layout is only really relevant and necessary for psycho PCI controllers, which unlike all the others share a single IOMMU instance between sibling PCI busses. Signed-off-by: David S. Miller <davem@davemloft.net>
2008-09-10 06:54:02 +00:00
iommu = kzalloc(sizeof(struct iommu), GFP_KERNEL);
sparc64: Convert FIRE PCI controller driver into a real driver. And now all the by-hand PCI controller probing junk in pci.c can die too. Signed-off-by: David S. Miller <davem@davemloft.net>
2008-08-30 10:12:38 +00:00
if (!iommu) {
sparc64: Get rid of pci_controller_info. It is just used as a parent to encapsulate two PBM objects. But that layout is only really relevant and necessary for psycho PCI controllers, which unlike all the others share a single IOMMU instance between sibling PCI busses. Signed-off-by: David S. Miller <davem@davemloft.net>
2008-09-10 06:54:02 +00:00
printk(KERN_ERR PFX "Cannot allocate PBM iommu.\n");
sparc64: Simplify error handling in PCI controller probing. Based upon suggestions from Stephen Rothwell. Signed-off-by: David S. Miller <davem@davemloft.net>
2008-08-31 08:33:52 +00:00
goto out_free_controller;
sparc64: Convert FIRE PCI controller driver into a real driver. And now all the by-hand PCI controller probing junk in pci.c can die too. Signed-off-by: David S. Miller <davem@davemloft.net>
2008-08-30 10:12:38 +00:00
}
[SPARC64]: SUN4U PCI-E controller support. Some minor refactoring in the generic code was necessary for this: 1) This controller requires 8-byte access to the interrupt map and clear register. They are 64-bits on all the other SBUS and PCI controllers anyways, so this was easy to cure. 2) The IMAP register has a different layout and some bits that we need to preserve, so use a read/modify/write when making changes to the IMAP register in generic code. 3) Flushing the entire IOMMU TLB is best done with a single write to a register on this PCI controller, add a iommu->iommu_flushinv for this. Still lacks MSI support, that will come later. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-05-03 00:31:36 +00:00
sparc64: Get rid of pci_controller_info. It is just used as a parent to encapsulate two PBM objects. But that layout is only really relevant and necessary for psycho PCI controllers, which unlike all the others share a single IOMMU instance between sibling PCI busses. Signed-off-by: David S. Miller <davem@davemloft.net>
2008-09-10 06:54:02 +00:00
pbm->iommu = iommu;
[SPARC64]: SUN4U PCI-E controller support. Some minor refactoring in the generic code was necessary for this: 1) This controller requires 8-byte access to the interrupt map and clear register. They are 64-bits on all the other SBUS and PCI controllers anyways, so this was easy to cure. 2) The IMAP register has a different layout and some bits that we need to preserve, so use a read/modify/write when making changes to the IMAP register in generic code. 3) Flushing the entire IOMMU TLB is best done with a single write to a register on this PCI controller, add a iommu->iommu_flushinv for this. Still lacks MSI support, that will come later. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-05-03 00:31:36 +00:00
sparc64: Get rid of pci_controller_info. It is just used as a parent to encapsulate two PBM objects. But that layout is only really relevant and necessary for psycho PCI controllers, which unlike all the others share a single IOMMU instance between sibling PCI busses. Signed-off-by: David S. Miller <davem@davemloft.net>
2008-09-10 06:54:02 +00:00
err = pci_fire_pbm_init(pbm, op, portid);
if (err)
goto out_free_iommu;
[SPARC64]: SUN4U PCI-E controller support. Some minor refactoring in the generic code was necessary for this: 1) This controller requires 8-byte access to the interrupt map and clear register. They are 64-bits on all the other SBUS and PCI controllers anyways, so this was easy to cure. 2) The IMAP register has a different layout and some bits that we need to preserve, so use a read/modify/write when making changes to the IMAP register in generic code. 3) Flushing the entire IOMMU TLB is best done with a single write to a register on this PCI controller, add a iommu->iommu_flushinv for this. Still lacks MSI support, that will come later. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-05-03 00:31:36 +00:00
sparc64: Get rid of pci_controller_info. It is just used as a parent to encapsulate two PBM objects. But that layout is only really relevant and necessary for psycho PCI controllers, which unlike all the others share a single IOMMU instance between sibling PCI busses. Signed-off-by: David S. Miller <davem@davemloft.net>
2008-09-10 06:54:02 +00:00
dev_set_drvdata(&op->dev, pbm);
[SPARC64]: SUN4U PCI-E controller support. Some minor refactoring in the generic code was necessary for this: 1) This controller requires 8-byte access to the interrupt map and clear register. They are 64-bits on all the other SBUS and PCI controllers anyways, so this was easy to cure. 2) The IMAP register has a different layout and some bits that we need to preserve, so use a read/modify/write when making changes to the IMAP register in generic code. 3) Flushing the entire IOMMU TLB is best done with a single write to a register on this PCI controller, add a iommu->iommu_flushinv for this. Still lacks MSI support, that will come later. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-05-03 00:31:36 +00:00
sparc64: Get rid of pci_controller_info. It is just used as a parent to encapsulate two PBM objects. But that layout is only really relevant and necessary for psycho PCI controllers, which unlike all the others share a single IOMMU instance between sibling PCI busses. Signed-off-by: David S. Miller <davem@davemloft.net>
2008-09-10 06:54:02 +00:00
return 0;
[SPARC64]: Fix conflicts in SBUS/PCI/EBUS/ISA DMA handling. Fully unify all of the DMA ops so that subordinate bus types to the DMA operation providers (such as ebus, isa, of_device) can work transparently. Basically, we just make sure that for every system device we create, the dev->archdata 'iommu' and 'stc' fields are filled in. Then we have two platform variants of the DMA ops, one for SUN4U which actually programs the real hardware, and one for SUN4V which makes hypervisor calls. This also fixes the crashes in parport_pc on sparc64, reported by Meelis Roos. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-07-28 05:39:14 +00:00
sparc64: Get rid of pci_controller_info. It is just used as a parent to encapsulate two PBM objects. But that layout is only really relevant and necessary for psycho PCI controllers, which unlike all the others share a single IOMMU instance between sibling PCI busses. Signed-off-by: David S. Miller <davem@davemloft.net>
2008-09-10 06:54:02 +00:00
out_free_iommu:
kfree(pbm->iommu);
sparc64: Simplify error handling in PCI controller probing. Based upon suggestions from Stephen Rothwell. Signed-off-by: David S. Miller <davem@davemloft.net>
2008-08-31 08:33:52 +00:00
out_free_controller:
sparc64: Get rid of pci_controller_info. It is just used as a parent to encapsulate two PBM objects. But that layout is only really relevant and necessary for psycho PCI controllers, which unlike all the others share a single IOMMU instance between sibling PCI busses. Signed-off-by: David S. Miller <davem@davemloft.net>
2008-09-10 06:54:02 +00:00
kfree(pbm);
sparc64: Simplify error handling in PCI controller probing. Based upon suggestions from Stephen Rothwell. Signed-off-by: David S. Miller <davem@davemloft.net>
2008-08-31 08:33:52 +00:00
out_err:
sparc64: Convert FIRE PCI controller driver into a real driver. And now all the by-hand PCI controller probing junk in pci.c can die too. Signed-off-by: David S. Miller <davem@davemloft.net>
2008-08-30 10:12:38 +00:00
return err;
}
sparc64: Fix section mis-match errors. Fix all of the problems spotted by CONFIG_DEBUG_SECTION_MISMATCH under arch/sparc during a 64-bit defconfig build. They fall into two categorites: 1) of_device_id is marked as __initdata, and we can never do this since these objects sit in the device core data structures way past boot. So even if a driver will never be reloaded, we have to keep the device ID table around. Mark such cases const instead. 2) The bootmem alloc/free handling code in mdesc.c was not fully marked __init as it should be, thus generating a reference to free_bootmem_late() (which is __init) from non-__init code. Signed-off-by: David S. Miller <davem@davemloft.net>
2011-03-31 00:37:56 +00:00
static const struct of_device_id fire_match[] = {
sparc64: Convert FIRE PCI controller driver into a real driver. And now all the by-hand PCI controller probing junk in pci.c can die too. Signed-off-by: David S. Miller <davem@davemloft.net>
2008-08-30 10:12:38 +00:00
{
.name = "pci",
.compatible = "pciex108e,80f0",
},
{},
};
[SPARC64]: SUN4U PCI-E controller support. Some minor refactoring in the generic code was necessary for this: 1) This controller requires 8-byte access to the interrupt map and clear register. They are 64-bits on all the other SBUS and PCI controllers anyways, so this was easy to cure. 2) The IMAP register has a different layout and some bits that we need to preserve, so use a read/modify/write when making changes to the IMAP register in generic code. 3) Flushing the entire IOMMU TLB is best done with a single write to a register on this PCI controller, add a iommu->iommu_flushinv for this. Still lacks MSI support, that will come later. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-05-03 00:31:36 +00:00
dt/sparc: Eliminate users of of_platform_{,un}register_driver Get rid of old users of of_platform_driver in arch/sparc. Most of_platform_driver users can be converted to use the platform_bus directly. Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2011-02-23 03:01:33 +00:00
static struct platform_driver fire_driver = {
of: Remove duplicate fields from of_platform_driver .name, .match_table and .owner are duplicated in both of_platform_driver and device_driver. This patch is a removes the extra copies from struct of_platform_driver and converts all users to the device_driver members. This patch is a pretty mechanical change. The usage model doesn't change and if any drivers have been missed, or if anything has been fixed up incorrectly, then it will fail with a compile time error, and the fixup will be trivial. This patch looks big and scary because it touches so many files, but it should be pretty safe. Signed-off-by: Grant Likely <grant.likely@secretlab.ca> Acked-by: Sean MacLennan <smaclennan@pikatech.com>
2010-04-13 23:13:02 +00:00
.driver = {
.name = DRIVER_NAME,
.of_match_table = fire_match,
},
sparc64: Convert FIRE PCI controller driver into a real driver. And now all the by-hand PCI controller probing junk in pci.c can die too. Signed-off-by: David S. Miller <davem@davemloft.net>
2008-08-30 10:12:38 +00:00
.probe = fire_probe,
};
static int __init fire_init(void)
{
dt/sparc: Eliminate users of of_platform_{,un}register_driver Get rid of old users of of_platform_driver in arch/sparc. Most of_platform_driver users can be converted to use the platform_bus directly. Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2011-02-23 03:01:33 +00:00
return platform_driver_register(&fire_driver);
[SPARC64]: SUN4U PCI-E controller support. Some minor refactoring in the generic code was necessary for this: 1) This controller requires 8-byte access to the interrupt map and clear register. They are 64-bits on all the other SBUS and PCI controllers anyways, so this was easy to cure. 2) The IMAP register has a different layout and some bits that we need to preserve, so use a read/modify/write when making changes to the IMAP register in generic code. 3) Flushing the entire IOMMU TLB is best done with a single write to a register on this PCI controller, add a iommu->iommu_flushinv for this. Still lacks MSI support, that will come later. Signed-off-by: David S. Miller <davem@davemloft.net>
2007-05-03 00:31:36 +00:00
}
sparc64: Convert FIRE PCI controller driver into a real driver. And now all the by-hand PCI controller probing junk in pci.c can die too. Signed-off-by: David S. Miller <davem@davemloft.net>
2008-08-30 10:12:38 +00:00
subsys_initcall(fire_init);
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