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linux/arch/arm/boot/dts/sun5i.dtsi

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ARM: sun5i: Add a DTSI common to A10s and A13 The A10s and the A13 are very similar SoCs, the only difference being the number of pins and the number of devices available (number of UARTs, EMAC only in the A10s, etc.), and the clocks and pinctrl functions obviously. Create a common DTSI that will be included by the A10s and A13 DTSI, that will add their SoC differences in there. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-30 15:30:48 +00:00
/*
* Copyright 2012-2015 Maxime Ripard
*
* Maxime Ripard <maxime.ripard@free-electrons.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include "skeleton.dtsi"
#include <dt-bindings/dma/sun4i-a10.h>
#include <dt-bindings/pinctrl/sun4i-a10.h>
/ {
interrupt-parent = <&intc>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a8";
reg = <0x0>;
clocks = <&cpu>;
};
};
clocks {
#address-cells = <1>;
#size-cells = <1>;
ranges;
/*
* This is a dummy clock, to be used as placeholder on
* other mux clocks when a specific parent clock is not
* yet implemented. It should be dropped when the driver
* is complete.
*/
dummy: dummy {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;
};
osc24M: clk@01c20050 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-osc-clk";
reg = <0x01c20050 0x4>;
clock-frequency = <24000000>;
clock-output-names = "osc24M";
};
osc32k: clk@0 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32768>;
clock-output-names = "osc32k";
};
pll1: clk@01c20000 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-pll1-clk";
reg = <0x01c20000 0x4>;
clocks = <&osc24M>;
clock-output-names = "pll1";
};
pll4: clk@01c20018 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-pll1-clk";
reg = <0x01c20018 0x4>;
clocks = <&osc24M>;
clock-output-names = "pll4";
};
pll5: clk@01c20020 {
#clock-cells = <1>;
compatible = "allwinner,sun4i-a10-pll5-clk";
reg = <0x01c20020 0x4>;
clocks = <&osc24M>;
clock-output-names = "pll5_ddr", "pll5_other";
};
pll6: clk@01c20028 {
#clock-cells = <1>;
compatible = "allwinner,sun4i-a10-pll6-clk";
reg = <0x01c20028 0x4>;
clocks = <&osc24M>;
clock-output-names = "pll6_sata", "pll6_other", "pll6";
};
/* dummy is 200M */
cpu: cpu@01c20054 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-cpu-clk";
reg = <0x01c20054 0x4>;
clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
clock-output-names = "cpu";
};
axi: axi@01c20054 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-axi-clk";
reg = <0x01c20054 0x4>;
clocks = <&cpu>;
clock-output-names = "axi";
};
ahb: ahb@01c20054 {
#clock-cells = <0>;
ARM: dts: sunxi: Update ahb clocks for sun5i and sun7i The clock driver now supports a muxable ahb clock. Update the dtsi with the proper compatible and add the new parent clocks. This also adds the new pll6/4 output for pll6 on sun7i-a20. The output is not used on sun4/5i. Also use assigned-clocks to reparent ahb to pll6. We want ahb to have a stable, non-changing clock rate. cpu/axi clock rate changes as a result of newly added cpufreq support. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-03-24 17:22:09 +00:00
compatible = "allwinner,sun5i-a13-ahb-clk";
ARM: sun5i: Add a DTSI common to A10s and A13 The A10s and the A13 are very similar SoCs, the only difference being the number of pins and the number of devices available (number of UARTs, EMAC only in the A10s, etc.), and the clocks and pinctrl functions obviously. Create a common DTSI that will be included by the A10s and A13 DTSI, that will add their SoC differences in there. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-30 15:30:48 +00:00
reg = <0x01c20054 0x4>;
ARM: dts: sunxi: Update ahb clocks for sun5i and sun7i The clock driver now supports a muxable ahb clock. Update the dtsi with the proper compatible and add the new parent clocks. This also adds the new pll6/4 output for pll6 on sun7i-a20. The output is not used on sun4/5i. Also use assigned-clocks to reparent ahb to pll6. We want ahb to have a stable, non-changing clock rate. cpu/axi clock rate changes as a result of newly added cpufreq support. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-03-24 17:22:09 +00:00
clocks = <&axi>, <&cpu>, <&pll6 1>;
ARM: sun5i: Add a DTSI common to A10s and A13 The A10s and the A13 are very similar SoCs, the only difference being the number of pins and the number of devices available (number of UARTs, EMAC only in the A10s, etc.), and the clocks and pinctrl functions obviously. Create a common DTSI that will be included by the A10s and A13 DTSI, that will add their SoC differences in there. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-30 15:30:48 +00:00
clock-output-names = "ahb";
ARM: dts: sunxi: Update ahb clocks for sun5i and sun7i The clock driver now supports a muxable ahb clock. Update the dtsi with the proper compatible and add the new parent clocks. This also adds the new pll6/4 output for pll6 on sun7i-a20. The output is not used on sun4/5i. Also use assigned-clocks to reparent ahb to pll6. We want ahb to have a stable, non-changing clock rate. cpu/axi clock rate changes as a result of newly added cpufreq support. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-03-24 17:22:09 +00:00
/*
* Use PLL6 as parent, instead of CPU/AXI
* which has rate changes due to cpufreq
*/
assigned-clocks = <&ahb>;
assigned-clock-parents = <&pll6 1>;
ARM: sun5i: Add a DTSI common to A10s and A13 The A10s and the A13 are very similar SoCs, the only difference being the number of pins and the number of devices available (number of UARTs, EMAC only in the A10s, etc.), and the clocks and pinctrl functions obviously. Create a common DTSI that will be included by the A10s and A13 DTSI, that will add their SoC differences in there. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-30 15:30:48 +00:00
};
apb0: apb0@01c20054 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-apb0-clk";
reg = <0x01c20054 0x4>;
clocks = <&ahb>;
clock-output-names = "apb0";
};
apb1: clk@01c20058 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-apb1-clk";
reg = <0x01c20058 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
clock-output-names = "apb1";
};
axi_gates: clk@01c2005c {
#clock-cells = <1>;
compatible = "allwinner,sun4i-a10-axi-gates-clk";
reg = <0x01c2005c 0x4>;
clocks = <&axi>;
clock-output-names = "axi_dram";
};
nand_clk: clk@01c20080 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-mod0-clk";
reg = <0x01c20080 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "nand";
};
ms_clk: clk@01c20084 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-mod0-clk";
reg = <0x01c20084 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "ms";
};
mmc0_clk: clk@01c20088 {
#clock-cells = <1>;
compatible = "allwinner,sun4i-a10-mmc-clk";
reg = <0x01c20088 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "mmc0",
"mmc0_output",
"mmc0_sample";
};
mmc1_clk: clk@01c2008c {
#clock-cells = <1>;
compatible = "allwinner,sun4i-a10-mmc-clk";
reg = <0x01c2008c 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "mmc1",
"mmc1_output",
"mmc1_sample";
};
mmc2_clk: clk@01c20090 {
#clock-cells = <1>;
compatible = "allwinner,sun4i-a10-mmc-clk";
reg = <0x01c20090 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "mmc2",
"mmc2_output",
"mmc2_sample";
};
ts_clk: clk@01c20098 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-mod0-clk";
reg = <0x01c20098 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "ts";
};
ss_clk: clk@01c2009c {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-mod0-clk";
reg = <0x01c2009c 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "ss";
};
spi0_clk: clk@01c200a0 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-mod0-clk";
reg = <0x01c200a0 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "spi0";
};
spi1_clk: clk@01c200a4 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-mod0-clk";
reg = <0x01c200a4 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "spi1";
};
spi2_clk: clk@01c200a8 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-mod0-clk";
reg = <0x01c200a8 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "spi2";
};
ir0_clk: clk@01c200b0 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-mod0-clk";
reg = <0x01c200b0 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "ir0";
};
usb_clk: clk@01c200cc {
#clock-cells = <1>;
ARM: sunxi: dt: Fix whitespace errors A few lines (probably copy pasted) have an indentation mixing tabs and spaces that triggers a checkpatch warning. Fix those, and while we're at it, fix the space-indented sections. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-05-03 09:54:35 +00:00
#reset-cells = <1>;
ARM: sun5i: Add a DTSI common to A10s and A13 The A10s and the A13 are very similar SoCs, the only difference being the number of pins and the number of devices available (number of UARTs, EMAC only in the A10s, etc.), and the clocks and pinctrl functions obviously. Create a common DTSI that will be included by the A10s and A13 DTSI, that will add their SoC differences in there. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-30 15:30:48 +00:00
compatible = "allwinner,sun5i-a13-usb-clk";
reg = <0x01c200cc 0x4>;
clocks = <&pll6 1>;
clock-output-names = "usb_ohci0", "usb_phy";
};
mbus_clk: clk@01c2015c {
#clock-cells = <0>;
compatible = "allwinner,sun5i-a13-mbus-clk";
reg = <0x01c2015c 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
clock-output-names = "mbus";
};
};
soc@01c00000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
ARM: dts: sun5i: Add A10s and A13 SRAM and SRAM controller The A10s and A13 have a few SRAM that can be mapped either to a device or to the CPU, with the mapping being controlled by a SRAM controller. Add the SRAM controller, the SRAM that it drives and the section that can be used by the various devices. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Hans de Goede <hdegoede@redhat.com> Tested-by: Hans de Goede <hdegoede@redhat.com>
2015-03-26 14:53:44 +00:00
sram-controller@01c00000 {
compatible = "allwinner,sun4i-a10-sram-controller";
reg = <0x01c00000 0x30>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
sram_a: sram@00000000 {
compatible = "mmio-sram";
reg = <0x00000000 0xc000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x00000000 0xc000>;
};
sram_d: sram@00010000 {
compatible = "mmio-sram";
reg = <0x00010000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x00010000 0x1000>;
otg_sram: sram-section@0000 {
compatible = "allwinner,sun4i-a10-sram-d";
reg = <0x0000 0x1000>;
status = "disabled";
};
};
};
ARM: sun5i: Add a DTSI common to A10s and A13 The A10s and the A13 are very similar SoCs, the only difference being the number of pins and the number of devices available (number of UARTs, EMAC only in the A10s, etc.), and the clocks and pinctrl functions obviously. Create a common DTSI that will be included by the A10s and A13 DTSI, that will add their SoC differences in there. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-30 15:30:48 +00:00
dma: dma-controller@01c02000 {
compatible = "allwinner,sun4i-a10-dma";
reg = <0x01c02000 0x1000>;
interrupts = <27>;
clocks = <&ahb_gates 6>;
#dma-cells = <2>;
};
spi0: spi@01c05000 {
compatible = "allwinner,sun4i-a10-spi";
reg = <0x01c05000 0x1000>;
interrupts = <10>;
clocks = <&ahb_gates 20>, <&spi0_clk>;
clock-names = "ahb", "mod";
dmas = <&dma SUN4I_DMA_DEDICATED 27>,
<&dma SUN4I_DMA_DEDICATED 26>;
dma-names = "rx", "tx";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
spi1: spi@01c06000 {
compatible = "allwinner,sun4i-a10-spi";
reg = <0x01c06000 0x1000>;
interrupts = <11>;
clocks = <&ahb_gates 21>, <&spi1_clk>;
clock-names = "ahb", "mod";
dmas = <&dma SUN4I_DMA_DEDICATED 9>,
<&dma SUN4I_DMA_DEDICATED 8>;
dma-names = "rx", "tx";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
mmc0: mmc@01c0f000 {
compatible = "allwinner,sun5i-a13-mmc";
reg = <0x01c0f000 0x1000>;
clocks = <&ahb_gates 8>,
<&mmc0_clk 0>,
<&mmc0_clk 1>,
<&mmc0_clk 2>;
clock-names = "ahb",
"mmc",
"output",
"sample";
interrupts = <32>;
status = "disabled";
ARM: dts: sunxi: Add address- and size-cells properties to the mmc ctrl nodes Sometimes we need to specify non-probably information for sdio devices in the devicetree, this is done through child nodes addressed by the reg property, whereby the reg property refers to the sdio function number, see; Documentation/devicetree/bindings/mmc/mmc.txt This commit adds the necessary address- and size-cells properties to the mmc controller nodes in the dtsi files, so that dts files needing such a child node do not need to specify these themselves. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-03-10 15:27:09 +00:00
#address-cells = <1>;
#size-cells = <0>;
ARM: sun5i: Add a DTSI common to A10s and A13 The A10s and the A13 are very similar SoCs, the only difference being the number of pins and the number of devices available (number of UARTs, EMAC only in the A10s, etc.), and the clocks and pinctrl functions obviously. Create a common DTSI that will be included by the A10s and A13 DTSI, that will add their SoC differences in there. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-30 15:30:48 +00:00
};
mmc1: mmc@01c10000 {
compatible = "allwinner,sun5i-a13-mmc";
reg = <0x01c10000 0x1000>;
clocks = <&ahb_gates 9>,
<&mmc1_clk 0>,
<&mmc1_clk 1>,
<&mmc1_clk 2>;
clock-names = "ahb",
"mmc",
"output",
"sample";
interrupts = <33>;
status = "disabled";
ARM: dts: sunxi: Add address- and size-cells properties to the mmc ctrl nodes Sometimes we need to specify non-probably information for sdio devices in the devicetree, this is done through child nodes addressed by the reg property, whereby the reg property refers to the sdio function number, see; Documentation/devicetree/bindings/mmc/mmc.txt This commit adds the necessary address- and size-cells properties to the mmc controller nodes in the dtsi files, so that dts files needing such a child node do not need to specify these themselves. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-03-10 15:27:09 +00:00
#address-cells = <1>;
#size-cells = <0>;
ARM: sun5i: Add a DTSI common to A10s and A13 The A10s and the A13 are very similar SoCs, the only difference being the number of pins and the number of devices available (number of UARTs, EMAC only in the A10s, etc.), and the clocks and pinctrl functions obviously. Create a common DTSI that will be included by the A10s and A13 DTSI, that will add their SoC differences in there. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-30 15:30:48 +00:00
};
mmc2: mmc@01c11000 {
compatible = "allwinner,sun5i-a13-mmc";
reg = <0x01c11000 0x1000>;
clocks = <&ahb_gates 10>,
<&mmc2_clk 0>,
<&mmc2_clk 1>,
<&mmc2_clk 2>;
clock-names = "ahb",
"mmc",
"output",
"sample";
interrupts = <34>;
status = "disabled";
ARM: dts: sunxi: Add address- and size-cells properties to the mmc ctrl nodes Sometimes we need to specify non-probably information for sdio devices in the devicetree, this is done through child nodes addressed by the reg property, whereby the reg property refers to the sdio function number, see; Documentation/devicetree/bindings/mmc/mmc.txt This commit adds the necessary address- and size-cells properties to the mmc controller nodes in the dtsi files, so that dts files needing such a child node do not need to specify these themselves. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-03-10 15:27:09 +00:00
#address-cells = <1>;
#size-cells = <0>;
ARM: sun5i: Add a DTSI common to A10s and A13 The A10s and the A13 are very similar SoCs, the only difference being the number of pins and the number of devices available (number of UARTs, EMAC only in the A10s, etc.), and the clocks and pinctrl functions obviously. Create a common DTSI that will be included by the A10s and A13 DTSI, that will add their SoC differences in there. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-30 15:30:48 +00:00
};
usbphy: phy@01c13400 {
#phy-cells = <1>;
compatible = "allwinner,sun5i-a13-usb-phy";
reg = <0x01c13400 0x10 0x01c14800 0x4>;
reg-names = "phy_ctrl", "pmu1";
clocks = <&usb_clk 8>;
clock-names = "usb_phy";
resets = <&usb_clk 0>, <&usb_clk 1>;
reset-names = "usb0_reset", "usb1_reset";
status = "disabled";
};
ehci0: usb@01c14000 {
ARM: dts: sun5i: Stop using different compatibles for ehci/ohci on a13 vs a10s The A13 and the A10s use the same die (this has been confirmed by Allwinner), as such there is no need to differentiate between the ehci/ohci parts of both, the only reasons there were different allwinner,sun5i-a*-foo compatible between these 2 parts is costemetically and because we could when we still had 2 completely different dtsi files. The allwinner,sun5i-a*-foo compatible strings are not used for binding at all, the actual driver binds to the generic-?hci compatible, so we can safely remove this cosmetical difference and simplify the dtsi files. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-03-07 19:01:19 +00:00
compatible = "allwinner,sun5i-a13-ehci", "generic-ehci";
ARM: sun5i: Add a DTSI common to A10s and A13 The A10s and the A13 are very similar SoCs, the only difference being the number of pins and the number of devices available (number of UARTs, EMAC only in the A10s, etc.), and the clocks and pinctrl functions obviously. Create a common DTSI that will be included by the A10s and A13 DTSI, that will add their SoC differences in there. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-30 15:30:48 +00:00
reg = <0x01c14000 0x100>;
interrupts = <39>;
clocks = <&ahb_gates 1>;
phys = <&usbphy 1>;
phy-names = "usb";
status = "disabled";
};
ohci0: usb@01c14400 {
ARM: dts: sun5i: Stop using different compatibles for ehci/ohci on a13 vs a10s The A13 and the A10s use the same die (this has been confirmed by Allwinner), as such there is no need to differentiate between the ehci/ohci parts of both, the only reasons there were different allwinner,sun5i-a*-foo compatible between these 2 parts is costemetically and because we could when we still had 2 completely different dtsi files. The allwinner,sun5i-a*-foo compatible strings are not used for binding at all, the actual driver binds to the generic-?hci compatible, so we can safely remove this cosmetical difference and simplify the dtsi files. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-03-07 19:01:19 +00:00
compatible = "allwinner,sun5i-a13-ohci", "generic-ohci";
ARM: sun5i: Add a DTSI common to A10s and A13 The A10s and the A13 are very similar SoCs, the only difference being the number of pins and the number of devices available (number of UARTs, EMAC only in the A10s, etc.), and the clocks and pinctrl functions obviously. Create a common DTSI that will be included by the A10s and A13 DTSI, that will add their SoC differences in there. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-30 15:30:48 +00:00
reg = <0x01c14400 0x100>;
interrupts = <40>;
clocks = <&usb_clk 6>, <&ahb_gates 2>;
phys = <&usbphy 1>;
phy-names = "usb";
status = "disabled";
};
spi2: spi@01c17000 {
compatible = "allwinner,sun4i-a10-spi";
reg = <0x01c17000 0x1000>;
interrupts = <12>;
clocks = <&ahb_gates 22>, <&spi2_clk>;
clock-names = "ahb", "mod";
dmas = <&dma SUN4I_DMA_DEDICATED 29>,
<&dma SUN4I_DMA_DEDICATED 28>;
dma-names = "rx", "tx";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
intc: interrupt-controller@01c20400 {
compatible = "allwinner,sun4i-a10-ic";
reg = <0x01c20400 0x400>;
interrupt-controller;
#interrupt-cells = <1>;
};
pio: pinctrl@01c20800 {
reg = <0x01c20800 0x400>;
interrupts = <28>;
clocks = <&apb0_gates 5>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
#size-cells = <0>;
#gpio-cells = <3>;
ARM: sun5i: a13: Move to the common sun5i DTSI Now that we have a common DTSI for the sun5i family, move the A13 to use it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-30 15:31:19 +00:00
i2c0_pins_a: i2c0@0 {
allwinner,pins = "PB0", "PB1";
allwinner,function = "i2c0";
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
i2c1_pins_a: i2c1@0 {
allwinner,pins = "PB15", "PB16";
allwinner,function = "i2c1";
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
i2c2_pins_a: i2c2@0 {
allwinner,pins = "PB17", "PB18";
allwinner,function = "i2c2";
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
mmc0_pins_a: mmc0@0 {
ARM: sunxi: DT: Fix lines over 80 characters A few lines in our DTSIs are over the 80 characters limit, making checkpatch complain about that. If possible (and relevant), wrap these lines to 80 characters. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-05-03 09:53:07 +00:00
allwinner,pins = "PF0", "PF1", "PF2", "PF3",
"PF4", "PF5";
ARM: sun5i: a13: Move to the common sun5i DTSI Now that we have a common DTSI for the sun5i family, move the A13 to use it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-30 15:31:19 +00:00
allwinner,function = "mmc0";
allwinner,drive = <SUN4I_PINCTRL_30_MA>;
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
ARM: dts: sun5i: Add mmc2 pinmux settings Add A13 mmc2 pinmux settings, note these are for a 8bit bus. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-03-07 19:01:20 +00:00
mmc2_pins_a: mmc2@0 {
allwinner,pins = "PC6", "PC7", "PC8", "PC9",
"PC10", "PC11", "PC12", "PC13",
"PC14", "PC15";
allwinner,function = "mmc2";
allwinner,drive = <SUN4I_PINCTRL_30_MA>;
allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
};
ARM: sun5i: Add a DTSI common to A10s and A13 The A10s and the A13 are very similar SoCs, the only difference being the number of pins and the number of devices available (number of UARTs, EMAC only in the A10s, etc.), and the clocks and pinctrl functions obviously. Create a common DTSI that will be included by the A10s and A13 DTSI, that will add their SoC differences in there. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-30 15:30:48 +00:00
};
timer@01c20c00 {
compatible = "allwinner,sun4i-a10-timer";
reg = <0x01c20c00 0x90>;
interrupts = <22>;
clocks = <&osc24M>;
};
wdt: watchdog@01c20c90 {
compatible = "allwinner,sun4i-a10-wdt";
reg = <0x01c20c90 0x10>;
};
lradc: lradc@01c22800 {
compatible = "allwinner,sun4i-a10-lradc-keys";
reg = <0x01c22800 0x100>;
interrupts = <31>;
status = "disabled";
};
sid: eeprom@01c23800 {
compatible = "allwinner,sun4i-a10-sid";
reg = <0x01c23800 0x10>;
};
rtp: rtp@01c25000 {
ARM: dts: sunxi: Adjust touchscreen compatible for sun5i and later The touchscreen controller in the A13 and later has a different temperature curve than the one in the original A10, change the compatible for the A13 and later so that the kernel will use the correct curve. Reported-by: Tong Zhang <lovewilliam@gmail.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-03-08 20:53:42 +00:00
compatible = "allwinner,sun5i-a13-ts";
ARM: sun5i: Add a DTSI common to A10s and A13 The A10s and the A13 are very similar SoCs, the only difference being the number of pins and the number of devices available (number of UARTs, EMAC only in the A10s, etc.), and the clocks and pinctrl functions obviously. Create a common DTSI that will be included by the A10s and A13 DTSI, that will add their SoC differences in there. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-30 15:30:48 +00:00
reg = <0x01c25000 0x100>;
interrupts = <29>;
#thermal-sensor-cells = <0>;
};
uart1: serial@01c28400 {
compatible = "snps,dw-apb-uart";
reg = <0x01c28400 0x400>;
interrupts = <2>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&apb1_gates 17>;
status = "disabled";
};
uart3: serial@01c28c00 {
compatible = "snps,dw-apb-uart";
reg = <0x01c28c00 0x400>;
interrupts = <4>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&apb1_gates 19>;
status = "disabled";
};
i2c0: i2c@01c2ac00 {
compatible = "allwinner,sun4i-a10-i2c";
reg = <0x01c2ac00 0x400>;
interrupts = <7>;
clocks = <&apb1_gates 0>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
i2c1: i2c@01c2b000 {
compatible = "allwinner,sun4i-a10-i2c";
reg = <0x01c2b000 0x400>;
interrupts = <8>;
clocks = <&apb1_gates 1>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
i2c2: i2c@01c2b400 {
compatible = "allwinner,sun4i-a10-i2c";
reg = <0x01c2b400 0x400>;
interrupts = <9>;
clocks = <&apb1_gates 2>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
timer@01c60000 {
compatible = "allwinner,sun5i-a13-hstimer";
reg = <0x01c60000 0x1000>;
interrupts = <82>, <83>;
clocks = <&ahb_gates 28>;
};
};
};
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