2013-03-27 15:49:34 +00:00
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/*
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* Device Tree Source for the r8a7790 SoC
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*
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2015-02-19 15:42:55 +00:00
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* Copyright (C) 2015 Renesas Electronics Corporation
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2014-02-19 23:20:43 +00:00
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* Copyright (C) 2013-2014 Renesas Solutions Corp.
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* Copyright (C) 2014 Cogent Embedded Inc.
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2013-03-27 15:49:34 +00:00
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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2013-12-11 14:05:14 +00:00
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#include <dt-bindings/clock/r8a7790-clock.h>
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2013-11-19 02:18:25 +00:00
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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2013-03-27 15:49:34 +00:00
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/ {
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compatible = "renesas,r8a7790";
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interrupt-parent = <&gic>;
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2013-03-29 07:49:17 +00:00
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#address-cells = <2>;
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#size-cells = <2>;
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2013-03-27 15:49:34 +00:00
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2014-02-16 09:40:58 +00:00
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aliases {
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i2c0 = &i2c0;
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i2c1 = &i2c1;
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i2c2 = &i2c2;
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i2c3 = &i2c3;
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2014-03-25 18:56:29 +00:00
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i2c4 = &iic0;
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i2c5 = &iic1;
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i2c6 = &iic2;
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i2c7 = &iic3;
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2014-02-25 10:30:13 +00:00
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spi0 = &qspi;
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2014-02-25 10:30:15 +00:00
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spi1 = &msiof0;
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spi2 = &msiof1;
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spi3 = &msiof2;
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spi4 = &msiof3;
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2014-08-12 20:16:18 +00:00
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vin0 = &vin0;
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vin1 = &vin1;
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vin2 = &vin2;
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vin3 = &vin3;
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2014-02-16 09:40:58 +00:00
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};
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2013-03-27 15:49:34 +00:00
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0>;
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clock-frequency = <1300000000>;
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2014-06-03 12:02:24 +00:00
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voltage-tolerance = <1>; /* 1% */
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clocks = <&cpg_clocks R8A7790_CLK_Z>;
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clock-latency = <300000>; /* 300 us */
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/* kHz - uV - OPPs unknown yet */
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operating-points = <1400000 1000000>,
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<1225000 1000000>,
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<1050000 1000000>,
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< 875000 1000000>,
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< 700000 1000000>,
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< 350000 1000000>;
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2013-03-27 15:49:34 +00:00
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};
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2013-08-28 23:22:17 +00:00
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <1>;
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clock-frequency = <1300000000>;
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};
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cpu2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <2>;
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clock-frequency = <1300000000>;
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};
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cpu3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <3>;
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clock-frequency = <1300000000>;
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};
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2013-09-14 15:28:58 +00:00
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cpu4: cpu@4 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x100>;
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clock-frequency = <780000000>;
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};
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cpu5: cpu@5 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x101>;
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clock-frequency = <780000000>;
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};
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cpu6: cpu@6 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x102>;
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clock-frequency = <780000000>;
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};
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cpu7: cpu@7 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x103>;
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clock-frequency = <780000000>;
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};
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2013-03-27 15:49:34 +00:00
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};
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gic: interrupt-controller@f1001000 {
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compatible = "arm,cortex-a15-gic";
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#interrupt-cells = <3>;
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#address-cells = <0>;
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interrupt-controller;
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2013-03-29 07:49:17 +00:00
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reg = <0 0xf1001000 0 0x1000>,
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<0 0xf1002000 0 0x1000>,
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<0 0xf1004000 0 0x2000>,
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<0 0xf1006000 0 0x2000>;
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2013-11-19 02:18:25 +00:00
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interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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2013-03-27 15:49:34 +00:00
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};
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2013-11-21 05:19:29 +00:00
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gpio0: gpio@e6050000 {
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2013-05-10 13:51:14 +00:00
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compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
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2013-11-21 05:19:29 +00:00
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reg = <0 0xe6050000 0 0x50>;
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2013-11-19 02:18:25 +00:00
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interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
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2013-05-10 13:51:14 +00:00
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 0 32>;
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#interrupt-cells = <2>;
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interrupt-controller;
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2014-04-23 08:25:27 +00:00
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clocks = <&mstp9_clks R8A7790_CLK_GPIO0>;
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2013-05-10 13:51:14 +00:00
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};
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2013-11-21 05:19:29 +00:00
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gpio1: gpio@e6051000 {
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2013-05-10 13:51:14 +00:00
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compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
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2013-11-21 05:19:29 +00:00
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reg = <0 0xe6051000 0 0x50>;
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2013-11-19 02:18:25 +00:00
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interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
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2013-05-10 13:51:14 +00:00
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 32 32>;
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#interrupt-cells = <2>;
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interrupt-controller;
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2014-04-23 08:25:27 +00:00
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clocks = <&mstp9_clks R8A7790_CLK_GPIO1>;
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2013-05-10 13:51:14 +00:00
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};
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2013-11-21 05:19:29 +00:00
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gpio2: gpio@e6052000 {
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2013-05-10 13:51:14 +00:00
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compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
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2013-11-21 05:19:29 +00:00
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reg = <0 0xe6052000 0 0x50>;
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2013-11-19 02:18:25 +00:00
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interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
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2013-05-10 13:51:14 +00:00
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 64 32>;
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#interrupt-cells = <2>;
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interrupt-controller;
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2014-04-23 08:25:27 +00:00
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clocks = <&mstp9_clks R8A7790_CLK_GPIO2>;
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2013-05-10 13:51:14 +00:00
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};
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2013-11-21 05:19:29 +00:00
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gpio3: gpio@e6053000 {
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2013-05-10 13:51:14 +00:00
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compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
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2013-11-21 05:19:29 +00:00
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reg = <0 0xe6053000 0 0x50>;
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2013-11-19 02:18:25 +00:00
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interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
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2013-05-10 13:51:14 +00:00
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 96 32>;
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#interrupt-cells = <2>;
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interrupt-controller;
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2014-04-23 08:25:27 +00:00
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clocks = <&mstp9_clks R8A7790_CLK_GPIO3>;
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2013-05-10 13:51:14 +00:00
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};
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2013-11-21 05:19:29 +00:00
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gpio4: gpio@e6054000 {
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2013-05-10 13:51:14 +00:00
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compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
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2013-11-21 05:19:29 +00:00
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reg = <0 0xe6054000 0 0x50>;
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2013-11-19 02:18:25 +00:00
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interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
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2013-05-10 13:51:14 +00:00
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 128 32>;
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#interrupt-cells = <2>;
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interrupt-controller;
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2014-04-23 08:25:27 +00:00
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clocks = <&mstp9_clks R8A7790_CLK_GPIO4>;
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2013-05-10 13:51:14 +00:00
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};
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2013-11-21 05:19:29 +00:00
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gpio5: gpio@e6055000 {
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2013-05-10 13:51:14 +00:00
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compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
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2013-11-21 05:19:29 +00:00
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reg = <0 0xe6055000 0 0x50>;
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2013-11-19 02:18:25 +00:00
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interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
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2013-05-10 13:51:14 +00:00
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 160 32>;
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#interrupt-cells = <2>;
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interrupt-controller;
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2014-04-23 08:25:27 +00:00
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clocks = <&mstp9_clks R8A7790_CLK_GPIO5>;
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2013-05-10 13:51:14 +00:00
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};
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2013-11-20 07:59:30 +00:00
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thermal@e61f0000 {
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compatible = "renesas,thermal-r8a7790", "renesas,rcar-thermal";
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reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
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interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
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2014-01-07 18:57:14 +00:00
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clocks = <&mstp5_clks R8A7790_CLK_THERMAL>;
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2013-11-20 07:59:30 +00:00
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};
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2013-03-27 15:49:34 +00:00
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timer {
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compatible = "arm,armv7-timer";
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2013-11-19 02:18:25 +00:00
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interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<1 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<1 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
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2013-03-27 15:49:34 +00:00
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};
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2013-03-27 15:49:54 +00:00
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2014-07-09 13:12:37 +00:00
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cmt0: timer@ffca0000 {
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2014-09-08 00:27:45 +00:00
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compatible = "renesas,cmt-48-r8a7790", "renesas,cmt-48-gen2";
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2014-07-09 13:12:37 +00:00
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reg = <0 0xffca0000 0 0x1004>;
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interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>,
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<0 143 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp1_clks R8A7790_CLK_CMT0>;
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clock-names = "fck";
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renesas,channels-mask = <0x60>;
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status = "disabled";
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};
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cmt1: timer@e6130000 {
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2014-09-08 00:27:45 +00:00
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compatible = "renesas,cmt-48-r8a7790", "renesas,cmt-48-gen2";
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2014-07-09 13:12:37 +00:00
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reg = <0 0xe6130000 0 0x1004>;
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interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>,
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<0 121 IRQ_TYPE_LEVEL_HIGH>,
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<0 122 IRQ_TYPE_LEVEL_HIGH>,
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<0 123 IRQ_TYPE_LEVEL_HIGH>,
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<0 124 IRQ_TYPE_LEVEL_HIGH>,
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<0 125 IRQ_TYPE_LEVEL_HIGH>,
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<0 126 IRQ_TYPE_LEVEL_HIGH>,
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<0 127 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp3_clks R8A7790_CLK_CMT1>;
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clock-names = "fck";
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renesas,channels-mask = <0xff>;
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status = "disabled";
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};
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2013-03-27 15:49:54 +00:00
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irqc0: interrupt-controller@e61c0000 {
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2013-11-20 00:07:40 +00:00
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compatible = "renesas,irqc-r8a7790", "renesas,irqc";
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2013-03-27 15:49:54 +00:00
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#interrupt-cells = <2>;
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interrupt-controller;
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2013-03-29 07:49:17 +00:00
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reg = <0 0xe61c0000 0 0x200>;
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2013-11-19 02:18:25 +00:00
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interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
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<0 1 IRQ_TYPE_LEVEL_HIGH>,
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<0 2 IRQ_TYPE_LEVEL_HIGH>,
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<0 3 IRQ_TYPE_LEVEL_HIGH>;
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2015-03-18 18:55:59 +00:00
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clocks = <&mstp4_clks R8A7790_CLK_IRQC>;
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2013-03-27 15:49:54 +00:00
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};
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2013-07-08 15:54:46 +00:00
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2014-07-18 23:50:24 +00:00
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dmac0: dma-controller@e6700000 {
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compatible = "renesas,rcar-dmac";
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reg = <0 0xe6700000 0 0x20000>;
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interrupts = <0 197 IRQ_TYPE_LEVEL_HIGH
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0 200 IRQ_TYPE_LEVEL_HIGH
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0 201 IRQ_TYPE_LEVEL_HIGH
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0 202 IRQ_TYPE_LEVEL_HIGH
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0 203 IRQ_TYPE_LEVEL_HIGH
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0 204 IRQ_TYPE_LEVEL_HIGH
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0 205 IRQ_TYPE_LEVEL_HIGH
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0 206 IRQ_TYPE_LEVEL_HIGH
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0 207 IRQ_TYPE_LEVEL_HIGH
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|
0 208 IRQ_TYPE_LEVEL_HIGH
|
|
|
|
|
0 209 IRQ_TYPE_LEVEL_HIGH
|
|
|
|
|
0 210 IRQ_TYPE_LEVEL_HIGH
|
|
|
|
|
0 211 IRQ_TYPE_LEVEL_HIGH
|
|
|
|
|
0 212 IRQ_TYPE_LEVEL_HIGH
|
|
|
|
|
0 213 IRQ_TYPE_LEVEL_HIGH
|
|
|
|
|
0 214 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
interrupt-names = "error",
|
|
|
|
|
"ch0", "ch1", "ch2", "ch3",
|
|
|
|
|
"ch4", "ch5", "ch6", "ch7",
|
|
|
|
|
"ch8", "ch9", "ch10", "ch11",
|
|
|
|
|
"ch12", "ch13", "ch14";
|
|
|
|
|
clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC0>;
|
|
|
|
|
clock-names = "fck";
|
|
|
|
|
#dma-cells = <1>;
|
|
|
|
|
dma-channels = <15>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
dmac1: dma-controller@e6720000 {
|
|
|
|
|
compatible = "renesas,rcar-dmac";
|
|
|
|
|
reg = <0 0xe6720000 0 0x20000>;
|
|
|
|
|
interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH
|
|
|
|
|
0 216 IRQ_TYPE_LEVEL_HIGH
|
|
|
|
|
0 217 IRQ_TYPE_LEVEL_HIGH
|
|
|
|
|
0 218 IRQ_TYPE_LEVEL_HIGH
|
|
|
|
|
0 219 IRQ_TYPE_LEVEL_HIGH
|
|
|
|
|
0 308 IRQ_TYPE_LEVEL_HIGH
|
|
|
|
|
0 309 IRQ_TYPE_LEVEL_HIGH
|
|
|
|
|
0 310 IRQ_TYPE_LEVEL_HIGH
|
|
|
|
|
0 311 IRQ_TYPE_LEVEL_HIGH
|
|
|
|
|
0 312 IRQ_TYPE_LEVEL_HIGH
|
|
|
|
|
0 313 IRQ_TYPE_LEVEL_HIGH
|
|
|
|
|
0 314 IRQ_TYPE_LEVEL_HIGH
|
|
|
|
|
0 315 IRQ_TYPE_LEVEL_HIGH
|
|
|
|
|
0 316 IRQ_TYPE_LEVEL_HIGH
|
|
|
|
|
0 317 IRQ_TYPE_LEVEL_HIGH
|
|
|
|
|
0 318 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
interrupt-names = "error",
|
|
|
|
|
"ch0", "ch1", "ch2", "ch3",
|
|
|
|
|
"ch4", "ch5", "ch6", "ch7",
|
|
|
|
|
"ch8", "ch9", "ch10", "ch11",
|
|
|
|
|
"ch12", "ch13", "ch14";
|
|
|
|
|
clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC1>;
|
|
|
|
|
clock-names = "fck";
|
|
|
|
|
#dma-cells = <1>;
|
|
|
|
|
dma-channels = <15>;
|
|
|
|
|
};
|
2014-11-04 01:44:51 +00:00
|
|
|
|
|
|
|
|
audma0: dma-controller@ec700000 {
|
|
|
|
|
compatible = "renesas,rcar-dmac";
|
|
|
|
|
reg = <0 0xec700000 0 0x10000>;
|
|
|
|
|
interrupts = <0 346 IRQ_TYPE_LEVEL_HIGH
|
|
|
|
|
0 320 IRQ_TYPE_LEVEL_HIGH
|
|
|
|
|
0 321 IRQ_TYPE_LEVEL_HIGH
|
|
|
|
|
0 322 IRQ_TYPE_LEVEL_HIGH
|
|
|
|
|
0 323 IRQ_TYPE_LEVEL_HIGH
|
|
|
|
|
0 324 IRQ_TYPE_LEVEL_HIGH
|
|
|
|
|
0 325 IRQ_TYPE_LEVEL_HIGH
|
|
|
|
|
0 326 IRQ_TYPE_LEVEL_HIGH
|
|
|
|
|
0 327 IRQ_TYPE_LEVEL_HIGH
|
|
|
|
|
0 328 IRQ_TYPE_LEVEL_HIGH
|
|
|
|
|
0 329 IRQ_TYPE_LEVEL_HIGH
|
|
|
|
|
0 330 IRQ_TYPE_LEVEL_HIGH
|
|
|
|
|
0 331 IRQ_TYPE_LEVEL_HIGH
|
|
|
|
|
0 332 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
interrupt-names = "error",
|
|
|
|
|
"ch0", "ch1", "ch2", "ch3",
|
|
|
|
|
"ch4", "ch5", "ch6", "ch7",
|
|
|
|
|
"ch8", "ch9", "ch10", "ch11",
|
|
|
|
|
"ch12";
|
|
|
|
|
clocks = <&mstp5_clks R8A7790_CLK_AUDIO_DMAC0>;
|
|
|
|
|
clock-names = "fck";
|
|
|
|
|
#dma-cells = <1>;
|
|
|
|
|
dma-channels = <13>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
audma1: dma-controller@ec720000 {
|
|
|
|
|
compatible = "renesas,rcar-dmac";
|
|
|
|
|
reg = <0 0xec720000 0 0x10000>;
|
|
|
|
|
interrupts = <0 347 IRQ_TYPE_LEVEL_HIGH
|
|
|
|
|
0 333 IRQ_TYPE_LEVEL_HIGH
|
|
|
|
|
0 334 IRQ_TYPE_LEVEL_HIGH
|
|
|
|
|
0 335 IRQ_TYPE_LEVEL_HIGH
|
|
|
|
|
0 336 IRQ_TYPE_LEVEL_HIGH
|
|
|
|
|
0 337 IRQ_TYPE_LEVEL_HIGH
|
|
|
|
|
0 338 IRQ_TYPE_LEVEL_HIGH
|
|
|
|
|
0 339 IRQ_TYPE_LEVEL_HIGH
|
|
|
|
|
0 340 IRQ_TYPE_LEVEL_HIGH
|
|
|
|
|
0 341 IRQ_TYPE_LEVEL_HIGH
|
|
|
|
|
0 342 IRQ_TYPE_LEVEL_HIGH
|
|
|
|
|
0 343 IRQ_TYPE_LEVEL_HIGH
|
|
|
|
|
0 344 IRQ_TYPE_LEVEL_HIGH
|
|
|
|
|
0 345 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
interrupt-names = "error",
|
|
|
|
|
"ch0", "ch1", "ch2", "ch3",
|
|
|
|
|
"ch4", "ch5", "ch6", "ch7",
|
|
|
|
|
"ch8", "ch9", "ch10", "ch11",
|
|
|
|
|
"ch12";
|
|
|
|
|
clocks = <&mstp5_clks R8A7790_CLK_AUDIO_DMAC1>;
|
|
|
|
|
clock-names = "fck";
|
|
|
|
|
#dma-cells = <1>;
|
|
|
|
|
dma-channels = <13>;
|
|
|
|
|
};
|
|
|
|
|
|
2013-09-26 17:20:58 +00:00
|
|
|
i2c0: i2c@e6508000 {
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
compatible = "renesas,i2c-r8a7790";
|
|
|
|
|
reg = <0 0xe6508000 0 0x40>;
|
2013-11-19 02:18:25 +00:00
|
|
|
interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>;
|
2014-01-20 11:44:21 +00:00
|
|
|
clocks = <&mstp9_clks R8A7790_CLK_I2C0>;
|
2013-09-26 17:20:58 +00:00
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
i2c1: i2c@e6518000 {
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
compatible = "renesas,i2c-r8a7790";
|
|
|
|
|
reg = <0 0xe6518000 0 0x40>;
|
2013-11-19 02:18:25 +00:00
|
|
|
interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>;
|
2014-01-20 11:44:21 +00:00
|
|
|
clocks = <&mstp9_clks R8A7790_CLK_I2C1>;
|
2013-09-26 17:20:58 +00:00
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
i2c2: i2c@e6530000 {
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
compatible = "renesas,i2c-r8a7790";
|
|
|
|
|
reg = <0 0xe6530000 0 0x40>;
|
2013-11-19 02:18:25 +00:00
|
|
|
interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>;
|
2014-01-20 11:44:21 +00:00
|
|
|
clocks = <&mstp9_clks R8A7790_CLK_I2C2>;
|
2013-09-26 17:20:58 +00:00
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
i2c3: i2c@e6540000 {
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
compatible = "renesas,i2c-r8a7790";
|
|
|
|
|
reg = <0 0xe6540000 0 0x40>;
|
2013-11-19 02:18:25 +00:00
|
|
|
interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>;
|
2014-01-20 11:44:21 +00:00
|
|
|
clocks = <&mstp9_clks R8A7790_CLK_I2C3>;
|
2013-09-26 17:20:58 +00:00
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
2014-03-25 18:56:29 +00:00
|
|
|
iic0: i2c@e6500000 {
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
|
|
|
|
|
reg = <0 0xe6500000 0 0x425>;
|
|
|
|
|
interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clocks = <&mstp3_clks R8A7790_CLK_IIC0>;
|
2014-11-07 10:11:43 +00:00
|
|
|
dmas = <&dmac0 0x61>, <&dmac0 0x62>;
|
|
|
|
|
dma-names = "tx", "rx";
|
2014-03-25 18:56:29 +00:00
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
iic1: i2c@e6510000 {
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
|
|
|
|
|
reg = <0 0xe6510000 0 0x425>;
|
|
|
|
|
interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clocks = <&mstp3_clks R8A7790_CLK_IIC1>;
|
2014-11-07 10:11:43 +00:00
|
|
|
dmas = <&dmac0 0x65>, <&dmac0 0x66>;
|
|
|
|
|
dma-names = "tx", "rx";
|
2014-03-25 18:56:29 +00:00
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
iic2: i2c@e6520000 {
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
|
|
|
|
|
reg = <0 0xe6520000 0 0x425>;
|
|
|
|
|
interrupts = <0 176 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clocks = <&mstp3_clks R8A7790_CLK_IIC2>;
|
2014-11-07 10:11:43 +00:00
|
|
|
dmas = <&dmac0 0x69>, <&dmac0 0x6a>;
|
|
|
|
|
dma-names = "tx", "rx";
|
2014-03-25 18:56:29 +00:00
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
iic3: i2c@e60b0000 {
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
|
|
|
|
|
reg = <0 0xe60b0000 0 0x425>;
|
|
|
|
|
interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clocks = <&mstp9_clks R8A7790_CLK_IICDVFS>;
|
2014-11-07 10:11:43 +00:00
|
|
|
dmas = <&dmac0 0x77>, <&dmac0 0x78>;
|
|
|
|
|
dma-names = "tx", "rx";
|
2014-03-25 18:56:29 +00:00
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
2014-10-26 17:40:11 +00:00
|
|
|
mmcif0: mmc@ee200000 {
|
2013-11-20 00:05:53 +00:00
|
|
|
compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
|
2013-07-08 15:54:46 +00:00
|
|
|
reg = <0 0xee200000 0 0x80>;
|
2013-11-19 02:18:25 +00:00
|
|
|
interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>;
|
2013-12-11 14:05:15 +00:00
|
|
|
clocks = <&mstp3_clks R8A7790_CLK_MMCIF0>;
|
2014-10-26 17:40:13 +00:00
|
|
|
dmas = <&dmac0 0xd1>, <&dmac0 0xd2>;
|
|
|
|
|
dma-names = "tx", "rx";
|
2013-07-08 15:54:46 +00:00
|
|
|
reg-io-width = <4>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
2013-10-22 02:36:13 +00:00
|
|
|
mmcif1: mmc@ee220000 {
|
2013-11-20 00:05:53 +00:00
|
|
|
compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
|
2013-07-08 15:54:46 +00:00
|
|
|
reg = <0 0xee220000 0 0x80>;
|
2013-11-19 02:18:25 +00:00
|
|
|
interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>;
|
2013-12-11 14:05:15 +00:00
|
|
|
clocks = <&mstp3_clks R8A7790_CLK_MMCIF1>;
|
2014-10-26 17:40:13 +00:00
|
|
|
dmas = <&dmac0 0xe1>, <&dmac0 0xe2>;
|
|
|
|
|
dma-names = "tx", "rx";
|
2013-07-08 15:54:46 +00:00
|
|
|
reg-io-width = <4>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
2013-05-09 13:05:57 +00:00
|
|
|
pfc: pfc@e6060000 {
|
|
|
|
|
compatible = "renesas,pfc-r8a7790";
|
|
|
|
|
reg = <0 0xe6060000 0 0x250>;
|
|
|
|
|
};
|
2013-08-14 07:24:05 +00:00
|
|
|
|
2013-10-22 02:36:13 +00:00
|
|
|
sdhi0: sd@ee100000 {
|
2013-08-29 15:14:49 +00:00
|
|
|
compatible = "renesas,sdhi-r8a7790";
|
2015-02-24 02:20:37 +00:00
|
|
|
reg = <0 0xee100000 0 0x328>;
|
2013-11-19 02:18:25 +00:00
|
|
|
interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
|
2013-12-11 14:05:15 +00:00
|
|
|
clocks = <&mstp3_clks R8A7790_CLK_SDHI0>;
|
2015-02-24 02:20:03 +00:00
|
|
|
dmas = <&dmac1 0xcd>, <&dmac1 0xce>;
|
|
|
|
|
dma-names = "tx", "rx";
|
2013-07-08 15:54:46 +00:00
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
2013-10-22 02:36:13 +00:00
|
|
|
sdhi1: sd@ee120000 {
|
2013-08-29 15:14:49 +00:00
|
|
|
compatible = "renesas,sdhi-r8a7790";
|
2015-02-24 02:20:37 +00:00
|
|
|
reg = <0 0xee120000 0 0x328>;
|
2013-11-19 02:18:25 +00:00
|
|
|
interrupts = <0 166 IRQ_TYPE_LEVEL_HIGH>;
|
2013-12-11 14:05:15 +00:00
|
|
|
clocks = <&mstp3_clks R8A7790_CLK_SDHI1>;
|
2015-02-24 02:20:03 +00:00
|
|
|
dmas = <&dmac1 0xc9>, <&dmac1 0xca>;
|
|
|
|
|
dma-names = "tx", "rx";
|
2013-07-08 15:54:46 +00:00
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
2013-10-22 02:36:13 +00:00
|
|
|
sdhi2: sd@ee140000 {
|
2013-08-29 15:14:49 +00:00
|
|
|
compatible = "renesas,sdhi-r8a7790";
|
2013-07-08 15:54:46 +00:00
|
|
|
reg = <0 0xee140000 0 0x100>;
|
2013-11-19 02:18:25 +00:00
|
|
|
interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>;
|
2013-12-11 14:05:15 +00:00
|
|
|
clocks = <&mstp3_clks R8A7790_CLK_SDHI2>;
|
2015-02-24 02:20:03 +00:00
|
|
|
dmas = <&dmac1 0xc1>, <&dmac1 0xc2>;
|
|
|
|
|
dma-names = "tx", "rx";
|
2013-07-08 15:54:46 +00:00
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
2013-10-22 02:36:13 +00:00
|
|
|
sdhi3: sd@ee160000 {
|
2013-08-29 15:14:49 +00:00
|
|
|
compatible = "renesas,sdhi-r8a7790";
|
2013-07-08 15:54:46 +00:00
|
|
|
reg = <0 0xee160000 0 0x100>;
|
2013-11-19 02:18:25 +00:00
|
|
|
interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>;
|
2013-12-11 14:05:15 +00:00
|
|
|
clocks = <&mstp3_clks R8A7790_CLK_SDHI3>;
|
2015-02-24 02:20:03 +00:00
|
|
|
dmas = <&dmac1 0xd3>, <&dmac1 0xd4>;
|
|
|
|
|
dma-names = "tx", "rx";
|
2013-07-08 15:54:46 +00:00
|
|
|
status = "disabled";
|
|
|
|
|
};
|
2013-12-11 14:05:14 +00:00
|
|
|
|
2013-10-29 15:23:12 +00:00
|
|
|
scifa0: serial@e6c40000 {
|
2014-01-21 12:48:38 +00:00
|
|
|
compatible = "renesas,scifa-r8a7790", "renesas,scifa";
|
2013-10-29 15:23:12 +00:00
|
|
|
reg = <0 0xe6c40000 0 64>;
|
2014-01-21 12:48:39 +00:00
|
|
|
interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
|
2013-10-29 15:23:12 +00:00
|
|
|
clocks = <&mstp2_clks R8A7790_CLK_SCIFA0>;
|
|
|
|
|
clock-names = "sci_ick";
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
scifa1: serial@e6c50000 {
|
2014-01-21 12:48:38 +00:00
|
|
|
compatible = "renesas,scifa-r8a7790", "renesas,scifa";
|
2013-10-29 15:23:12 +00:00
|
|
|
reg = <0 0xe6c50000 0 64>;
|
2014-01-21 12:48:39 +00:00
|
|
|
interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
|
2013-10-29 15:23:12 +00:00
|
|
|
clocks = <&mstp2_clks R8A7790_CLK_SCIFA1>;
|
|
|
|
|
clock-names = "sci_ick";
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
scifa2: serial@e6c60000 {
|
2014-01-21 12:48:38 +00:00
|
|
|
compatible = "renesas,scifa-r8a7790", "renesas,scifa";
|
2013-10-29 15:23:12 +00:00
|
|
|
reg = <0 0xe6c60000 0 64>;
|
2014-01-21 12:48:39 +00:00
|
|
|
interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>;
|
2013-10-29 15:23:12 +00:00
|
|
|
clocks = <&mstp2_clks R8A7790_CLK_SCIFA2>;
|
|
|
|
|
clock-names = "sci_ick";
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
scifb0: serial@e6c20000 {
|
2014-01-21 12:48:38 +00:00
|
|
|
compatible = "renesas,scifb-r8a7790", "renesas,scifb";
|
2013-10-29 15:23:12 +00:00
|
|
|
reg = <0 0xe6c20000 0 64>;
|
2014-01-21 12:48:39 +00:00
|
|
|
interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
|
2013-10-29 15:23:12 +00:00
|
|
|
clocks = <&mstp2_clks R8A7790_CLK_SCIFB0>;
|
|
|
|
|
clock-names = "sci_ick";
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
scifb1: serial@e6c30000 {
|
2014-01-21 12:48:38 +00:00
|
|
|
compatible = "renesas,scifb-r8a7790", "renesas,scifb";
|
2013-10-29 15:23:12 +00:00
|
|
|
reg = <0 0xe6c30000 0 64>;
|
2014-01-21 12:48:39 +00:00
|
|
|
interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
|
2013-10-29 15:23:12 +00:00
|
|
|
clocks = <&mstp2_clks R8A7790_CLK_SCIFB1>;
|
|
|
|
|
clock-names = "sci_ick";
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
scifb2: serial@e6ce0000 {
|
2014-01-21 12:48:38 +00:00
|
|
|
compatible = "renesas,scifb-r8a7790", "renesas,scifb";
|
2013-10-29 15:23:12 +00:00
|
|
|
reg = <0 0xe6ce0000 0 64>;
|
2014-01-21 12:48:39 +00:00
|
|
|
interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
|
2013-10-29 15:23:12 +00:00
|
|
|
clocks = <&mstp2_clks R8A7790_CLK_SCIFB2>;
|
|
|
|
|
clock-names = "sci_ick";
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
scif0: serial@e6e60000 {
|
2014-01-21 12:48:38 +00:00
|
|
|
compatible = "renesas,scif-r8a7790", "renesas,scif";
|
2013-10-29 15:23:12 +00:00
|
|
|
reg = <0 0xe6e60000 0 64>;
|
2014-01-21 12:48:39 +00:00
|
|
|
interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>;
|
2013-10-29 15:23:12 +00:00
|
|
|
clocks = <&mstp7_clks R8A7790_CLK_SCIF0>;
|
|
|
|
|
clock-names = "sci_ick";
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
scif1: serial@e6e68000 {
|
2014-01-21 12:48:38 +00:00
|
|
|
compatible = "renesas,scif-r8a7790", "renesas,scif";
|
2013-10-29 15:23:12 +00:00
|
|
|
reg = <0 0xe6e68000 0 64>;
|
2014-01-21 12:48:39 +00:00
|
|
|
interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>;
|
2013-10-29 15:23:12 +00:00
|
|
|
clocks = <&mstp7_clks R8A7790_CLK_SCIF1>;
|
|
|
|
|
clock-names = "sci_ick";
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
hscif0: serial@e62c0000 {
|
2014-01-21 12:48:38 +00:00
|
|
|
compatible = "renesas,hscif-r8a7790", "renesas,hscif";
|
2013-10-29 15:23:12 +00:00
|
|
|
reg = <0 0xe62c0000 0 96>;
|
2014-01-21 12:48:39 +00:00
|
|
|
interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>;
|
2013-10-29 15:23:12 +00:00
|
|
|
clocks = <&mstp7_clks R8A7790_CLK_HSCIF0>;
|
|
|
|
|
clock-names = "sci_ick";
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
hscif1: serial@e62c8000 {
|
2014-01-21 12:48:38 +00:00
|
|
|
compatible = "renesas,hscif-r8a7790", "renesas,hscif";
|
2013-10-29 15:23:12 +00:00
|
|
|
reg = <0 0xe62c8000 0 96>;
|
2014-01-21 12:48:39 +00:00
|
|
|
interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>;
|
2013-10-29 15:23:12 +00:00
|
|
|
clocks = <&mstp7_clks R8A7790_CLK_HSCIF1>;
|
|
|
|
|
clock-names = "sci_ick";
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
2014-02-19 23:20:43 +00:00
|
|
|
ether: ethernet@ee700000 {
|
|
|
|
|
compatible = "renesas,ether-r8a7790";
|
|
|
|
|
reg = <0 0xee700000 0 0x400>;
|
|
|
|
|
interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clocks = <&mstp8_clks R8A7790_CLK_ETHER>;
|
|
|
|
|
phy-mode = "rmii";
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
2014-01-14 17:05:30 +00:00
|
|
|
sata0: sata@ee300000 {
|
|
|
|
|
compatible = "renesas,sata-r8a7790";
|
|
|
|
|
reg = <0 0xee300000 0 0x2000>;
|
|
|
|
|
interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clocks = <&mstp8_clks R8A7790_CLK_SATA0>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
sata1: sata@ee500000 {
|
|
|
|
|
compatible = "renesas,sata-r8a7790";
|
|
|
|
|
reg = <0 0xee500000 0 0x2000>;
|
|
|
|
|
interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clocks = <&mstp8_clks R8A7790_CLK_SATA1>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
2014-10-24 10:44:33 +00:00
|
|
|
hsusb: usb@e6590000 {
|
|
|
|
|
compatible = "renesas,usbhs-r8a7790";
|
|
|
|
|
reg = <0 0xe6590000 0 0x100>;
|
|
|
|
|
interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clocks = <&mstp7_clks R8A7790_CLK_HSUSB>;
|
|
|
|
|
renesas,buswait = <4>;
|
|
|
|
|
phys = <&usb0 1>;
|
|
|
|
|
phy-names = "usb";
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
2014-09-26 21:00:20 +00:00
|
|
|
usbphy: usb-phy@e6590100 {
|
|
|
|
|
compatible = "renesas,usb-phy-r8a7790";
|
|
|
|
|
reg = <0 0xe6590100 0 0x100>;
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
clocks = <&mstp7_clks R8A7790_CLK_HSUSB>;
|
|
|
|
|
clock-names = "usbhs";
|
|
|
|
|
status = "disabled";
|
|
|
|
|
|
|
|
|
|
usb0: usb-channel@0 {
|
|
|
|
|
reg = <0>;
|
|
|
|
|
#phy-cells = <1>;
|
|
|
|
|
};
|
|
|
|
|
usb2: usb-channel@2 {
|
|
|
|
|
reg = <2>;
|
|
|
|
|
#phy-cells = <1>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
2014-08-12 20:16:18 +00:00
|
|
|
vin0: video@e6ef0000 {
|
|
|
|
|
compatible = "renesas,vin-r8a7790";
|
|
|
|
|
clocks = <&mstp8_clks R8A7790_CLK_VIN0>;
|
|
|
|
|
reg = <0 0xe6ef0000 0 0x1000>;
|
|
|
|
|
interrupts = <0 188 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
vin1: video@e6ef1000 {
|
|
|
|
|
compatible = "renesas,vin-r8a7790";
|
|
|
|
|
clocks = <&mstp8_clks R8A7790_CLK_VIN1>;
|
|
|
|
|
reg = <0 0xe6ef1000 0 0x1000>;
|
|
|
|
|
interrupts = <0 189 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
vin2: video@e6ef2000 {
|
|
|
|
|
compatible = "renesas,vin-r8a7790";
|
|
|
|
|
clocks = <&mstp8_clks R8A7790_CLK_VIN2>;
|
|
|
|
|
reg = <0 0xe6ef2000 0 0x1000>;
|
|
|
|
|
interrupts = <0 190 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
vin3: video@e6ef3000 {
|
|
|
|
|
compatible = "renesas,vin-r8a7790";
|
|
|
|
|
clocks = <&mstp8_clks R8A7790_CLK_VIN3>;
|
|
|
|
|
reg = <0 0xe6ef3000 0 0x1000>;
|
|
|
|
|
interrupts = <0 191 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
2014-01-21 15:00:46 +00:00
|
|
|
vsp1@fe920000 {
|
|
|
|
|
compatible = "renesas,vsp1";
|
|
|
|
|
reg = <0 0xfe920000 0 0x8000>;
|
|
|
|
|
interrupts = <0 266 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clocks = <&mstp1_clks R8A7790_CLK_VSP1_R>;
|
|
|
|
|
|
|
|
|
|
renesas,has-sru;
|
|
|
|
|
renesas,#rpf = <5>;
|
|
|
|
|
renesas,#uds = <1>;
|
|
|
|
|
renesas,#wpf = <4>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
vsp1@fe928000 {
|
|
|
|
|
compatible = "renesas,vsp1";
|
|
|
|
|
reg = <0 0xfe928000 0 0x8000>;
|
|
|
|
|
interrupts = <0 267 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clocks = <&mstp1_clks R8A7790_CLK_VSP1_S>;
|
|
|
|
|
|
|
|
|
|
renesas,has-lut;
|
|
|
|
|
renesas,has-sru;
|
|
|
|
|
renesas,#rpf = <5>;
|
|
|
|
|
renesas,#uds = <3>;
|
|
|
|
|
renesas,#wpf = <4>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
vsp1@fe930000 {
|
|
|
|
|
compatible = "renesas,vsp1";
|
|
|
|
|
reg = <0 0xfe930000 0 0x8000>;
|
|
|
|
|
interrupts = <0 246 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clocks = <&mstp1_clks R8A7790_CLK_VSP1_DU0>;
|
|
|
|
|
|
|
|
|
|
renesas,has-lif;
|
|
|
|
|
renesas,has-lut;
|
|
|
|
|
renesas,#rpf = <4>;
|
|
|
|
|
renesas,#uds = <1>;
|
|
|
|
|
renesas,#wpf = <4>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
vsp1@fe938000 {
|
|
|
|
|
compatible = "renesas,vsp1";
|
|
|
|
|
reg = <0 0xfe938000 0 0x8000>;
|
|
|
|
|
interrupts = <0 247 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clocks = <&mstp1_clks R8A7790_CLK_VSP1_DU1>;
|
|
|
|
|
|
|
|
|
|
renesas,has-lif;
|
|
|
|
|
renesas,has-lut;
|
|
|
|
|
renesas,#rpf = <4>;
|
|
|
|
|
renesas,#uds = <1>;
|
|
|
|
|
renesas,#wpf = <4>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
du: display@feb00000 {
|
|
|
|
|
compatible = "renesas,du-r8a7790";
|
|
|
|
|
reg = <0 0xfeb00000 0 0x70000>,
|
|
|
|
|
<0 0xfeb90000 0 0x1c>,
|
|
|
|
|
<0 0xfeb94000 0 0x1c>;
|
|
|
|
|
reg-names = "du", "lvds.0", "lvds.1";
|
|
|
|
|
interrupts = <0 256 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<0 268 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<0 269 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clocks = <&mstp7_clks R8A7790_CLK_DU0>,
|
|
|
|
|
<&mstp7_clks R8A7790_CLK_DU1>,
|
|
|
|
|
<&mstp7_clks R8A7790_CLK_DU2>,
|
|
|
|
|
<&mstp7_clks R8A7790_CLK_LVDS0>,
|
|
|
|
|
<&mstp7_clks R8A7790_CLK_LVDS1>;
|
|
|
|
|
clock-names = "du.0", "du.1", "du.2", "lvds.0", "lvds.1";
|
|
|
|
|
status = "disabled";
|
|
|
|
|
|
|
|
|
|
ports {
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
|
|
|
|
|
port@0 {
|
|
|
|
|
reg = <0>;
|
|
|
|
|
du_out_rgb: endpoint {
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
port@1 {
|
|
|
|
|
reg = <1>;
|
|
|
|
|
du_out_lvds0: endpoint {
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
port@2 {
|
|
|
|
|
reg = <2>;
|
|
|
|
|
du_out_lvds1: endpoint {
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
2015-01-05 21:34:42 +00:00
|
|
|
can0: can@e6e80000 {
|
|
|
|
|
compatible = "renesas,can-r8a7790";
|
|
|
|
|
reg = <0 0xe6e80000 0 0x1000>;
|
|
|
|
|
interrupts = <0 186 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clocks = <&mstp9_clks R8A7790_CLK_RCAN0>,
|
|
|
|
|
<&cpg_clocks R8A7790_CLK_RCAN>, <&can_clk>;
|
|
|
|
|
clock-names = "clkp1", "clkp2", "can_clk";
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
can1: can@e6e88000 {
|
|
|
|
|
compatible = "renesas,can-r8a7790";
|
|
|
|
|
reg = <0 0xe6e88000 0 0x1000>;
|
|
|
|
|
interrupts = <0 187 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clocks = <&mstp9_clks R8A7790_CLK_RCAN1>,
|
|
|
|
|
<&cpg_clocks R8A7790_CLK_RCAN>, <&can_clk>;
|
|
|
|
|
clock-names = "clkp1", "clkp2", "can_clk";
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
2013-12-11 14:05:14 +00:00
|
|
|
clocks {
|
|
|
|
|
#address-cells = <2>;
|
|
|
|
|
#size-cells = <2>;
|
|
|
|
|
ranges;
|
|
|
|
|
|
|
|
|
|
/* External root clock */
|
|
|
|
|
extal_clk: extal_clk {
|
|
|
|
|
compatible = "fixed-clock";
|
|
|
|
|
#clock-cells = <0>;
|
|
|
|
|
/* This value must be overriden by the board. */
|
|
|
|
|
clock-frequency = <0>;
|
|
|
|
|
clock-output-names = "extal";
|
|
|
|
|
};
|
|
|
|
|
|
2014-06-13 09:37:16 +00:00
|
|
|
/* External PCIe clock - can be overridden by the board */
|
|
|
|
|
pcie_bus_clk: pcie_bus_clk {
|
|
|
|
|
compatible = "fixed-clock";
|
|
|
|
|
#clock-cells = <0>;
|
|
|
|
|
clock-frequency = <100000000>;
|
|
|
|
|
clock-output-names = "pcie_bus";
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
2014-01-14 02:25:39 +00:00
|
|
|
/*
|
|
|
|
|
* The external audio clocks are configured as 0 Hz fixed frequency clocks by
|
|
|
|
|
* default. Boards that provide audio clocks should override them.
|
|
|
|
|
*/
|
|
|
|
|
audio_clk_a: audio_clk_a {
|
|
|
|
|
compatible = "fixed-clock";
|
|
|
|
|
#clock-cells = <0>;
|
|
|
|
|
clock-frequency = <0>;
|
|
|
|
|
clock-output-names = "audio_clk_a";
|
|
|
|
|
};
|
|
|
|
|
audio_clk_b: audio_clk_b {
|
|
|
|
|
compatible = "fixed-clock";
|
|
|
|
|
#clock-cells = <0>;
|
|
|
|
|
clock-frequency = <0>;
|
|
|
|
|
clock-output-names = "audio_clk_b";
|
|
|
|
|
};
|
|
|
|
|
audio_clk_c: audio_clk_c {
|
|
|
|
|
compatible = "fixed-clock";
|
|
|
|
|
#clock-cells = <0>;
|
|
|
|
|
clock-frequency = <0>;
|
|
|
|
|
clock-output-names = "audio_clk_c";
|
|
|
|
|
};
|
|
|
|
|
|
2015-01-05 21:33:25 +00:00
|
|
|
/* External USB clock - can be overridden by the board */
|
|
|
|
|
usb_extal_clk: usb_extal_clk {
|
|
|
|
|
compatible = "fixed-clock";
|
|
|
|
|
#clock-cells = <0>;
|
|
|
|
|
clock-frequency = <48000000>;
|
|
|
|
|
clock-output-names = "usb_extal";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
/* External CAN clock */
|
|
|
|
|
can_clk: can_clk {
|
|
|
|
|
compatible = "fixed-clock";
|
|
|
|
|
#clock-cells = <0>;
|
|
|
|
|
/* This value must be overridden by the board. */
|
|
|
|
|
clock-frequency = <0>;
|
|
|
|
|
clock-output-names = "can_clk";
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
2013-12-11 14:05:14 +00:00
|
|
|
/* Special CPG clocks */
|
|
|
|
|
cpg_clocks: cpg_clocks@e6150000 {
|
|
|
|
|
compatible = "renesas,r8a7790-cpg-clocks",
|
|
|
|
|
"renesas,rcar-gen2-cpg-clocks";
|
|
|
|
|
reg = <0 0xe6150000 0 0x1000>;
|
2015-01-05 21:33:25 +00:00
|
|
|
clocks = <&extal_clk &usb_extal_clk>;
|
2013-12-11 14:05:14 +00:00
|
|
|
#clock-cells = <1>;
|
|
|
|
|
clock-output-names = "main", "pll0", "pll1", "pll3",
|
|
|
|
|
"lb", "qspi", "sdh", "sd0", "sd1",
|
2014-12-30 20:21:45 +00:00
|
|
|
"z", "rcan", "adsp";
|
2013-12-11 14:05:14 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
/* Variable factor clocks */
|
|
|
|
|
sd2_clk: sd2_clk@e6150078 {
|
|
|
|
|
compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
|
|
|
|
|
reg = <0 0xe6150078 0 4>;
|
|
|
|
|
clocks = <&pll1_div2_clk>;
|
|
|
|
|
#clock-cells = <0>;
|
|
|
|
|
clock-output-names = "sd2";
|
|
|
|
|
};
|
2014-10-30 05:57:57 +00:00
|
|
|
sd3_clk: sd3_clk@e615026c {
|
2013-12-11 14:05:14 +00:00
|
|
|
compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
|
2014-10-30 05:57:57 +00:00
|
|
|
reg = <0 0xe615026c 0 4>;
|
2013-12-11 14:05:14 +00:00
|
|
|
clocks = <&pll1_div2_clk>;
|
|
|
|
|
#clock-cells = <0>;
|
|
|
|
|
clock-output-names = "sd3";
|
|
|
|
|
};
|
|
|
|
|
mmc0_clk: mmc0_clk@e6150240 {
|
|
|
|
|
compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
|
|
|
|
|
reg = <0 0xe6150240 0 4>;
|
|
|
|
|
clocks = <&pll1_div2_clk>;
|
|
|
|
|
#clock-cells = <0>;
|
|
|
|
|
clock-output-names = "mmc0";
|
|
|
|
|
};
|
|
|
|
|
mmc1_clk: mmc1_clk@e6150244 {
|
|
|
|
|
compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
|
|
|
|
|
reg = <0 0xe6150244 0 4>;
|
|
|
|
|
clocks = <&pll1_div2_clk>;
|
|
|
|
|
#clock-cells = <0>;
|
|
|
|
|
clock-output-names = "mmc1";
|
|
|
|
|
};
|
|
|
|
|
ssp_clk: ssp_clk@e6150248 {
|
|
|
|
|
compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
|
|
|
|
|
reg = <0 0xe6150248 0 4>;
|
|
|
|
|
clocks = <&pll1_div2_clk>;
|
|
|
|
|
#clock-cells = <0>;
|
|
|
|
|
clock-output-names = "ssp";
|
|
|
|
|
};
|
|
|
|
|
ssprs_clk: ssprs_clk@e615024c {
|
|
|
|
|
compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
|
|
|
|
|
reg = <0 0xe615024c 0 4>;
|
|
|
|
|
clocks = <&pll1_div2_clk>;
|
|
|
|
|
#clock-cells = <0>;
|
|
|
|
|
clock-output-names = "ssprs";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
/* Fixed factor clocks */
|
|
|
|
|
pll1_div2_clk: pll1_div2_clk {
|
|
|
|
|
compatible = "fixed-factor-clock";
|
|
|
|
|
clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
|
|
|
|
|
#clock-cells = <0>;
|
|
|
|
|
clock-div = <2>;
|
|
|
|
|
clock-mult = <1>;
|
|
|
|
|
clock-output-names = "pll1_div2";
|
|
|
|
|
};
|
|
|
|
|
z2_clk: z2_clk {
|
|
|
|
|
compatible = "fixed-factor-clock";
|
|
|
|
|
clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
|
|
|
|
|
#clock-cells = <0>;
|
|
|
|
|
clock-div = <2>;
|
|
|
|
|
clock-mult = <1>;
|
|
|
|
|
clock-output-names = "z2";
|
|
|
|
|
};
|
|
|
|
|
zg_clk: zg_clk {
|
|
|
|
|
compatible = "fixed-factor-clock";
|
|
|
|
|
clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
|
|
|
|
|
#clock-cells = <0>;
|
|
|
|
|
clock-div = <3>;
|
|
|
|
|
clock-mult = <1>;
|
|
|
|
|
clock-output-names = "zg";
|
|
|
|
|
};
|
|
|
|
|
zx_clk: zx_clk {
|
|
|
|
|
compatible = "fixed-factor-clock";
|
|
|
|
|
clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
|
|
|
|
|
#clock-cells = <0>;
|
|
|
|
|
clock-div = <3>;
|
|
|
|
|
clock-mult = <1>;
|
|
|
|
|
clock-output-names = "zx";
|
|
|
|
|
};
|
|
|
|
|
zs_clk: zs_clk {
|
|
|
|
|
compatible = "fixed-factor-clock";
|
|
|
|
|
clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
|
|
|
|
|
#clock-cells = <0>;
|
|
|
|
|
clock-div = <6>;
|
|
|
|
|
clock-mult = <1>;
|
|
|
|
|
clock-output-names = "zs";
|
|
|
|
|
};
|
|
|
|
|
hp_clk: hp_clk {
|
|
|
|
|
compatible = "fixed-factor-clock";
|
|
|
|
|
clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
|
|
|
|
|
#clock-cells = <0>;
|
|
|
|
|
clock-div = <12>;
|
|
|
|
|
clock-mult = <1>;
|
|
|
|
|
clock-output-names = "hp";
|
|
|
|
|
};
|
|
|
|
|
i_clk: i_clk {
|
|
|
|
|
compatible = "fixed-factor-clock";
|
|
|
|
|
clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
|
|
|
|
|
#clock-cells = <0>;
|
|
|
|
|
clock-div = <2>;
|
|
|
|
|
clock-mult = <1>;
|
|
|
|
|
clock-output-names = "i";
|
|
|
|
|
};
|
|
|
|
|
b_clk: b_clk {
|
|
|
|
|
compatible = "fixed-factor-clock";
|
|
|
|
|
clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
|
|
|
|
|
#clock-cells = <0>;
|
|
|
|
|
clock-div = <12>;
|
|
|
|
|
clock-mult = <1>;
|
|
|
|
|
clock-output-names = "b";
|
|
|
|
|
};
|
|
|
|
|
p_clk: p_clk {
|
|
|
|
|
compatible = "fixed-factor-clock";
|
|
|
|
|
clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
|
|
|
|
|
#clock-cells = <0>;
|
|
|
|
|
clock-div = <24>;
|
|
|
|
|
clock-mult = <1>;
|
|
|
|
|
clock-output-names = "p";
|
|
|
|
|
};
|
|
|
|
|
cl_clk: cl_clk {
|
|
|
|
|
compatible = "fixed-factor-clock";
|
|
|
|
|
clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
|
|
|
|
|
#clock-cells = <0>;
|
|
|
|
|
clock-div = <48>;
|
|
|
|
|
clock-mult = <1>;
|
|
|
|
|
clock-output-names = "cl";
|
|
|
|
|
};
|
|
|
|
|
m2_clk: m2_clk {
|
|
|
|
|
compatible = "fixed-factor-clock";
|
|
|
|
|
clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
|
|
|
|
|
#clock-cells = <0>;
|
|
|
|
|
clock-div = <8>;
|
|
|
|
|
clock-mult = <1>;
|
|
|
|
|
clock-output-names = "m2";
|
|
|
|
|
};
|
|
|
|
|
imp_clk: imp_clk {
|
|
|
|
|
compatible = "fixed-factor-clock";
|
|
|
|
|
clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
|
|
|
|
|
#clock-cells = <0>;
|
|
|
|
|
clock-div = <4>;
|
|
|
|
|
clock-mult = <1>;
|
|
|
|
|
clock-output-names = "imp";
|
|
|
|
|
};
|
|
|
|
|
rclk_clk: rclk_clk {
|
|
|
|
|
compatible = "fixed-factor-clock";
|
|
|
|
|
clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
|
|
|
|
|
#clock-cells = <0>;
|
|
|
|
|
clock-div = <(48 * 1024)>;
|
|
|
|
|
clock-mult = <1>;
|
|
|
|
|
clock-output-names = "rclk";
|
|
|
|
|
};
|
|
|
|
|
oscclk_clk: oscclk_clk {
|
|
|
|
|
compatible = "fixed-factor-clock";
|
|
|
|
|
clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
|
|
|
|
|
#clock-cells = <0>;
|
|
|
|
|
clock-div = <(12 * 1024)>;
|
|
|
|
|
clock-mult = <1>;
|
|
|
|
|
clock-output-names = "oscclk";
|
|
|
|
|
};
|
|
|
|
|
zb3_clk: zb3_clk {
|
|
|
|
|
compatible = "fixed-factor-clock";
|
|
|
|
|
clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
|
|
|
|
|
#clock-cells = <0>;
|
|
|
|
|
clock-div = <4>;
|
|
|
|
|
clock-mult = <1>;
|
|
|
|
|
clock-output-names = "zb3";
|
|
|
|
|
};
|
|
|
|
|
zb3d2_clk: zb3d2_clk {
|
|
|
|
|
compatible = "fixed-factor-clock";
|
|
|
|
|
clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
|
|
|
|
|
#clock-cells = <0>;
|
|
|
|
|
clock-div = <8>;
|
|
|
|
|
clock-mult = <1>;
|
|
|
|
|
clock-output-names = "zb3d2";
|
|
|
|
|
};
|
|
|
|
|
ddr_clk: ddr_clk {
|
|
|
|
|
compatible = "fixed-factor-clock";
|
|
|
|
|
clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
|
|
|
|
|
#clock-cells = <0>;
|
|
|
|
|
clock-div = <8>;
|
|
|
|
|
clock-mult = <1>;
|
|
|
|
|
clock-output-names = "ddr";
|
|
|
|
|
};
|
|
|
|
|
mp_clk: mp_clk {
|
|
|
|
|
compatible = "fixed-factor-clock";
|
|
|
|
|
clocks = <&pll1_div2_clk>;
|
|
|
|
|
#clock-cells = <0>;
|
|
|
|
|
clock-div = <15>;
|
|
|
|
|
clock-mult = <1>;
|
|
|
|
|
clock-output-names = "mp";
|
|
|
|
|
};
|
|
|
|
|
cp_clk: cp_clk {
|
|
|
|
|
compatible = "fixed-factor-clock";
|
|
|
|
|
clocks = <&extal_clk>;
|
|
|
|
|
#clock-cells = <0>;
|
|
|
|
|
clock-div = <2>;
|
|
|
|
|
clock-mult = <1>;
|
|
|
|
|
clock-output-names = "cp";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
/* Gate clocks */
|
2013-12-19 15:51:01 +00:00
|
|
|
mstp0_clks: mstp0_clks@e6150130 {
|
|
|
|
|
compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
|
|
|
|
|
reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
|
|
|
|
|
clocks = <&mp_clk>;
|
|
|
|
|
#clock-cells = <1>;
|
2014-11-10 18:49:37 +00:00
|
|
|
clock-indices = <R8A7790_CLK_MSIOF0>;
|
2013-12-19 15:51:01 +00:00
|
|
|
clock-output-names = "msiof0";
|
|
|
|
|
};
|
2013-12-11 14:05:14 +00:00
|
|
|
mstp1_clks: mstp1_clks@e6150134 {
|
|
|
|
|
compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
|
|
|
|
|
reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
|
2014-10-14 07:01:42 +00:00
|
|
|
clocks = <&zs_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&m2_clk>,
|
|
|
|
|
<&zs_clk>, <&p_clk>, <&zg_clk>, <&zs_clk>, <&zs_clk>,
|
|
|
|
|
<&zs_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
|
|
|
|
|
<&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>;
|
2013-12-11 14:05:14 +00:00
|
|
|
#clock-cells = <1>;
|
2014-11-10 18:49:37 +00:00
|
|
|
clock-indices = <
|
2014-10-14 07:01:42 +00:00
|
|
|
R8A7790_CLK_VCP1 R8A7790_CLK_VCP0 R8A7790_CLK_VPC1
|
|
|
|
|
R8A7790_CLK_VPC0 R8A7790_CLK_JPU R8A7790_CLK_SSP1
|
|
|
|
|
R8A7790_CLK_TMU1 R8A7790_CLK_3DG R8A7790_CLK_2DDMAC
|
|
|
|
|
R8A7790_CLK_FDP1_2 R8A7790_CLK_FDP1_1 R8A7790_CLK_FDP1_0
|
|
|
|
|
R8A7790_CLK_TMU3 R8A7790_CLK_TMU2 R8A7790_CLK_CMT0
|
|
|
|
|
R8A7790_CLK_TMU0 R8A7790_CLK_VSP1_DU1 R8A7790_CLK_VSP1_DU0
|
|
|
|
|
R8A7790_CLK_VSP1_R R8A7790_CLK_VSP1_S
|
2013-12-11 14:05:14 +00:00
|
|
|
>;
|
|
|
|
|
clock-output-names =
|
2014-10-14 07:01:42 +00:00
|
|
|
"vcp1", "vcp0", "vpc1", "vpc0", "jpu", "ssp1",
|
|
|
|
|
"tmu1", "3dg", "2ddmac", "fdp1-2", "fdp1-1",
|
|
|
|
|
"fdp1-0", "tmu3", "tmu2", "cmt0", "tmu0",
|
2014-10-14 07:01:40 +00:00
|
|
|
"vsp1-du1", "vsp1-du0", "vsp1-rt", "vsp1-sy";
|
2013-12-11 14:05:14 +00:00
|
|
|
};
|
|
|
|
|
mstp2_clks: mstp2_clks@e6150138 {
|
|
|
|
|
compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
|
|
|
|
|
reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
|
|
|
|
|
clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
|
2014-07-18 23:50:23 +00:00
|
|
|
<&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&zs_clk>,
|
|
|
|
|
<&zs_clk>;
|
2013-12-11 14:05:14 +00:00
|
|
|
#clock-cells = <1>;
|
2014-11-10 18:49:37 +00:00
|
|
|
clock-indices = <
|
2013-12-11 14:05:14 +00:00
|
|
|
R8A7790_CLK_SCIFA2 R8A7790_CLK_SCIFA1 R8A7790_CLK_SCIFA0
|
2013-12-19 15:51:01 +00:00
|
|
|
R8A7790_CLK_MSIOF2 R8A7790_CLK_SCIFB0 R8A7790_CLK_SCIFB1
|
|
|
|
|
R8A7790_CLK_MSIOF1 R8A7790_CLK_MSIOF3 R8A7790_CLK_SCIFB2
|
2014-07-18 23:50:23 +00:00
|
|
|
R8A7790_CLK_SYS_DMAC1 R8A7790_CLK_SYS_DMAC0
|
2013-12-11 14:05:14 +00:00
|
|
|
>;
|
|
|
|
|
clock-output-names =
|
2013-12-19 15:51:01 +00:00
|
|
|
"scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
|
2014-07-18 23:50:23 +00:00
|
|
|
"scifb1", "msiof1", "msiof3", "scifb2",
|
|
|
|
|
"sys-dmac1", "sys-dmac0";
|
2013-12-11 14:05:14 +00:00
|
|
|
};
|
|
|
|
|
mstp3_clks: mstp3_clks@e615013c {
|
|
|
|
|
compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
|
|
|
|
|
reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
|
2014-03-11 21:24:37 +00:00
|
|
|
clocks = <&hp_clk>, <&cp_clk>, <&mmc1_clk>, <&sd3_clk>,
|
|
|
|
|
<&sd2_clk>, <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>, <&mmc0_clk>,
|
2014-11-17 09:25:13 +00:00
|
|
|
<&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>,
|
|
|
|
|
<&hp_clk>, <&hp_clk>;
|
2013-12-11 14:05:14 +00:00
|
|
|
#clock-cells = <1>;
|
2014-11-10 18:49:37 +00:00
|
|
|
clock-indices = <
|
2014-03-11 21:24:37 +00:00
|
|
|
R8A7790_CLK_IIC2 R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3
|
|
|
|
|
R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0 R8A7790_CLK_MMCIF0
|
2014-06-13 09:37:15 +00:00
|
|
|
R8A7790_CLK_IIC0 R8A7790_CLK_PCIEC R8A7790_CLK_IIC1 R8A7790_CLK_SSUSB R8A7790_CLK_CMT1
|
2014-11-17 09:25:13 +00:00
|
|
|
R8A7790_CLK_USBDMAC0 R8A7790_CLK_USBDMAC1
|
2013-12-11 14:05:14 +00:00
|
|
|
>;
|
|
|
|
|
clock-output-names =
|
2014-03-11 21:24:37 +00:00
|
|
|
"iic2", "tpu0", "mmcif1", "sdhi3",
|
|
|
|
|
"sdhi2", "sdhi1", "sdhi0", "mmcif0",
|
2014-11-17 09:25:13 +00:00
|
|
|
"iic0", "pciec", "iic1", "ssusb", "cmt1",
|
|
|
|
|
"usbdmac0", "usbdmac1";
|
2013-12-11 14:05:14 +00:00
|
|
|
};
|
2015-03-18 18:55:59 +00:00
|
|
|
mstp4_clks: mstp4_clks@e6150140 {
|
|
|
|
|
compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
|
|
|
|
|
reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
|
|
|
|
|
clocks = <&cp_clk>;
|
|
|
|
|
#clock-cells = <1>;
|
|
|
|
|
clock-indices = <R8A7790_CLK_IRQC>;
|
|
|
|
|
clock-output-names = "irqc";
|
|
|
|
|
};
|
2013-12-11 14:05:14 +00:00
|
|
|
mstp5_clks: mstp5_clks@e6150144 {
|
|
|
|
|
compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
|
|
|
|
|
reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
|
2014-12-30 20:21:45 +00:00
|
|
|
clocks = <&hp_clk>, <&hp_clk>, <&cpg_clocks R8A7790_CLK_ADSP>,
|
|
|
|
|
<&extal_clk>, <&p_clk>;
|
2013-12-11 14:05:14 +00:00
|
|
|
#clock-cells = <1>;
|
2014-11-10 18:49:37 +00:00
|
|
|
clock-indices = <
|
|
|
|
|
R8A7790_CLK_AUDIO_DMAC0 R8A7790_CLK_AUDIO_DMAC1
|
2014-12-30 20:21:45 +00:00
|
|
|
R8A7790_CLK_ADSP_MOD R8A7790_CLK_THERMAL
|
|
|
|
|
R8A7790_CLK_PWM
|
2014-11-10 18:49:37 +00:00
|
|
|
>;
|
2014-12-30 20:21:45 +00:00
|
|
|
clock-output-names = "audmac0", "audmac1", "adsp_mod",
|
|
|
|
|
"thermal", "pwm";
|
2013-12-11 14:05:14 +00:00
|
|
|
};
|
|
|
|
|
mstp7_clks: mstp7_clks@e615014c {
|
|
|
|
|
compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
|
|
|
|
|
reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
|
2015-02-19 15:42:55 +00:00
|
|
|
clocks = <&mp_clk>, <&hp_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
|
2013-12-11 14:05:14 +00:00
|
|
|
<&p_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>,
|
|
|
|
|
<&zx_clk>;
|
|
|
|
|
#clock-cells = <1>;
|
2014-11-10 18:49:37 +00:00
|
|
|
clock-indices = <
|
2013-12-11 14:05:14 +00:00
|
|
|
R8A7790_CLK_EHCI R8A7790_CLK_HSUSB R8A7790_CLK_HSCIF1
|
|
|
|
|
R8A7790_CLK_HSCIF0 R8A7790_CLK_SCIF1 R8A7790_CLK_SCIF0
|
|
|
|
|
R8A7790_CLK_DU2 R8A7790_CLK_DU1 R8A7790_CLK_DU0
|
|
|
|
|
R8A7790_CLK_LVDS1 R8A7790_CLK_LVDS0
|
|
|
|
|
>;
|
|
|
|
|
clock-output-names =
|
|
|
|
|
"ehci", "hsusb", "hscif1", "hscif0", "scif1",
|
|
|
|
|
"scif0", "du2", "du1", "du0", "lvds1", "lvds0";
|
|
|
|
|
};
|
|
|
|
|
mstp8_clks: mstp8_clks@e6150990 {
|
|
|
|
|
compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
|
|
|
|
|
reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
|
2014-12-18 20:41:52 +00:00
|
|
|
clocks = <&hp_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>,
|
|
|
|
|
<&zg_clk>, <&p_clk>, <&zs_clk>, <&zs_clk>;
|
2013-12-11 14:05:14 +00:00
|
|
|
#clock-cells = <1>;
|
2014-11-10 18:49:37 +00:00
|
|
|
clock-indices = <
|
2014-12-18 20:41:52 +00:00
|
|
|
R8A7790_CLK_MLB R8A7790_CLK_VIN3 R8A7790_CLK_VIN2
|
|
|
|
|
R8A7790_CLK_VIN1 R8A7790_CLK_VIN0 R8A7790_CLK_ETHER
|
|
|
|
|
R8A7790_CLK_SATA1 R8A7790_CLK_SATA0
|
2014-01-07 08:22:53 +00:00
|
|
|
>;
|
2014-01-07 08:22:55 +00:00
|
|
|
clock-output-names =
|
2014-12-18 20:41:52 +00:00
|
|
|
"mlb", "vin3", "vin2", "vin1", "vin0", "ether",
|
|
|
|
|
"sata1", "sata0";
|
2013-12-11 14:05:14 +00:00
|
|
|
};
|
|
|
|
|
mstp9_clks: mstp9_clks@e6150994 {
|
|
|
|
|
compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
|
|
|
|
|
reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
|
2014-04-23 08:25:27 +00:00
|
|
|
clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>,
|
|
|
|
|
<&cp_clk>, <&cp_clk>, <&cp_clk>,
|
|
|
|
|
<&p_clk>, <&p_clk>, <&cpg_clocks R8A7790_CLK_QSPI>, <&cp_clk>,
|
2014-04-01 11:02:17 +00:00
|
|
|
<&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>;
|
2013-12-11 14:05:14 +00:00
|
|
|
#clock-cells = <1>;
|
2014-11-10 18:49:37 +00:00
|
|
|
clock-indices = <
|
2014-04-23 08:25:27 +00:00
|
|
|
R8A7790_CLK_GPIO5 R8A7790_CLK_GPIO4 R8A7790_CLK_GPIO3
|
|
|
|
|
R8A7790_CLK_GPIO2 R8A7790_CLK_GPIO1 R8A7790_CLK_GPIO0
|
2014-03-11 21:24:37 +00:00
|
|
|
R8A7790_CLK_RCAN1 R8A7790_CLK_RCAN0 R8A7790_CLK_QSPI_MOD R8A7790_CLK_IICDVFS
|
|
|
|
|
R8A7790_CLK_I2C3 R8A7790_CLK_I2C2 R8A7790_CLK_I2C1 R8A7790_CLK_I2C0
|
2013-12-11 14:05:14 +00:00
|
|
|
>;
|
2013-12-19 15:51:03 +00:00
|
|
|
clock-output-names =
|
2014-04-23 08:25:27 +00:00
|
|
|
"gpio5", "gpio4", "gpio3", "gpio2", "gpio1", "gpio0",
|
2014-03-11 21:24:37 +00:00
|
|
|
"rcan1", "rcan0", "qspi_mod", "iic3",
|
|
|
|
|
"i2c3", "i2c2", "i2c1", "i2c0";
|
2013-12-11 14:05:14 +00:00
|
|
|
};
|
2014-06-11 06:53:27 +00:00
|
|
|
mstp10_clks: mstp10_clks@e6150998 {
|
|
|
|
|
compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
|
|
|
|
|
reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
|
|
|
|
|
clocks = <&p_clk>,
|
|
|
|
|
<&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
|
|
|
|
|
<&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
|
|
|
|
|
<&p_clk>,
|
|
|
|
|
<&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
|
|
|
|
|
<&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
|
|
|
|
|
<&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
|
|
|
|
|
<&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
|
|
|
|
|
<&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
|
|
|
|
|
<&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>;
|
|
|
|
|
|
|
|
|
|
#clock-cells = <1>;
|
|
|
|
|
clock-indices = <
|
|
|
|
|
R8A7790_CLK_SSI_ALL
|
|
|
|
|
R8A7790_CLK_SSI9 R8A7790_CLK_SSI8 R8A7790_CLK_SSI7 R8A7790_CLK_SSI6 R8A7790_CLK_SSI5
|
|
|
|
|
R8A7790_CLK_SSI4 R8A7790_CLK_SSI3 R8A7790_CLK_SSI2 R8A7790_CLK_SSI1 R8A7790_CLK_SSI0
|
|
|
|
|
R8A7790_CLK_SCU_ALL
|
|
|
|
|
R8A7790_CLK_SCU_DVC1 R8A7790_CLK_SCU_DVC0
|
|
|
|
|
R8A7790_CLK_SCU_SRC9 R8A7790_CLK_SCU_SRC8 R8A7790_CLK_SCU_SRC7 R8A7790_CLK_SCU_SRC6 R8A7790_CLK_SCU_SRC5
|
|
|
|
|
R8A7790_CLK_SCU_SRC4 R8A7790_CLK_SCU_SRC3 R8A7790_CLK_SCU_SRC2 R8A7790_CLK_SCU_SRC1 R8A7790_CLK_SCU_SRC0
|
|
|
|
|
>;
|
|
|
|
|
clock-output-names =
|
|
|
|
|
"ssi-all",
|
|
|
|
|
"ssi9", "ssi8", "ssi7", "ssi6", "ssi5",
|
|
|
|
|
"ssi4", "ssi3", "ssi2", "ssi1", "ssi0",
|
|
|
|
|
"scu-all",
|
|
|
|
|
"scu-dvc1", "scu-dvc0",
|
|
|
|
|
"scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5",
|
|
|
|
|
"scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0";
|
|
|
|
|
};
|
2013-12-11 14:05:14 +00:00
|
|
|
};
|
2014-02-10 10:47:29 +00:00
|
|
|
|
2014-02-25 10:30:13 +00:00
|
|
|
qspi: spi@e6b10000 {
|
2014-02-10 10:47:29 +00:00
|
|
|
compatible = "renesas,qspi-r8a7790", "renesas,qspi";
|
|
|
|
|
reg = <0 0xe6b10000 0 0x2c>;
|
|
|
|
|
interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clocks = <&mstp9_clks R8A7790_CLK_QSPI_MOD>;
|
2014-08-06 12:59:08 +00:00
|
|
|
dmas = <&dmac0 0x17>, <&dmac0 0x18>;
|
|
|
|
|
dma-names = "tx", "rx";
|
2014-02-10 10:47:29 +00:00
|
|
|
num-cs = <1>;
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
2014-02-25 10:30:15 +00:00
|
|
|
|
|
|
|
|
msiof0: spi@e6e20000 {
|
|
|
|
|
compatible = "renesas,msiof-r8a7790";
|
2015-04-04 16:54:31 +00:00
|
|
|
reg = <0 0xe6e20000 0 0x0064>;
|
2014-02-25 10:30:15 +00:00
|
|
|
interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clocks = <&mstp0_clks R8A7790_CLK_MSIOF0>;
|
2014-08-06 12:59:09 +00:00
|
|
|
dmas = <&dmac0 0x51>, <&dmac0 0x52>;
|
|
|
|
|
dma-names = "tx", "rx";
|
2014-02-25 10:30:15 +00:00
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
msiof1: spi@e6e10000 {
|
|
|
|
|
compatible = "renesas,msiof-r8a7790";
|
2015-04-04 16:54:31 +00:00
|
|
|
reg = <0 0xe6e10000 0 0x0064>;
|
2014-02-25 10:30:15 +00:00
|
|
|
interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clocks = <&mstp2_clks R8A7790_CLK_MSIOF1>;
|
2014-08-06 12:59:09 +00:00
|
|
|
dmas = <&dmac0 0x55>, <&dmac0 0x56>;
|
|
|
|
|
dma-names = "tx", "rx";
|
2014-02-25 10:30:15 +00:00
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
msiof2: spi@e6e00000 {
|
|
|
|
|
compatible = "renesas,msiof-r8a7790";
|
2015-04-04 16:54:31 +00:00
|
|
|
reg = <0 0xe6e00000 0 0x0064>;
|
2014-02-25 10:30:15 +00:00
|
|
|
interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clocks = <&mstp2_clks R8A7790_CLK_MSIOF2>;
|
2014-08-06 12:59:09 +00:00
|
|
|
dmas = <&dmac0 0x41>, <&dmac0 0x42>;
|
|
|
|
|
dma-names = "tx", "rx";
|
2014-02-25 10:30:15 +00:00
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
msiof3: spi@e6c90000 {
|
|
|
|
|
compatible = "renesas,msiof-r8a7790";
|
2015-04-04 16:54:31 +00:00
|
|
|
reg = <0 0xe6c90000 0 0x0064>;
|
2014-02-25 10:30:15 +00:00
|
|
|
interrupts = <0 159 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clocks = <&mstp2_clks R8A7790_CLK_MSIOF3>;
|
2014-08-06 12:59:09 +00:00
|
|
|
dmas = <&dmac0 0x45>, <&dmac0 0x46>;
|
|
|
|
|
dma-names = "tx", "rx";
|
2014-02-25 10:30:15 +00:00
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
2014-06-11 06:53:54 +00:00
|
|
|
|
2014-10-24 10:41:46 +00:00
|
|
|
xhci: usb@ee000000 {
|
|
|
|
|
compatible = "renesas,xhci-r8a7790";
|
|
|
|
|
reg = <0 0xee000000 0 0xc00>;
|
|
|
|
|
interrupts = <0 101 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clocks = <&mstp3_clks R8A7790_CLK_SSUSB>;
|
|
|
|
|
phys = <&usb2 1>;
|
|
|
|
|
phy-names = "usb";
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
2014-06-24 17:59:54 +00:00
|
|
|
pci0: pci@ee090000 {
|
|
|
|
|
compatible = "renesas,pci-r8a7790";
|
|
|
|
|
device_type = "pci";
|
|
|
|
|
clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
|
|
|
|
|
reg = <0 0xee090000 0 0xc00>,
|
|
|
|
|
<0 0xee080000 0 0x1100>;
|
|
|
|
|
interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
|
|
|
|
|
bus-range = <0 0>;
|
|
|
|
|
#address-cells = <3>;
|
|
|
|
|
#size-cells = <2>;
|
|
|
|
|
#interrupt-cells = <1>;
|
|
|
|
|
ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
|
|
|
|
|
interrupt-map-mask = <0xff00 0 0 0x7>;
|
|
|
|
|
interrupt-map = <0x0000 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
|
2014-06-30 09:49:53 +00:00
|
|
|
0x0800 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
|
|
|
|
|
0x1000 0 0 2 &gic 0 108 IRQ_TYPE_LEVEL_HIGH>;
|
2014-09-29 18:21:59 +00:00
|
|
|
|
|
|
|
|
usb@0,1 {
|
|
|
|
|
reg = <0x800 0 0 0 0>;
|
|
|
|
|
device_type = "pci";
|
|
|
|
|
phys = <&usb0 0>;
|
|
|
|
|
phy-names = "usb";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
usb@0,2 {
|
|
|
|
|
reg = <0x1000 0 0 0 0>;
|
|
|
|
|
device_type = "pci";
|
|
|
|
|
phys = <&usb0 0>;
|
|
|
|
|
phy-names = "usb";
|
|
|
|
|
};
|
2014-06-24 17:59:54 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pci1: pci@ee0b0000 {
|
|
|
|
|
compatible = "renesas,pci-r8a7790";
|
|
|
|
|
device_type = "pci";
|
|
|
|
|
clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
|
|
|
|
|
reg = <0 0xee0b0000 0 0xc00>,
|
|
|
|
|
<0 0xee0a0000 0 0x1100>;
|
|
|
|
|
interrupts = <0 112 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
|
|
|
|
|
bus-range = <1 1>;
|
|
|
|
|
#address-cells = <3>;
|
|
|
|
|
#size-cells = <2>;
|
|
|
|
|
#interrupt-cells = <1>;
|
|
|
|
|
ranges = <0x02000000 0 0xee0a0000 0 0xee0a0000 0 0x00010000>;
|
|
|
|
|
interrupt-map-mask = <0xff00 0 0 0x7>;
|
|
|
|
|
interrupt-map = <0x0000 0 0 1 &gic 0 112 IRQ_TYPE_LEVEL_HIGH
|
2014-06-30 09:49:53 +00:00
|
|
|
0x0800 0 0 1 &gic 0 112 IRQ_TYPE_LEVEL_HIGH
|
|
|
|
|
0x1000 0 0 2 &gic 0 112 IRQ_TYPE_LEVEL_HIGH>;
|
2014-06-24 17:59:54 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pci2: pci@ee0d0000 {
|
|
|
|
|
compatible = "renesas,pci-r8a7790";
|
|
|
|
|
device_type = "pci";
|
|
|
|
|
clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
|
|
|
|
|
reg = <0 0xee0d0000 0 0xc00>,
|
|
|
|
|
<0 0xee0c0000 0 0x1100>;
|
|
|
|
|
interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
|
|
|
|
|
bus-range = <2 2>;
|
|
|
|
|
#address-cells = <3>;
|
|
|
|
|
#size-cells = <2>;
|
|
|
|
|
#interrupt-cells = <1>;
|
|
|
|
|
ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
|
|
|
|
|
interrupt-map-mask = <0xff00 0 0 0x7>;
|
|
|
|
|
interrupt-map = <0x0000 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH
|
2014-06-30 09:49:53 +00:00
|
|
|
0x0800 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH
|
|
|
|
|
0x1000 0 0 2 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>;
|
2014-09-29 18:21:59 +00:00
|
|
|
|
|
|
|
|
usb@0,1 {
|
|
|
|
|
reg = <0x800 0 0 0 0>;
|
|
|
|
|
device_type = "pci";
|
|
|
|
|
phys = <&usb2 0>;
|
|
|
|
|
phy-names = "usb";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
usb@0,2 {
|
|
|
|
|
reg = <0x1000 0 0 0 0>;
|
|
|
|
|
device_type = "pci";
|
|
|
|
|
phys = <&usb2 0>;
|
|
|
|
|
phy-names = "usb";
|
|
|
|
|
};
|
2014-06-24 17:59:54 +00:00
|
|
|
};
|
|
|
|
|
|
2014-06-13 09:37:17 +00:00
|
|
|
pciec: pcie@fe000000 {
|
|
|
|
|
compatible = "renesas,pcie-r8a7790";
|
|
|
|
|
reg = <0 0xfe000000 0 0x80000>;
|
|
|
|
|
#address-cells = <3>;
|
|
|
|
|
#size-cells = <2>;
|
|
|
|
|
bus-range = <0x00 0xff>;
|
|
|
|
|
device_type = "pci";
|
|
|
|
|
ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
|
|
|
|
|
0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
|
|
|
|
|
0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
|
|
|
|
|
0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
|
|
|
|
|
/* Map all possible DDR as inbound ranges */
|
|
|
|
|
dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000
|
|
|
|
|
0x43000000 1 0x80000000 1 0x80000000 0 0x80000000>;
|
|
|
|
|
interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<0 117 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<0 118 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
#interrupt-cells = <1>;
|
|
|
|
|
interrupt-map-mask = <0 0 0 0>;
|
|
|
|
|
interrupt-map = <0 0 0 0 &gic 0 116 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clocks = <&mstp3_clks R8A7790_CLK_PCIEC>, <&pcie_bus_clk>;
|
|
|
|
|
clock-names = "pcie", "pcie_bus";
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
2014-10-29 14:30:51 +00:00
|
|
|
rcar_sound: rcar_sound@ec500000 {
|
2014-12-17 06:11:52 +00:00
|
|
|
/*
|
|
|
|
|
* #sound-dai-cells is required
|
|
|
|
|
*
|
|
|
|
|
* Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
|
|
|
|
|
* Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
|
|
|
|
|
*/
|
2015-01-06 20:01:52 +00:00
|
|
|
compatible = "renesas,rcar_sound-r8a7790", "renesas,rcar_sound-gen2";
|
2014-06-11 06:53:54 +00:00
|
|
|
reg = <0 0xec500000 0 0x1000>, /* SCU */
|
|
|
|
|
<0 0xec5a0000 0 0x100>, /* ADG */
|
|
|
|
|
<0 0xec540000 0 0x1000>, /* SSIU */
|
2015-03-10 01:39:39 +00:00
|
|
|
<0 0xec541000 0 0x1280>, /* SSI */
|
|
|
|
|
<0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/
|
|
|
|
|
reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
|
2015-03-10 01:39:01 +00:00
|
|
|
|
2014-06-11 06:53:54 +00:00
|
|
|
clocks = <&mstp10_clks R8A7790_CLK_SSI_ALL>,
|
|
|
|
|
<&mstp10_clks R8A7790_CLK_SSI9>, <&mstp10_clks R8A7790_CLK_SSI8>,
|
|
|
|
|
<&mstp10_clks R8A7790_CLK_SSI7>, <&mstp10_clks R8A7790_CLK_SSI6>,
|
|
|
|
|
<&mstp10_clks R8A7790_CLK_SSI5>, <&mstp10_clks R8A7790_CLK_SSI4>,
|
|
|
|
|
<&mstp10_clks R8A7790_CLK_SSI3>, <&mstp10_clks R8A7790_CLK_SSI2>,
|
|
|
|
|
<&mstp10_clks R8A7790_CLK_SSI1>, <&mstp10_clks R8A7790_CLK_SSI0>,
|
|
|
|
|
<&mstp10_clks R8A7790_CLK_SCU_SRC9>, <&mstp10_clks R8A7790_CLK_SCU_SRC8>,
|
|
|
|
|
<&mstp10_clks R8A7790_CLK_SCU_SRC7>, <&mstp10_clks R8A7790_CLK_SCU_SRC6>,
|
|
|
|
|
<&mstp10_clks R8A7790_CLK_SCU_SRC5>, <&mstp10_clks R8A7790_CLK_SCU_SRC4>,
|
|
|
|
|
<&mstp10_clks R8A7790_CLK_SCU_SRC3>, <&mstp10_clks R8A7790_CLK_SCU_SRC2>,
|
|
|
|
|
<&mstp10_clks R8A7790_CLK_SCU_SRC1>, <&mstp10_clks R8A7790_CLK_SCU_SRC0>,
|
2014-06-26 00:52:17 +00:00
|
|
|
<&mstp10_clks R8A7790_CLK_SCU_DVC0>, <&mstp10_clks R8A7790_CLK_SCU_DVC1>,
|
2014-06-11 06:53:54 +00:00
|
|
|
<&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>;
|
|
|
|
|
clock-names = "ssi-all",
|
|
|
|
|
"ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
|
|
|
|
|
"ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
|
|
|
|
|
"src.9", "src.8", "src.7", "src.6", "src.5",
|
|
|
|
|
"src.4", "src.3", "src.2", "src.1", "src.0",
|
2014-06-26 00:52:17 +00:00
|
|
|
"dvc.0", "dvc.1",
|
2014-06-11 06:53:54 +00:00
|
|
|
"clk_a", "clk_b", "clk_c", "clk_i";
|
|
|
|
|
|
|
|
|
|
status = "disabled";
|
|
|
|
|
|
2014-06-26 00:52:17 +00:00
|
|
|
rcar_sound,dvc {
|
2015-03-10 01:40:13 +00:00
|
|
|
dvc0: dvc@0 {
|
|
|
|
|
dmas = <&audma0 0xbc>;
|
|
|
|
|
dma-names = "tx";
|
|
|
|
|
};
|
|
|
|
|
dvc1: dvc@1 {
|
|
|
|
|
dmas = <&audma0 0xbe>;
|
|
|
|
|
dma-names = "tx";
|
|
|
|
|
};
|
2014-06-26 00:52:17 +00:00
|
|
|
};
|
|
|
|
|
|
2014-06-11 06:53:54 +00:00
|
|
|
rcar_sound,src {
|
2015-03-10 01:40:13 +00:00
|
|
|
src0: src@0 {
|
|
|
|
|
interrupts = <0 352 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
dmas = <&audma0 0x85>, <&audma1 0x9a>;
|
|
|
|
|
dma-names = "rx", "tx";
|
|
|
|
|
};
|
|
|
|
|
src1: src@1 {
|
|
|
|
|
interrupts = <0 353 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
dmas = <&audma0 0x87>, <&audma1 0x9c>;
|
|
|
|
|
dma-names = "rx", "tx";
|
|
|
|
|
};
|
|
|
|
|
src2: src@2 {
|
|
|
|
|
interrupts = <0 354 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
dmas = <&audma0 0x89>, <&audma1 0x9e>;
|
|
|
|
|
dma-names = "rx", "tx";
|
|
|
|
|
};
|
|
|
|
|
src3: src@3 {
|
|
|
|
|
interrupts = <0 355 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
dmas = <&audma0 0x8b>, <&audma1 0xa0>;
|
|
|
|
|
dma-names = "rx", "tx";
|
|
|
|
|
};
|
|
|
|
|
src4: src@4 {
|
|
|
|
|
interrupts = <0 356 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
dmas = <&audma0 0x8d>, <&audma1 0xb0>;
|
|
|
|
|
dma-names = "rx", "tx";
|
|
|
|
|
};
|
|
|
|
|
src5: src@5 {
|
|
|
|
|
interrupts = <0 357 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
dmas = <&audma0 0x8f>, <&audma1 0xb2>;
|
|
|
|
|
dma-names = "rx", "tx";
|
|
|
|
|
};
|
|
|
|
|
src6: src@6 {
|
|
|
|
|
interrupts = <0 358 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
dmas = <&audma0 0x91>, <&audma1 0xb4>;
|
|
|
|
|
dma-names = "rx", "tx";
|
|
|
|
|
};
|
|
|
|
|
src7: src@7 {
|
|
|
|
|
interrupts = <0 359 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
dmas = <&audma0 0x93>, <&audma1 0xb6>;
|
|
|
|
|
dma-names = "rx", "tx";
|
|
|
|
|
};
|
|
|
|
|
src8: src@8 {
|
|
|
|
|
interrupts = <0 360 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
dmas = <&audma0 0x95>, <&audma1 0xb8>;
|
|
|
|
|
dma-names = "rx", "tx";
|
|
|
|
|
};
|
|
|
|
|
src9: src@9 {
|
|
|
|
|
interrupts = <0 361 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
dmas = <&audma0 0x97>, <&audma1 0xba>;
|
|
|
|
|
dma-names = "rx", "tx";
|
|
|
|
|
};
|
2014-06-11 06:53:54 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
rcar_sound,ssi {
|
2015-03-10 01:40:13 +00:00
|
|
|
ssi0: ssi@0 {
|
|
|
|
|
interrupts = <0 370 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>;
|
|
|
|
|
dma-names = "rx", "tx", "rxu", "txu";
|
|
|
|
|
};
|
|
|
|
|
ssi1: ssi@1 {
|
|
|
|
|
interrupts = <0 371 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>;
|
|
|
|
|
dma-names = "rx", "tx", "rxu", "txu";
|
|
|
|
|
};
|
|
|
|
|
ssi2: ssi@2 {
|
|
|
|
|
interrupts = <0 372 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>;
|
|
|
|
|
dma-names = "rx", "tx", "rxu", "txu";
|
|
|
|
|
};
|
|
|
|
|
ssi3: ssi@3 {
|
|
|
|
|
interrupts = <0 373 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>;
|
|
|
|
|
dma-names = "rx", "tx", "rxu", "txu";
|
|
|
|
|
};
|
|
|
|
|
ssi4: ssi@4 {
|
|
|
|
|
interrupts = <0 374 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>;
|
|
|
|
|
dma-names = "rx", "tx", "rxu", "txu";
|
|
|
|
|
};
|
|
|
|
|
ssi5: ssi@5 {
|
|
|
|
|
interrupts = <0 375 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>;
|
|
|
|
|
dma-names = "rx", "tx", "rxu", "txu";
|
|
|
|
|
};
|
|
|
|
|
ssi6: ssi@6 {
|
|
|
|
|
interrupts = <0 376 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>;
|
|
|
|
|
dma-names = "rx", "tx", "rxu", "txu";
|
|
|
|
|
};
|
|
|
|
|
ssi7: ssi@7 {
|
|
|
|
|
interrupts = <0 377 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>;
|
|
|
|
|
dma-names = "rx", "tx", "rxu", "txu";
|
|
|
|
|
};
|
|
|
|
|
ssi8: ssi@8 {
|
|
|
|
|
interrupts = <0 378 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>;
|
|
|
|
|
dma-names = "rx", "tx", "rxu", "txu";
|
|
|
|
|
};
|
|
|
|
|
ssi9: ssi@9 {
|
|
|
|
|
interrupts = <0 379 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>;
|
|
|
|
|
dma-names = "rx", "tx", "rxu", "txu";
|
|
|
|
|
};
|
2014-06-11 06:53:54 +00:00
|
|
|
};
|
|
|
|
|
};
|
2015-01-27 09:13:23 +00:00
|
|
|
|
|
|
|
|
ipmmu_sy0: mmu@e6280000 {
|
|
|
|
|
compatible = "renesas,ipmmu-vmsa";
|
|
|
|
|
reg = <0 0xe6280000 0 0x1000>;
|
|
|
|
|
interrupts = <0 223 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<0 224 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
#iommu-cells = <1>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
ipmmu_sy1: mmu@e6290000 {
|
|
|
|
|
compatible = "renesas,ipmmu-vmsa";
|
|
|
|
|
reg = <0 0xe6290000 0 0x1000>;
|
|
|
|
|
interrupts = <0 225 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
#iommu-cells = <1>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
ipmmu_ds: mmu@e6740000 {
|
|
|
|
|
compatible = "renesas,ipmmu-vmsa";
|
|
|
|
|
reg = <0 0xe6740000 0 0x1000>;
|
|
|
|
|
interrupts = <0 198 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<0 199 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
#iommu-cells = <1>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
ipmmu_mp: mmu@ec680000 {
|
|
|
|
|
compatible = "renesas,ipmmu-vmsa";
|
|
|
|
|
reg = <0 0xec680000 0 0x1000>;
|
|
|
|
|
interrupts = <0 226 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
#iommu-cells = <1>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
ipmmu_mx: mmu@fe951000 {
|
|
|
|
|
compatible = "renesas,ipmmu-vmsa";
|
|
|
|
|
reg = <0 0xfe951000 0 0x1000>;
|
|
|
|
|
interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<0 221 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
#iommu-cells = <1>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
ipmmu_rt: mmu@ffc80000 {
|
|
|
|
|
compatible = "renesas,ipmmu-vmsa";
|
|
|
|
|
reg = <0 0xffc80000 0 0x1000>;
|
|
|
|
|
interrupts = <0 307 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
#iommu-cells = <1>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
2013-03-27 15:49:34 +00:00
|
|
|
};
|
