2005-11-10 14:26:52 +00:00
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/*
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2011-02-25 20:56:40 +00:00
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* OMAP2430 clock data
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2005-11-10 14:26:52 +00:00
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*
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2011-02-25 20:56:40 +00:00
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* Copyright (C) 2005-2009 Texas Instruments, Inc.
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* Copyright (C) 2004-2011 Nokia Corporation
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2005-11-10 14:26:52 +00:00
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*
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2011-02-25 20:56:40 +00:00
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* Contacts:
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* Richard Woodruff <r-woodruff2@ti.com>
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* Paul Walmsley
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2005-11-10 14:26:52 +00:00
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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2009-12-08 23:21:29 +00:00
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#include <linux/kernel.h>
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#include <linux/clk.h>
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OMAP2/3/4 clock: fix DPLL multiplier value errors; also copyrights, includes, documentation
The maximum DPLL multiplier (M) values for OMAP2xxx and OMAP3xxx are
one increment higher than they should be. See for example the
OMAP242x TRM Rev X Section 5.10.6 "Clock Generator Registers" and the
OMAP36xx TRM Rev C Table 3-202 "CM_CLKSEL1_PLL". Programming a 0 into
the DPLL's M register bitfield is valid for OMAP2/3 and indicates that
the DPLL should enter MN-bypass mode. Also, increase the minimum
multiplier (M) value for the DPLL rate rounding code from 1 to 2, to
ensure that it does not inadvertently put the DPLL into bypass.
Note that the register documentation in the OMAP2xxx and OMAP3xxx TRMs
does not make clear that the actual DPLL divider value (the "N") is
the content of the appropriate register bitfield for the N value,
_plus one_. (In other words, an N register bitfield of 0 indicates a
DPLL divider value of 1.) This is only clearly documented in the
OMAP4430 TRM, in, for example, OMAP4430 TRM Rev A Table 3-1167
"CM_CLKSEL_DPLL_USB".
While here, update copyrights, add kerneldoc for struct dpll_data,
drop the unused struct dpll_data.max_tolerance field, remove some
unnecessary #includes in DPLL-related code, and replace the #include
of <linux/module.h> with <linux/list.h>, which is what was really
needed. The OMAP4 clock autogenerator script has been updated
accordingly.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Benoît Cousson <b-cousson@ti.com>
Cc: Rajendra Nayak <rnayak@ti.com>
2010-02-23 05:09:12 +00:00
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#include <linux/list.h>
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2005-11-10 14:26:52 +00:00
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2012-02-24 18:34:35 +00:00
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#include <plat/hardware.h>
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2009-12-08 23:21:29 +00:00
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#include <plat/clkdev_omap.h>
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2008-03-18 08:35:15 +00:00
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2012-02-24 18:34:35 +00:00
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#include "iomap.h"
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2009-12-08 23:21:29 +00:00
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#include "clock.h"
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#include "clock2xxx.h"
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#include "opp2xxx.h"
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2010-12-21 22:30:55 +00:00
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#include "cm2xxx_3xxx.h"
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#include "prm2xxx_3xxx.h"
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2008-03-18 08:35:15 +00:00
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#include "prm-regbits-24xx.h"
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#include "cm-regbits-24xx.h"
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#include "sdrc.h"
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2010-10-08 17:40:20 +00:00
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#include "control.h"
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2008-03-18 08:35:15 +00:00
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OMAP2 clock: split OMAP2420, OMAP2430 clock data into their own files
In preparation for multi-OMAP2 kernels, split
mach-omap2/clock2xxx_data.c into mach-omap2/clock2420_data.c and
mach-omap2/clock2430_data.c. 2430 uses a different device space
physical memory layout than past or future OMAPs, and we use a
different virtual memory layout as well, which causes trouble for
architecture-level code/data that tries to support both. We tried
using offsets from the virtual base last year, but those patches never
made it upstream; so after some discussion with Tony about the best
all-around approach, we'll just grit our teeth and duplicate the
structures. The maintenance advantages of a single kernel config that
can compile and boot on OMAP2, 3, and 4 platforms are simply too
compelling.
This approach does have some nice benefits beyond multi-OMAP 2 kernel
support. The runtime size of OMAP2420-specific and OMAP2430-specific
kernels is smaller, since unused clocks for the other OMAP2 chip will
no longer be compiled in. (At some point we will mark the clock data
__initdata and allocate it during registration, which will eliminate
the runtime memory advantage.) It also makes the clock trees slightly
easier to read, since 2420-specific and 2430-specific clocks are no
longer mixed together.
This patch also splits 2430-specific clock code into its own file,
mach-omap2/clock2430.c, which is only compiled in for 2430 builds -
mostly for organizational clarity.
While here, fix a bug in the OMAP2430 clock tree: "emul_ck" was
incorrectly marked as being 2420-only, when actually it is present on
both OMAP2420 and OMAP2430.
Thanks to Tony for some good discussions about how to approach this
problem.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Richard Woodruff <r-woodruff2@ti.com>
2010-02-23 05:09:22 +00:00
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#define OMAP_CM_REGADDR OMAP2430_CM_REGADDR
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/*
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* 2430 clock tree.
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2005-11-10 14:26:52 +00:00
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*
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2011-02-25 20:56:40 +00:00
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* NOTE:In many cases here we are assigning a 'default' parent. In
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* many cases the parent is selectable. The set parent calls will
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* also switch sources.
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2005-11-10 14:26:52 +00:00
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*
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* Several sources are given initial rates which may be wrong, this will
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* be fixed up in the init func.
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*
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* Things are broadly separated below by clock domains. It is
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2011-02-25 20:56:40 +00:00
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* noteworthy that most peripherals have dependencies on multiple clock
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2005-11-10 14:26:52 +00:00
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* domains. Many get their interface clocks from the L4 domain, but get
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* functional clocks from fixed sources or other core domain derived
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* clocks.
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OMAP2 clock: split OMAP2420, OMAP2430 clock data into their own files
In preparation for multi-OMAP2 kernels, split
mach-omap2/clock2xxx_data.c into mach-omap2/clock2420_data.c and
mach-omap2/clock2430_data.c. 2430 uses a different device space
physical memory layout than past or future OMAPs, and we use a
different virtual memory layout as well, which causes trouble for
architecture-level code/data that tries to support both. We tried
using offsets from the virtual base last year, but those patches never
made it upstream; so after some discussion with Tony about the best
all-around approach, we'll just grit our teeth and duplicate the
structures. The maintenance advantages of a single kernel config that
can compile and boot on OMAP2, 3, and 4 platforms are simply too
compelling.
This approach does have some nice benefits beyond multi-OMAP 2 kernel
support. The runtime size of OMAP2420-specific and OMAP2430-specific
kernels is smaller, since unused clocks for the other OMAP2 chip will
no longer be compiled in. (At some point we will mark the clock data
__initdata and allocate it during registration, which will eliminate
the runtime memory advantage.) It also makes the clock trees slightly
easier to read, since 2420-specific and 2430-specific clocks are no
longer mixed together.
This patch also splits 2430-specific clock code into its own file,
mach-omap2/clock2430.c, which is only compiled in for 2430 builds -
mostly for organizational clarity.
While here, fix a bug in the OMAP2430 clock tree: "emul_ck" was
incorrectly marked as being 2420-only, when actually it is present on
both OMAP2420 and OMAP2430.
Thanks to Tony for some good discussions about how to approach this
problem.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Richard Woodruff <r-woodruff2@ti.com>
2010-02-23 05:09:22 +00:00
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*/
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2005-11-10 14:26:52 +00:00
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/* Base external input clocks */
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static struct clk func_32k_ck = {
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.name = "func_32k_ck",
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2008-11-04 16:35:03 +00:00
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.ops = &clkops_null,
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2011-02-16 22:38:38 +00:00
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.rate = 32768,
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2008-08-19 08:08:44 +00:00
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.clkdm_name = "wkup_clkdm",
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2005-11-10 14:26:52 +00:00
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};
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2008-03-18 13:47:55 +00:00
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OMAP2/3 GPTIMER: allow system tick GPTIMER to be changed in board-*.c files
Add a function omap2_gp_clockevent_set_gptimer() for board-*.c files
to use in .init_irq functions to configure the system tick GPTIMER.
Practical choices at this point are GPTIMER1 or GPTIMER12. Both of
these timers are in the WKUP powerdomain, and so are unaffected by
chip power management. GPTIMER1 can use sys_clk as a source, for
applications where a high-resolution timer is more important than
power management. GPTIMER12 has the special property that it has the
secure 32kHz oscillator as its source clock, which may be less prone
to glitches than the off-chip 32kHz oscillator. But on HS devices, it
may not be available for Linux use.
It appears that most boards are fine with GPTIMER1, but BeagleBoard
should use GPTIMER12 when using a 32KiHz timer source, due to hardware bugs
in revisions B4 and below. Modify board-omap3beagle.c to use GPTIMER12.
This patch originally used a Kbuild config option to select the GPTIMER,
but was changed to allow this to be specified in board-*.c files, per
Tony's request.
Kalle Vallo <kalle.valo@nokia.com> found a bug in an earlier version of
this patch - thanks Kalle.
Tested on Beagle rev B4 ES2.1, with and without CONFIG_OMAP_32K_TIMER, and
3430SDP.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Cc: Kalle Valo <kalle.valo@nokia.com>
2009-04-24 03:11:10 +00:00
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static struct clk secure_32k_ck = {
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.name = "secure_32k_ck",
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.ops = &clkops_null,
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.rate = 32768,
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.clkdm_name = "wkup_clkdm",
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};
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2005-11-10 14:26:52 +00:00
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/* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */
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static struct clk osc_ck = { /* (*12, *13, 19.2, *26, 38.4)MHz */
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.name = "osc_ck",
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2008-11-04 14:02:46 +00:00
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.ops = &clkops_oscck,
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2008-08-19 08:08:44 +00:00
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.clkdm_name = "wkup_clkdm",
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2008-03-18 13:47:55 +00:00
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.recalc = &omap2_osc_clk_recalc,
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2005-11-10 14:26:52 +00:00
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};
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2008-08-19 08:08:44 +00:00
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/* Without modem likely 12MHz, with modem likely 13MHz */
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2005-11-10 14:26:52 +00:00
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static struct clk sys_ck = { /* (*12, *13, 19.2, 26, 38.4)MHz */
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.name = "sys_ck", /* ~ ref_clk also */
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2008-11-04 16:35:03 +00:00
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.ops = &clkops_null,
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2005-11-10 14:26:52 +00:00
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.parent = &osc_ck,
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2008-08-19 08:08:44 +00:00
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.clkdm_name = "wkup_clkdm",
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2010-01-27 03:13:08 +00:00
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.recalc = &omap2xxx_sys_clk_recalc,
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2005-11-10 14:26:52 +00:00
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};
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2008-03-18 13:47:55 +00:00
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2005-11-10 14:26:52 +00:00
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static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */
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.name = "alt_ck",
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2008-11-04 16:35:03 +00:00
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.ops = &clkops_null,
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2005-11-10 14:26:52 +00:00
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.rate = 54000000,
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2008-08-19 08:08:44 +00:00
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.clkdm_name = "wkup_clkdm",
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2005-11-10 14:26:52 +00:00
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};
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2008-03-18 13:47:55 +00:00
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2010-10-08 17:40:18 +00:00
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/* Optional external clock input for McBSP CLKS */
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static struct clk mcbsp_clks = {
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.name = "mcbsp_clks",
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.ops = &clkops_null,
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};
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2005-11-10 14:26:52 +00:00
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/*
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* Analog domain root source clocks
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*/
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/* dpll_ck, is broken out in to special cases through clksel */
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2008-03-18 08:35:15 +00:00
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/* REVISIT: Rate changes on dpll_ck trigger a full set change. ...
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* deal with this
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*/
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ARM: OMAP2: Clock: New OMAP2/3 DPLL rate rounding algorithm
This patch adds a new rate rounding algorithm for DPLL clocks on the
OMAP2/3 architecture.
For a desired DPLL target rate, there may be several
multiplier/divider (M, N) values which will generate a sufficiently
close rate. Lower N values result in greater power economy. However,
lower N values can cause the difference between the rounded rate and
the target rate ("rate error") to be larger than it would be with a
higher N. This can cause downstream devices to run more slowly than
they otherwise would.
This DPLL rate rounding algorithm:
- attempts to find the lowest possible N (DPLL divider) to reach the
target_rate (since, according to Richard Woodruff <r-woodruff@ti.com>,
lower N values save more power than higher N values).
- allows developers to set an upper bound on the error between the
rounded rate and the desired target rate ("rate tolerance"), so an
appropriate balance between rate fidelity and power savings can be
set. This maximum rate error tolerance is set via
omap2_set_dpll_rate_tolerance().
- never returns a rounded rate higher than the target rate.
The rate rounding algorithm caches the last rounded M, N, and rate
computation to avoid rounding the rate twice for each clk_set_rate()
call. (This patch does not yet implement set_rate for DPLLs; that
follows in a future patch.)
The algorithm trades execution speed for rate accuracy. It will find
the (M, N) set that results in the least rate error, within a
specified rate tolerance. It does this by evaluating each divider
setting - on OMAP3, this involves 128 steps. Another approach to DPLL
rate rounding would be to bail out as soon as a valid rate is found
within the rate tolerance, which would trade rate accuracy for
execution speed. Alternate implementations welcome.
This code is not yet used by the OMAP24XX DPLL clock, since it
is currently defined as a composite clock, fusing the DPLL M,N and the
M2 output divider. This patch also renames the existing OMAP24xx DPLL
programming functions to highlight that they program both the DPLL and
the DPLL's output multiplier.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2008-07-03 09:24:46 +00:00
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static struct dpll_data dpll_dd = {
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2008-03-18 08:35:15 +00:00
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.mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
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.mult_mask = OMAP24XX_DPLL_MULT_MASK,
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.div1_mask = OMAP24XX_DPLL_DIV_MASK,
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[ARM] omap: add support for bypassing DPLLs
This roughly corresponds with OMAP commits: 7d06c48, 3241b19,
88b5d9b, 18a5500, 9c909ac, 5c6497b, 8b1f0bd, 2ac1da8.
For both OMAP2 and OMAP3, we note the reference and bypass clocks in
the DPLL data structure. Whenever we modify the DPLL rate, we first
ensure that both the reference and bypass clocks are enabled. Then,
we decide whether to use the reference and DPLL, or the bypass clock
if the desired rate is identical to the bypass rate, and program the
DPLL appropriately. Finally, we update the clock's parent, and then
disable the unused clocks.
This keeps the parents correctly balanced, and more importantly ensures
that the bypass clock is running whenever we reprogram the DPLL. This
is especially important because the procedure for reprogramming the DPLL
involves switching to the bypass clock.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-02-19 13:29:22 +00:00
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.clk_bypass = &sys_ck,
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.clk_ref = &sys_ck,
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.control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
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.enable_mask = OMAP24XX_EN_DPLL_MASK,
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OMAP2/3/4 clock: fix DPLL multiplier value errors; also copyrights, includes, documentation
The maximum DPLL multiplier (M) values for OMAP2xxx and OMAP3xxx are
one increment higher than they should be. See for example the
OMAP242x TRM Rev X Section 5.10.6 "Clock Generator Registers" and the
OMAP36xx TRM Rev C Table 3-202 "CM_CLKSEL1_PLL". Programming a 0 into
the DPLL's M register bitfield is valid for OMAP2/3 and indicates that
the DPLL should enter MN-bypass mode. Also, increase the minimum
multiplier (M) value for the DPLL rate rounding code from 1 to 2, to
ensure that it does not inadvertently put the DPLL into bypass.
Note that the register documentation in the OMAP2xxx and OMAP3xxx TRMs
does not make clear that the actual DPLL divider value (the "N") is
the content of the appropriate register bitfield for the N value,
_plus one_. (In other words, an N register bitfield of 0 indicates a
DPLL divider value of 1.) This is only clearly documented in the
OMAP4430 TRM, in, for example, OMAP4430 TRM Rev A Table 3-1167
"CM_CLKSEL_DPLL_USB".
While here, update copyrights, add kerneldoc for struct dpll_data,
drop the unused struct dpll_data.max_tolerance field, remove some
unnecessary #includes in DPLL-related code, and replace the #include
of <linux/module.h> with <linux/list.h>, which is what was really
needed. The OMAP4 clock autogenerator script has been updated
accordingly.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Benoît Cousson <b-cousson@ti.com>
Cc: Rajendra Nayak <rnayak@ti.com>
2010-02-23 05:09:12 +00:00
|
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.max_multiplier = 1023,
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2009-01-28 19:08:44 +00:00
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.min_divider = 1,
|
ARM: OMAP2: Clock: New OMAP2/3 DPLL rate rounding algorithm
This patch adds a new rate rounding algorithm for DPLL clocks on the
OMAP2/3 architecture.
For a desired DPLL target rate, there may be several
multiplier/divider (M, N) values which will generate a sufficiently
close rate. Lower N values result in greater power economy. However,
lower N values can cause the difference between the rounded rate and
the target rate ("rate error") to be larger than it would be with a
higher N. This can cause downstream devices to run more slowly than
they otherwise would.
This DPLL rate rounding algorithm:
- attempts to find the lowest possible N (DPLL divider) to reach the
target_rate (since, according to Richard Woodruff <r-woodruff@ti.com>,
lower N values save more power than higher N values).
- allows developers to set an upper bound on the error between the
rounded rate and the desired target rate ("rate tolerance"), so an
appropriate balance between rate fidelity and power savings can be
set. This maximum rate error tolerance is set via
omap2_set_dpll_rate_tolerance().
- never returns a rounded rate higher than the target rate.
The rate rounding algorithm caches the last rounded M, N, and rate
computation to avoid rounding the rate twice for each clk_set_rate()
call. (This patch does not yet implement set_rate for DPLLs; that
follows in a future patch.)
The algorithm trades execution speed for rate accuracy. It will find
the (M, N) set that results in the least rate error, within a
specified rate tolerance. It does this by evaluating each divider
setting - on OMAP3, this involves 128 steps. Another approach to DPLL
rate rounding would be to bail out as soon as a valid rate is found
within the rate tolerance, which would trade rate accuracy for
execution speed. Alternate implementations welcome.
This code is not yet used by the OMAP24XX DPLL clock, since it
is currently defined as a composite clock, fusing the DPLL M,N and the
M2 output divider. This patch also renames the existing OMAP24xx DPLL
programming functions to highlight that they program both the DPLL and
the DPLL's output multiplier.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2008-07-03 09:24:46 +00:00
|
|
|
.max_divider = 16,
|
2008-03-18 08:35:15 +00:00
|
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};
|
|
|
|
|
ARM: OMAP2: Clock: New OMAP2/3 DPLL rate rounding algorithm
This patch adds a new rate rounding algorithm for DPLL clocks on the
OMAP2/3 architecture.
For a desired DPLL target rate, there may be several
multiplier/divider (M, N) values which will generate a sufficiently
close rate. Lower N values result in greater power economy. However,
lower N values can cause the difference between the rounded rate and
the target rate ("rate error") to be larger than it would be with a
higher N. This can cause downstream devices to run more slowly than
they otherwise would.
This DPLL rate rounding algorithm:
- attempts to find the lowest possible N (DPLL divider) to reach the
target_rate (since, according to Richard Woodruff <r-woodruff@ti.com>,
lower N values save more power than higher N values).
- allows developers to set an upper bound on the error between the
rounded rate and the desired target rate ("rate tolerance"), so an
appropriate balance between rate fidelity and power savings can be
set. This maximum rate error tolerance is set via
omap2_set_dpll_rate_tolerance().
- never returns a rounded rate higher than the target rate.
The rate rounding algorithm caches the last rounded M, N, and rate
computation to avoid rounding the rate twice for each clk_set_rate()
call. (This patch does not yet implement set_rate for DPLLs; that
follows in a future patch.)
The algorithm trades execution speed for rate accuracy. It will find
the (M, N) set that results in the least rate error, within a
specified rate tolerance. It does this by evaluating each divider
setting - on OMAP3, this involves 128 steps. Another approach to DPLL
rate rounding would be to bail out as soon as a valid rate is found
within the rate tolerance, which would trade rate accuracy for
execution speed. Alternate implementations welcome.
This code is not yet used by the OMAP24XX DPLL clock, since it
is currently defined as a composite clock, fusing the DPLL M,N and the
M2 output divider. This patch also renames the existing OMAP24xx DPLL
programming functions to highlight that they program both the DPLL and
the DPLL's output multiplier.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2008-07-03 09:24:46 +00:00
|
|
|
/*
|
|
|
|
* XXX Cannot add round_rate here yet, as this is still a composite clock,
|
|
|
|
* not just a DPLL
|
|
|
|
*/
|
2005-11-10 14:26:52 +00:00
|
|
|
static struct clk dpll_ck = {
|
|
|
|
.name = "dpll_ck",
|
2011-02-25 22:49:53 +00:00
|
|
|
.ops = &clkops_omap2xxx_dpll_ops,
|
2005-11-10 14:26:52 +00:00
|
|
|
.parent = &sys_ck, /* Can be func_32k also */
|
2008-03-18 08:35:15 +00:00
|
|
|
.dpll_data = &dpll_dd,
|
2008-08-19 08:08:44 +00:00
|
|
|
.clkdm_name = "wkup_clkdm",
|
ARM: OMAP2: Clock: New OMAP2/3 DPLL rate rounding algorithm
This patch adds a new rate rounding algorithm for DPLL clocks on the
OMAP2/3 architecture.
For a desired DPLL target rate, there may be several
multiplier/divider (M, N) values which will generate a sufficiently
close rate. Lower N values result in greater power economy. However,
lower N values can cause the difference between the rounded rate and
the target rate ("rate error") to be larger than it would be with a
higher N. This can cause downstream devices to run more slowly than
they otherwise would.
This DPLL rate rounding algorithm:
- attempts to find the lowest possible N (DPLL divider) to reach the
target_rate (since, according to Richard Woodruff <r-woodruff@ti.com>,
lower N values save more power than higher N values).
- allows developers to set an upper bound on the error between the
rounded rate and the desired target rate ("rate tolerance"), so an
appropriate balance between rate fidelity and power savings can be
set. This maximum rate error tolerance is set via
omap2_set_dpll_rate_tolerance().
- never returns a rounded rate higher than the target rate.
The rate rounding algorithm caches the last rounded M, N, and rate
computation to avoid rounding the rate twice for each clk_set_rate()
call. (This patch does not yet implement set_rate for DPLLs; that
follows in a future patch.)
The algorithm trades execution speed for rate accuracy. It will find
the (M, N) set that results in the least rate error, within a
specified rate tolerance. It does this by evaluating each divider
setting - on OMAP3, this involves 128 steps. Another approach to DPLL
rate rounding would be to bail out as soon as a valid rate is found
within the rate tolerance, which would trade rate accuracy for
execution speed. Alternate implementations welcome.
This code is not yet used by the OMAP24XX DPLL clock, since it
is currently defined as a composite clock, fusing the DPLL M,N and the
M2 output divider. This patch also renames the existing OMAP24xx DPLL
programming functions to highlight that they program both the DPLL and
the DPLL's output multiplier.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2008-07-03 09:24:46 +00:00
|
|
|
.recalc = &omap2_dpllcore_recalc,
|
|
|
|
.set_rate = &omap2_reprogram_dpllcore,
|
2005-11-10 14:26:52 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk apll96_ck = {
|
|
|
|
.name = "apll96_ck",
|
2009-12-08 23:18:46 +00:00
|
|
|
.ops = &clkops_apll96,
|
2005-11-10 14:26:52 +00:00
|
|
|
.parent = &sys_ck,
|
|
|
|
.rate = 96000000,
|
2010-02-23 05:09:26 +00:00
|
|
|
.flags = ENABLE_ON_INIT,
|
2008-08-19 08:08:44 +00:00
|
|
|
.clkdm_name = "wkup_clkdm",
|
2008-03-18 08:35:15 +00:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
|
|
|
|
.enable_bit = OMAP24XX_EN_96M_PLL_SHIFT,
|
2005-11-10 14:26:52 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk apll54_ck = {
|
|
|
|
.name = "apll54_ck",
|
2009-12-08 23:18:46 +00:00
|
|
|
.ops = &clkops_apll54,
|
2005-11-10 14:26:52 +00:00
|
|
|
.parent = &sys_ck,
|
|
|
|
.rate = 54000000,
|
2010-02-23 05:09:26 +00:00
|
|
|
.flags = ENABLE_ON_INIT,
|
2008-08-19 08:08:44 +00:00
|
|
|
.clkdm_name = "wkup_clkdm",
|
2008-03-18 08:35:15 +00:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
|
|
|
|
.enable_bit = OMAP24XX_EN_54M_PLL_SHIFT,
|
2005-11-10 14:26:52 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
/*
|
|
|
|
* PRCM digital base sources
|
|
|
|
*/
|
2008-03-18 13:47:55 +00:00
|
|
|
|
|
|
|
/* func_54m_ck */
|
|
|
|
|
|
|
|
static const struct clksel_rate func_54m_apll54_rates[] = {
|
2010-05-19 00:40:24 +00:00
|
|
|
{ .div = 1, .val = 0, .flags = RATE_IN_24XX },
|
2008-03-18 13:47:55 +00:00
|
|
|
{ .div = 0 },
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct clksel_rate func_54m_alt_rates[] = {
|
2010-05-19 00:40:24 +00:00
|
|
|
{ .div = 1, .val = 1, .flags = RATE_IN_24XX },
|
2008-03-18 13:47:55 +00:00
|
|
|
{ .div = 0 },
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct clksel func_54m_clksel[] = {
|
|
|
|
{ .parent = &apll54_ck, .rates = func_54m_apll54_rates, },
|
|
|
|
{ .parent = &alt_ck, .rates = func_54m_alt_rates, },
|
|
|
|
{ .parent = NULL },
|
|
|
|
};
|
|
|
|
|
2005-11-10 14:26:52 +00:00
|
|
|
static struct clk func_54m_ck = {
|
|
|
|
.name = "func_54m_ck",
|
2008-11-04 16:48:35 +00:00
|
|
|
.ops = &clkops_null,
|
2005-11-10 14:26:52 +00:00
|
|
|
.parent = &apll54_ck, /* can also be alt_clk */
|
2008-08-19 08:08:44 +00:00
|
|
|
.clkdm_name = "wkup_clkdm",
|
2008-03-18 13:47:55 +00:00
|
|
|
.init = &omap2_init_clksel_parent,
|
|
|
|
.clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
|
2010-05-20 18:31:04 +00:00
|
|
|
.clksel_mask = OMAP24XX_54M_SOURCE_MASK,
|
2008-03-18 13:47:55 +00:00
|
|
|
.clksel = func_54m_clksel,
|
|
|
|
.recalc = &omap2_clksel_recalc,
|
2005-11-10 14:26:52 +00:00
|
|
|
};
|
2008-03-18 13:47:55 +00:00
|
|
|
|
2005-11-10 14:26:52 +00:00
|
|
|
static struct clk core_ck = {
|
|
|
|
.name = "core_ck",
|
2008-11-04 16:35:03 +00:00
|
|
|
.ops = &clkops_null,
|
2005-11-10 14:26:52 +00:00
|
|
|
.parent = &dpll_ck, /* can also be 32k */
|
2008-08-19 08:08:44 +00:00
|
|
|
.clkdm_name = "wkup_clkdm",
|
2008-03-18 08:35:15 +00:00
|
|
|
.recalc = &followparent_recalc,
|
2005-11-10 14:26:52 +00:00
|
|
|
};
|
2008-03-18 13:47:55 +00:00
|
|
|
|
|
|
|
/* func_96m_ck */
|
|
|
|
static const struct clksel_rate func_96m_apll96_rates[] = {
|
2010-05-19 00:40:24 +00:00
|
|
|
{ .div = 1, .val = 0, .flags = RATE_IN_24XX },
|
2008-03-18 13:47:55 +00:00
|
|
|
{ .div = 0 },
|
2005-11-10 14:26:52 +00:00
|
|
|
};
|
|
|
|
|
2008-03-18 13:47:55 +00:00
|
|
|
static const struct clksel_rate func_96m_alt_rates[] = {
|
2010-05-19 00:40:24 +00:00
|
|
|
{ .div = 1, .val = 1, .flags = RATE_IN_243X },
|
2008-03-18 13:47:55 +00:00
|
|
|
{ .div = 0 },
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct clksel func_96m_clksel[] = {
|
|
|
|
{ .parent = &apll96_ck, .rates = func_96m_apll96_rates },
|
|
|
|
{ .parent = &alt_ck, .rates = func_96m_alt_rates },
|
|
|
|
{ .parent = NULL }
|
|
|
|
};
|
|
|
|
|
2005-11-10 14:26:52 +00:00
|
|
|
static struct clk func_96m_ck = {
|
|
|
|
.name = "func_96m_ck",
|
2008-11-04 16:48:35 +00:00
|
|
|
.ops = &clkops_null,
|
2005-11-10 14:26:52 +00:00
|
|
|
.parent = &apll96_ck,
|
2008-08-19 08:08:44 +00:00
|
|
|
.clkdm_name = "wkup_clkdm",
|
2008-03-18 13:47:55 +00:00
|
|
|
.init = &omap2_init_clksel_parent,
|
|
|
|
.clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
|
2010-05-20 18:31:04 +00:00
|
|
|
.clksel_mask = OMAP2430_96M_SOURCE_MASK,
|
2008-03-18 13:47:55 +00:00
|
|
|
.clksel = func_96m_clksel,
|
|
|
|
.recalc = &omap2_clksel_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* func_48m_ck */
|
|
|
|
|
|
|
|
static const struct clksel_rate func_48m_apll96_rates[] = {
|
2010-05-19 00:40:24 +00:00
|
|
|
{ .div = 2, .val = 0, .flags = RATE_IN_24XX },
|
2008-03-18 13:47:55 +00:00
|
|
|
{ .div = 0 },
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct clksel_rate func_48m_alt_rates[] = {
|
2010-05-19 00:40:24 +00:00
|
|
|
{ .div = 1, .val = 1, .flags = RATE_IN_24XX },
|
2008-03-18 13:47:55 +00:00
|
|
|
{ .div = 0 },
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct clksel func_48m_clksel[] = {
|
|
|
|
{ .parent = &apll96_ck, .rates = func_48m_apll96_rates },
|
|
|
|
{ .parent = &alt_ck, .rates = func_48m_alt_rates },
|
|
|
|
{ .parent = NULL }
|
2005-11-10 14:26:52 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk func_48m_ck = {
|
|
|
|
.name = "func_48m_ck",
|
2008-11-04 16:48:35 +00:00
|
|
|
.ops = &clkops_null,
|
2005-11-10 14:26:52 +00:00
|
|
|
.parent = &apll96_ck, /* 96M or Alt */
|
2008-08-19 08:08:44 +00:00
|
|
|
.clkdm_name = "wkup_clkdm",
|
2008-03-18 13:47:55 +00:00
|
|
|
.init = &omap2_init_clksel_parent,
|
|
|
|
.clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
|
2010-05-20 18:31:04 +00:00
|
|
|
.clksel_mask = OMAP24XX_48M_SOURCE_MASK,
|
2008-03-18 13:47:55 +00:00
|
|
|
.clksel = func_48m_clksel,
|
|
|
|
.recalc = &omap2_clksel_recalc,
|
|
|
|
.round_rate = &omap2_clksel_round_rate,
|
|
|
|
.set_rate = &omap2_clksel_set_rate
|
2005-11-10 14:26:52 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk func_12m_ck = {
|
|
|
|
.name = "func_12m_ck",
|
2008-11-04 16:48:35 +00:00
|
|
|
.ops = &clkops_null,
|
2005-11-10 14:26:52 +00:00
|
|
|
.parent = &func_48m_ck,
|
2008-03-18 13:47:55 +00:00
|
|
|
.fixed_div = 4,
|
2008-08-19 08:08:44 +00:00
|
|
|
.clkdm_name = "wkup_clkdm",
|
2010-01-27 03:12:57 +00:00
|
|
|
.recalc = &omap_fixed_divisor_recalc,
|
2005-11-10 14:26:52 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
/* Secure timer, only available in secure mode */
|
|
|
|
static struct clk wdt1_osc_ck = {
|
|
|
|
.name = "ck_wdt1_osc",
|
2008-11-04 16:35:03 +00:00
|
|
|
.ops = &clkops_null, /* RMK: missing? */
|
2005-11-10 14:26:52 +00:00
|
|
|
.parent = &osc_ck,
|
2008-03-18 13:47:55 +00:00
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
/*
|
|
|
|
* The common_clkout* clksel_rate structs are common to
|
|
|
|
* sys_clkout, sys_clkout_src, sys_clkout2, and sys_clkout2_src.
|
|
|
|
* sys_clkout2_* are 2420-only, so the
|
|
|
|
* clksel_rate flags fields are inaccurate for those clocks. This is
|
|
|
|
* harmless since access to those clocks are gated by the struct clk
|
|
|
|
* flags fields, which mark them as 2420-only.
|
|
|
|
*/
|
|
|
|
static const struct clksel_rate common_clkout_src_core_rates[] = {
|
2010-05-19 00:40:24 +00:00
|
|
|
{ .div = 1, .val = 0, .flags = RATE_IN_24XX },
|
2008-03-18 13:47:55 +00:00
|
|
|
{ .div = 0 }
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct clksel_rate common_clkout_src_sys_rates[] = {
|
2010-05-19 00:40:24 +00:00
|
|
|
{ .div = 1, .val = 1, .flags = RATE_IN_24XX },
|
2008-03-18 13:47:55 +00:00
|
|
|
{ .div = 0 }
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct clksel_rate common_clkout_src_96m_rates[] = {
|
2010-05-19 00:40:24 +00:00
|
|
|
{ .div = 1, .val = 2, .flags = RATE_IN_24XX },
|
2008-03-18 13:47:55 +00:00
|
|
|
{ .div = 0 }
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct clksel_rate common_clkout_src_54m_rates[] = {
|
2010-05-19 00:40:24 +00:00
|
|
|
{ .div = 1, .val = 3, .flags = RATE_IN_24XX },
|
2008-03-18 13:47:55 +00:00
|
|
|
{ .div = 0 }
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct clksel common_clkout_src_clksel[] = {
|
|
|
|
{ .parent = &core_ck, .rates = common_clkout_src_core_rates },
|
|
|
|
{ .parent = &sys_ck, .rates = common_clkout_src_sys_rates },
|
|
|
|
{ .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates },
|
|
|
|
{ .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates },
|
|
|
|
{ .parent = NULL }
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk sys_clkout_src = {
|
|
|
|
.name = "sys_clkout_src",
|
[ARM] omap: don't use clkops_omap2_dflt_wait for non-ICLK/FCLK clocks
The original code in omap2_clk_wait_ready() used to check the low 8
bits to determine whether they were within the FCLKEN or ICLKEN
registers. Specifically, the test is satisfied when these offsets
are used:
CM_FCLKEN, CM_FCLKEN1, CM_CLKEN, OMAP24XX_CM_FCLKEN2, CM_ICLKEN,
CM_ICLKEN1, CM_ICLKEN2, CM_ICLKEN3, OMAP24XX_CM_ICLKEN4
OMAP3430_CM_CLKEN_PLL, OMAP3430ES2_CM_CLKEN2
If one of these offsets isn't used, omap2_clk_wait_ready() merely
returns without doing anything. So we should use the non-wait clkops
version instead and eliminate that conditional.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-11-04 21:24:00 +00:00
|
|
|
.ops = &clkops_omap2_dflt,
|
2008-03-18 13:47:55 +00:00
|
|
|
.parent = &func_54m_ck,
|
2008-08-19 08:08:44 +00:00
|
|
|
.clkdm_name = "wkup_clkdm",
|
OMAP2 clock: split OMAP2420, OMAP2430 clock data into their own files
In preparation for multi-OMAP2 kernels, split
mach-omap2/clock2xxx_data.c into mach-omap2/clock2420_data.c and
mach-omap2/clock2430_data.c. 2430 uses a different device space
physical memory layout than past or future OMAPs, and we use a
different virtual memory layout as well, which causes trouble for
architecture-level code/data that tries to support both. We tried
using offsets from the virtual base last year, but those patches never
made it upstream; so after some discussion with Tony about the best
all-around approach, we'll just grit our teeth and duplicate the
structures. The maintenance advantages of a single kernel config that
can compile and boot on OMAP2, 3, and 4 platforms are simply too
compelling.
This approach does have some nice benefits beyond multi-OMAP 2 kernel
support. The runtime size of OMAP2420-specific and OMAP2430-specific
kernels is smaller, since unused clocks for the other OMAP2 chip will
no longer be compiled in. (At some point we will mark the clock data
__initdata and allocate it during registration, which will eliminate
the runtime memory advantage.) It also makes the clock trees slightly
easier to read, since 2420-specific and 2430-specific clocks are no
longer mixed together.
This patch also splits 2430-specific clock code into its own file,
mach-omap2/clock2430.c, which is only compiled in for 2430 builds -
mostly for organizational clarity.
While here, fix a bug in the OMAP2430 clock tree: "emul_ck" was
incorrectly marked as being 2420-only, when actually it is present on
both OMAP2420 and OMAP2430.
Thanks to Tony for some good discussions about how to approach this
problem.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Richard Woodruff <r-woodruff2@ti.com>
2010-02-23 05:09:22 +00:00
|
|
|
.enable_reg = OMAP2430_PRCM_CLKOUT_CTRL,
|
2008-03-18 13:47:55 +00:00
|
|
|
.enable_bit = OMAP24XX_CLKOUT_EN_SHIFT,
|
|
|
|
.init = &omap2_init_clksel_parent,
|
OMAP2 clock: split OMAP2420, OMAP2430 clock data into their own files
In preparation for multi-OMAP2 kernels, split
mach-omap2/clock2xxx_data.c into mach-omap2/clock2420_data.c and
mach-omap2/clock2430_data.c. 2430 uses a different device space
physical memory layout than past or future OMAPs, and we use a
different virtual memory layout as well, which causes trouble for
architecture-level code/data that tries to support both. We tried
using offsets from the virtual base last year, but those patches never
made it upstream; so after some discussion with Tony about the best
all-around approach, we'll just grit our teeth and duplicate the
structures. The maintenance advantages of a single kernel config that
can compile and boot on OMAP2, 3, and 4 platforms are simply too
compelling.
This approach does have some nice benefits beyond multi-OMAP 2 kernel
support. The runtime size of OMAP2420-specific and OMAP2430-specific
kernels is smaller, since unused clocks for the other OMAP2 chip will
no longer be compiled in. (At some point we will mark the clock data
__initdata and allocate it during registration, which will eliminate
the runtime memory advantage.) It also makes the clock trees slightly
easier to read, since 2420-specific and 2430-specific clocks are no
longer mixed together.
This patch also splits 2430-specific clock code into its own file,
mach-omap2/clock2430.c, which is only compiled in for 2430 builds -
mostly for organizational clarity.
While here, fix a bug in the OMAP2430 clock tree: "emul_ck" was
incorrectly marked as being 2420-only, when actually it is present on
both OMAP2420 and OMAP2430.
Thanks to Tony for some good discussions about how to approach this
problem.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Richard Woodruff <r-woodruff2@ti.com>
2010-02-23 05:09:22 +00:00
|
|
|
.clksel_reg = OMAP2430_PRCM_CLKOUT_CTRL,
|
2008-03-18 13:47:55 +00:00
|
|
|
.clksel_mask = OMAP24XX_CLKOUT_SOURCE_MASK,
|
|
|
|
.clksel = common_clkout_src_clksel,
|
|
|
|
.recalc = &omap2_clksel_recalc,
|
|
|
|
.round_rate = &omap2_clksel_round_rate,
|
|
|
|
.set_rate = &omap2_clksel_set_rate
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct clksel_rate common_clkout_rates[] = {
|
2010-05-19 00:40:24 +00:00
|
|
|
{ .div = 1, .val = 0, .flags = RATE_IN_24XX },
|
2008-03-18 13:47:55 +00:00
|
|
|
{ .div = 2, .val = 1, .flags = RATE_IN_24XX },
|
|
|
|
{ .div = 4, .val = 2, .flags = RATE_IN_24XX },
|
|
|
|
{ .div = 8, .val = 3, .flags = RATE_IN_24XX },
|
|
|
|
{ .div = 16, .val = 4, .flags = RATE_IN_24XX },
|
|
|
|
{ .div = 0 },
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct clksel sys_clkout_clksel[] = {
|
|
|
|
{ .parent = &sys_clkout_src, .rates = common_clkout_rates },
|
|
|
|
{ .parent = NULL }
|
2005-11-10 14:26:52 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk sys_clkout = {
|
|
|
|
.name = "sys_clkout",
|
2008-11-04 16:48:35 +00:00
|
|
|
.ops = &clkops_null,
|
2008-03-18 13:47:55 +00:00
|
|
|
.parent = &sys_clkout_src,
|
2008-08-19 08:08:44 +00:00
|
|
|
.clkdm_name = "wkup_clkdm",
|
OMAP2 clock: split OMAP2420, OMAP2430 clock data into their own files
In preparation for multi-OMAP2 kernels, split
mach-omap2/clock2xxx_data.c into mach-omap2/clock2420_data.c and
mach-omap2/clock2430_data.c. 2430 uses a different device space
physical memory layout than past or future OMAPs, and we use a
different virtual memory layout as well, which causes trouble for
architecture-level code/data that tries to support both. We tried
using offsets from the virtual base last year, but those patches never
made it upstream; so after some discussion with Tony about the best
all-around approach, we'll just grit our teeth and duplicate the
structures. The maintenance advantages of a single kernel config that
can compile and boot on OMAP2, 3, and 4 platforms are simply too
compelling.
This approach does have some nice benefits beyond multi-OMAP 2 kernel
support. The runtime size of OMAP2420-specific and OMAP2430-specific
kernels is smaller, since unused clocks for the other OMAP2 chip will
no longer be compiled in. (At some point we will mark the clock data
__initdata and allocate it during registration, which will eliminate
the runtime memory advantage.) It also makes the clock trees slightly
easier to read, since 2420-specific and 2430-specific clocks are no
longer mixed together.
This patch also splits 2430-specific clock code into its own file,
mach-omap2/clock2430.c, which is only compiled in for 2430 builds -
mostly for organizational clarity.
While here, fix a bug in the OMAP2430 clock tree: "emul_ck" was
incorrectly marked as being 2420-only, when actually it is present on
both OMAP2420 and OMAP2430.
Thanks to Tony for some good discussions about how to approach this
problem.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Richard Woodruff <r-woodruff2@ti.com>
2010-02-23 05:09:22 +00:00
|
|
|
.clksel_reg = OMAP2430_PRCM_CLKOUT_CTRL,
|
2008-03-18 13:47:55 +00:00
|
|
|
.clksel_mask = OMAP24XX_CLKOUT_DIV_MASK,
|
|
|
|
.clksel = sys_clkout_clksel,
|
|
|
|
.recalc = &omap2_clksel_recalc,
|
|
|
|
.round_rate = &omap2_clksel_round_rate,
|
|
|
|
.set_rate = &omap2_clksel_set_rate
|
|
|
|
};
|
|
|
|
|
2006-04-02 16:46:20 +00:00
|
|
|
static struct clk emul_ck = {
|
|
|
|
.name = "emul_ck",
|
[ARM] omap: don't use clkops_omap2_dflt_wait for non-ICLK/FCLK clocks
The original code in omap2_clk_wait_ready() used to check the low 8
bits to determine whether they were within the FCLKEN or ICLKEN
registers. Specifically, the test is satisfied when these offsets
are used:
CM_FCLKEN, CM_FCLKEN1, CM_CLKEN, OMAP24XX_CM_FCLKEN2, CM_ICLKEN,
CM_ICLKEN1, CM_ICLKEN2, CM_ICLKEN3, OMAP24XX_CM_ICLKEN4
OMAP3430_CM_CLKEN_PLL, OMAP3430ES2_CM_CLKEN2
If one of these offsets isn't used, omap2_clk_wait_ready() merely
returns without doing anything. So we should use the non-wait clkops
version instead and eliminate that conditional.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-11-04 21:24:00 +00:00
|
|
|
.ops = &clkops_omap2_dflt,
|
2006-04-02 16:46:20 +00:00
|
|
|
.parent = &func_54m_ck,
|
2008-08-19 08:08:44 +00:00
|
|
|
.clkdm_name = "wkup_clkdm",
|
OMAP2 clock: split OMAP2420, OMAP2430 clock data into their own files
In preparation for multi-OMAP2 kernels, split
mach-omap2/clock2xxx_data.c into mach-omap2/clock2420_data.c and
mach-omap2/clock2430_data.c. 2430 uses a different device space
physical memory layout than past or future OMAPs, and we use a
different virtual memory layout as well, which causes trouble for
architecture-level code/data that tries to support both. We tried
using offsets from the virtual base last year, but those patches never
made it upstream; so after some discussion with Tony about the best
all-around approach, we'll just grit our teeth and duplicate the
structures. The maintenance advantages of a single kernel config that
can compile and boot on OMAP2, 3, and 4 platforms are simply too
compelling.
This approach does have some nice benefits beyond multi-OMAP 2 kernel
support. The runtime size of OMAP2420-specific and OMAP2430-specific
kernels is smaller, since unused clocks for the other OMAP2 chip will
no longer be compiled in. (At some point we will mark the clock data
__initdata and allocate it during registration, which will eliminate
the runtime memory advantage.) It also makes the clock trees slightly
easier to read, since 2420-specific and 2430-specific clocks are no
longer mixed together.
This patch also splits 2430-specific clock code into its own file,
mach-omap2/clock2430.c, which is only compiled in for 2430 builds -
mostly for organizational clarity.
While here, fix a bug in the OMAP2430 clock tree: "emul_ck" was
incorrectly marked as being 2420-only, when actually it is present on
both OMAP2420 and OMAP2430.
Thanks to Tony for some good discussions about how to approach this
problem.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Richard Woodruff <r-woodruff2@ti.com>
2010-02-23 05:09:22 +00:00
|
|
|
.enable_reg = OMAP2430_PRCM_CLKEMUL_CTRL,
|
2008-03-18 13:47:55 +00:00
|
|
|
.enable_bit = OMAP24XX_EMULATION_EN_SHIFT,
|
|
|
|
.recalc = &followparent_recalc,
|
2006-04-02 16:46:20 +00:00
|
|
|
|
|
|
|
};
|
2008-03-18 13:47:55 +00:00
|
|
|
|
2005-11-10 14:26:52 +00:00
|
|
|
/*
|
|
|
|
* MPU clock domain
|
|
|
|
* Clocks:
|
|
|
|
* MPU_FCLK, MPU_ICLK
|
|
|
|
* INT_M_FCLK, INT_M_I_CLK
|
|
|
|
*
|
|
|
|
* - Individual clocks are hardware managed.
|
|
|
|
* - Base divider comes from: CM_CLKSEL_MPU
|
|
|
|
*
|
|
|
|
*/
|
2008-03-18 13:47:55 +00:00
|
|
|
static const struct clksel_rate mpu_core_rates[] = {
|
2010-05-19 00:40:24 +00:00
|
|
|
{ .div = 1, .val = 1, .flags = RATE_IN_24XX },
|
2008-03-18 13:47:55 +00:00
|
|
|
{ .div = 2, .val = 2, .flags = RATE_IN_24XX },
|
|
|
|
{ .div = 0 },
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct clksel mpu_clksel[] = {
|
|
|
|
{ .parent = &core_ck, .rates = mpu_core_rates },
|
|
|
|
{ .parent = NULL }
|
|
|
|
};
|
|
|
|
|
2005-11-10 14:26:52 +00:00
|
|
|
static struct clk mpu_ck = { /* Control cpu */
|
|
|
|
.name = "mpu_ck",
|
2008-11-04 16:35:03 +00:00
|
|
|
.ops = &clkops_null,
|
2005-11-10 14:26:52 +00:00
|
|
|
.parent = &core_ck,
|
2008-08-19 08:08:44 +00:00
|
|
|
.clkdm_name = "mpu_clkdm",
|
2008-03-18 08:35:15 +00:00
|
|
|
.init = &omap2_init_clksel_parent,
|
|
|
|
.clksel_reg = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL),
|
|
|
|
.clksel_mask = OMAP24XX_CLKSEL_MPU_MASK,
|
2008-03-18 13:47:55 +00:00
|
|
|
.clksel = mpu_clksel,
|
2005-11-10 14:26:52 +00:00
|
|
|
.recalc = &omap2_clksel_recalc,
|
|
|
|
};
|
2008-03-18 13:47:55 +00:00
|
|
|
|
2005-11-10 14:26:52 +00:00
|
|
|
/*
|
OMAP2 clock: split OMAP2420, OMAP2430 clock data into their own files
In preparation for multi-OMAP2 kernels, split
mach-omap2/clock2xxx_data.c into mach-omap2/clock2420_data.c and
mach-omap2/clock2430_data.c. 2430 uses a different device space
physical memory layout than past or future OMAPs, and we use a
different virtual memory layout as well, which causes trouble for
architecture-level code/data that tries to support both. We tried
using offsets from the virtual base last year, but those patches never
made it upstream; so after some discussion with Tony about the best
all-around approach, we'll just grit our teeth and duplicate the
structures. The maintenance advantages of a single kernel config that
can compile and boot on OMAP2, 3, and 4 platforms are simply too
compelling.
This approach does have some nice benefits beyond multi-OMAP 2 kernel
support. The runtime size of OMAP2420-specific and OMAP2430-specific
kernels is smaller, since unused clocks for the other OMAP2 chip will
no longer be compiled in. (At some point we will mark the clock data
__initdata and allocate it during registration, which will eliminate
the runtime memory advantage.) It also makes the clock trees slightly
easier to read, since 2420-specific and 2430-specific clocks are no
longer mixed together.
This patch also splits 2430-specific clock code into its own file,
mach-omap2/clock2430.c, which is only compiled in for 2430 builds -
mostly for organizational clarity.
While here, fix a bug in the OMAP2430 clock tree: "emul_ck" was
incorrectly marked as being 2420-only, when actually it is present on
both OMAP2420 and OMAP2430.
Thanks to Tony for some good discussions about how to approach this
problem.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Richard Woodruff <r-woodruff2@ti.com>
2010-02-23 05:09:22 +00:00
|
|
|
* DSP (2430-IVA2.1) clock domain
|
2005-11-10 14:26:52 +00:00
|
|
|
* Clocks:
|
2008-03-18 13:47:55 +00:00
|
|
|
* 2430: IVA2.1_FCLK (really just DSP_FCLK), IVA2.1_ICLK
|
|
|
|
*
|
|
|
|
* Won't be too specific here. The core clock comes into this block
|
|
|
|
* it is divided then tee'ed. One branch goes directly to xyz enable
|
|
|
|
* controls. The other branch gets further divided by 2 then possibly
|
|
|
|
* routed into a synchronizer and out of clocks abc.
|
2005-11-10 14:26:52 +00:00
|
|
|
*/
|
2008-03-18 13:47:55 +00:00
|
|
|
static const struct clksel_rate dsp_fck_core_rates[] = {
|
2010-05-19 00:40:24 +00:00
|
|
|
{ .div = 1, .val = 1, .flags = RATE_IN_24XX },
|
2008-03-18 13:47:55 +00:00
|
|
|
{ .div = 2, .val = 2, .flags = RATE_IN_24XX },
|
|
|
|
{ .div = 3, .val = 3, .flags = RATE_IN_24XX },
|
|
|
|
{ .div = 4, .val = 4, .flags = RATE_IN_24XX },
|
|
|
|
{ .div = 0 },
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct clksel dsp_fck_clksel[] = {
|
|
|
|
{ .parent = &core_ck, .rates = dsp_fck_core_rates },
|
|
|
|
{ .parent = NULL }
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk dsp_fck = {
|
|
|
|
.name = "dsp_fck",
|
2008-11-04 17:59:52 +00:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2005-11-10 14:26:52 +00:00
|
|
|
.parent = &core_ck,
|
2008-08-19 08:08:44 +00:00
|
|
|
.clkdm_name = "dsp_clkdm",
|
2008-03-18 13:47:55 +00:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
|
|
|
|
.enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
|
|
|
|
.clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
|
|
|
|
.clksel_mask = OMAP24XX_CLKSEL_DSP_MASK,
|
|
|
|
.clksel = dsp_fck_clksel,
|
2005-11-10 14:26:52 +00:00
|
|
|
.recalc = &omap2_clksel_recalc,
|
|
|
|
};
|
|
|
|
|
2011-02-25 22:52:04 +00:00
|
|
|
static const struct clksel dsp_ick_clksel[] = {
|
|
|
|
{ .parent = &dsp_fck, .rates = dsp_ick_rates },
|
2008-03-18 13:47:55 +00:00
|
|
|
{ .parent = NULL }
|
2005-11-10 14:26:52 +00:00
|
|
|
};
|
|
|
|
|
2008-03-18 13:47:55 +00:00
|
|
|
/* 2430 only - EN_DSP controls both dsp fclk and iclk on 2430 */
|
|
|
|
static struct clk iva2_1_ick = {
|
|
|
|
.name = "iva2_1_ick",
|
2008-11-04 17:59:52 +00:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2011-02-25 22:52:04 +00:00
|
|
|
.parent = &dsp_fck,
|
|
|
|
.clkdm_name = "dsp_clkdm",
|
2008-03-18 13:47:55 +00:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
|
|
|
|
.enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
|
2011-02-25 22:52:04 +00:00
|
|
|
.clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
|
|
|
|
.clksel_mask = OMAP24XX_CLKSEL_DSP_IF_MASK,
|
|
|
|
.clksel = dsp_ick_clksel,
|
|
|
|
.recalc = &omap2_clksel_recalc,
|
2005-11-10 14:26:52 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
/*
|
|
|
|
* L3 clock domain
|
|
|
|
* L3 clocks are used for both interface and functional clocks to
|
|
|
|
* multiple entities. Some of these clocks are completely managed
|
|
|
|
* by hardware, and some others allow software control. Hardware
|
|
|
|
* managed ones general are based on directly CLK_REQ signals and
|
|
|
|
* various auto idle settings. The functional spec sets many of these
|
|
|
|
* as 'tie-high' for their enables.
|
|
|
|
*
|
|
|
|
* I-CLOCKS:
|
|
|
|
* L3-Interconnect, SMS, GPMC, SDRC, OCM_RAM, OCM_ROM, SDMA
|
|
|
|
* CAM, HS-USB.
|
|
|
|
* F-CLOCK
|
|
|
|
* SSI.
|
|
|
|
*
|
|
|
|
* GPMC memories and SDRC have timing and clock sensitive registers which
|
|
|
|
* may very well need notification when the clock changes. Currently for low
|
|
|
|
* operating points, these are taken care of in sleep.S.
|
|
|
|
*/
|
2008-03-18 13:47:55 +00:00
|
|
|
static const struct clksel_rate core_l3_core_rates[] = {
|
|
|
|
{ .div = 1, .val = 1, .flags = RATE_IN_24XX },
|
2010-05-19 00:40:24 +00:00
|
|
|
{ .div = 4, .val = 4, .flags = RATE_IN_24XX },
|
2008-03-18 13:47:55 +00:00
|
|
|
{ .div = 6, .val = 6, .flags = RATE_IN_24XX },
|
|
|
|
{ .div = 0 }
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct clksel core_l3_clksel[] = {
|
|
|
|
{ .parent = &core_ck, .rates = core_l3_core_rates },
|
|
|
|
{ .parent = NULL }
|
|
|
|
};
|
|
|
|
|
2005-11-10 14:26:52 +00:00
|
|
|
static struct clk core_l3_ck = { /* Used for ick and fck, interconnect */
|
|
|
|
.name = "core_l3_ck",
|
2008-11-04 16:35:03 +00:00
|
|
|
.ops = &clkops_null,
|
2005-11-10 14:26:52 +00:00
|
|
|
.parent = &core_ck,
|
2008-08-19 08:08:44 +00:00
|
|
|
.clkdm_name = "core_l3_clkdm",
|
2008-03-18 13:47:55 +00:00
|
|
|
.clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
|
|
|
|
.clksel_mask = OMAP24XX_CLKSEL_L3_MASK,
|
|
|
|
.clksel = core_l3_clksel,
|
2005-11-10 14:26:52 +00:00
|
|
|
.recalc = &omap2_clksel_recalc,
|
2008-03-18 13:47:55 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
/* usb_l4_ick */
|
|
|
|
static const struct clksel_rate usb_l4_ick_core_l3_rates[] = {
|
|
|
|
{ .div = 1, .val = 1, .flags = RATE_IN_24XX },
|
2010-05-19 00:40:24 +00:00
|
|
|
{ .div = 2, .val = 2, .flags = RATE_IN_24XX },
|
2008-03-18 13:47:55 +00:00
|
|
|
{ .div = 4, .val = 4, .flags = RATE_IN_24XX },
|
|
|
|
{ .div = 0 }
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct clksel usb_l4_ick_clksel[] = {
|
|
|
|
{ .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates },
|
|
|
|
{ .parent = NULL },
|
2005-11-10 14:26:52 +00:00
|
|
|
};
|
|
|
|
|
2008-08-19 08:08:44 +00:00
|
|
|
/* It is unclear from TRM whether usb_l4_ick is really in L3 or L4 clkdm */
|
2005-11-10 14:26:52 +00:00
|
|
|
static struct clk usb_l4_ick = { /* FS-USB interface clock */
|
|
|
|
.name = "usb_l4_ick",
|
2011-02-25 22:39:30 +00:00
|
|
|
.ops = &clkops_omap2_iclk_dflt_wait,
|
2006-01-17 23:31:18 +00:00
|
|
|
.parent = &core_l3_ck,
|
2008-08-19 08:08:44 +00:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 13:47:55 +00:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
|
|
|
|
.enable_bit = OMAP24XX_EN_USB_SHIFT,
|
|
|
|
.clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
|
|
|
|
.clksel_mask = OMAP24XX_CLKSEL_USB_MASK,
|
|
|
|
.clksel = usb_l4_ick_clksel,
|
2005-11-10 14:26:52 +00:00
|
|
|
.recalc = &omap2_clksel_recalc,
|
|
|
|
};
|
|
|
|
|
2008-08-19 08:08:44 +00:00
|
|
|
/*
|
|
|
|
* L4 clock management domain
|
|
|
|
*
|
|
|
|
* This domain contains lots of interface clocks from the L4 interface, some
|
|
|
|
* functional clocks. Fixed APLL functional source clocks are managed in
|
|
|
|
* this domain.
|
|
|
|
*/
|
|
|
|
static const struct clksel_rate l4_core_l3_rates[] = {
|
2010-05-19 00:40:24 +00:00
|
|
|
{ .div = 1, .val = 1, .flags = RATE_IN_24XX },
|
2008-08-19 08:08:44 +00:00
|
|
|
{ .div = 2, .val = 2, .flags = RATE_IN_24XX },
|
|
|
|
{ .div = 0 }
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct clksel l4_clksel[] = {
|
|
|
|
{ .parent = &core_l3_ck, .rates = l4_core_l3_rates },
|
|
|
|
{ .parent = NULL }
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk l4_ck = { /* used both as an ick and fck */
|
|
|
|
.name = "l4_ck",
|
2008-11-04 16:35:03 +00:00
|
|
|
.ops = &clkops_null,
|
2008-08-19 08:08:44 +00:00
|
|
|
.parent = &core_l3_ck,
|
|
|
|
.clkdm_name = "core_l4_clkdm",
|
|
|
|
.clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
|
|
|
|
.clksel_mask = OMAP24XX_CLKSEL_L4_MASK,
|
|
|
|
.clksel = l4_clksel,
|
|
|
|
.recalc = &omap2_clksel_recalc,
|
|
|
|
};
|
|
|
|
|
2005-11-10 14:26:52 +00:00
|
|
|
/*
|
|
|
|
* SSI is in L3 management domain, its direct parent is core not l3,
|
|
|
|
* many core power domain entities are grouped into the L3 clock
|
|
|
|
* domain.
|
2008-08-19 08:08:44 +00:00
|
|
|
* SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_ICLK
|
2005-11-10 14:26:52 +00:00
|
|
|
*
|
|
|
|
* ssr = core/1/2/3/4/5, sst = 1/2 ssr.
|
|
|
|
*/
|
2008-03-18 13:47:55 +00:00
|
|
|
static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = {
|
|
|
|
{ .div = 1, .val = 1, .flags = RATE_IN_24XX },
|
2010-05-19 00:40:24 +00:00
|
|
|
{ .div = 2, .val = 2, .flags = RATE_IN_24XX },
|
2008-03-18 13:47:55 +00:00
|
|
|
{ .div = 3, .val = 3, .flags = RATE_IN_24XX },
|
|
|
|
{ .div = 4, .val = 4, .flags = RATE_IN_24XX },
|
|
|
|
{ .div = 5, .val = 5, .flags = RATE_IN_243X },
|
|
|
|
{ .div = 0 }
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct clksel ssi_ssr_sst_fck_clksel[] = {
|
|
|
|
{ .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates },
|
|
|
|
{ .parent = NULL }
|
|
|
|
};
|
|
|
|
|
2005-11-10 14:26:52 +00:00
|
|
|
static struct clk ssi_ssr_sst_fck = {
|
|
|
|
.name = "ssi_fck",
|
2008-11-04 17:59:52 +00:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2005-11-10 14:26:52 +00:00
|
|
|
.parent = &core_ck,
|
2008-08-19 08:08:44 +00:00
|
|
|
.clkdm_name = "core_l3_clkdm",
|
2008-03-18 13:47:55 +00:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
|
|
|
|
.enable_bit = OMAP24XX_EN_SSI_SHIFT,
|
|
|
|
.clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
|
|
|
|
.clksel_mask = OMAP24XX_CLKSEL_SSI_MASK,
|
|
|
|
.clksel = ssi_ssr_sst_fck_clksel,
|
2005-11-10 14:26:52 +00:00
|
|
|
.recalc = &omap2_clksel_recalc,
|
|
|
|
};
|
|
|
|
|
2009-01-28 02:12:54 +00:00
|
|
|
/*
|
|
|
|
* Presumably this is the same as SSI_ICLK.
|
|
|
|
* TRM contradicts itself on what clockdomain SSI_ICLK is in
|
|
|
|
*/
|
|
|
|
static struct clk ssi_l4_ick = {
|
|
|
|
.name = "ssi_l4_ick",
|
2011-02-25 22:39:30 +00:00
|
|
|
.ops = &clkops_omap2_iclk_dflt_wait,
|
2009-01-28 02:12:54 +00:00
|
|
|
.parent = &l4_ck,
|
|
|
|
.clkdm_name = "core_l4_clkdm",
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
|
|
|
|
.enable_bit = OMAP24XX_EN_SSI_SHIFT,
|
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
2008-08-19 08:08:44 +00:00
|
|
|
|
2005-11-10 14:26:52 +00:00
|
|
|
/*
|
|
|
|
* GFX clock domain
|
|
|
|
* Clocks:
|
|
|
|
* GFX_FCLK, GFX_ICLK
|
|
|
|
* GFX_CG1(2d), GFX_CG2(3d)
|
|
|
|
*
|
|
|
|
* GFX_FCLK runs from L3, and is divided by (1,2,3,4)
|
|
|
|
* The 2d and 3d clocks run at a hardware determined
|
|
|
|
* divided value of fclk.
|
|
|
|
*
|
|
|
|
*/
|
2008-03-18 13:47:55 +00:00
|
|
|
|
|
|
|
/* This clksel struct is shared between gfx_3d_fck and gfx_2d_fck */
|
|
|
|
static const struct clksel gfx_fck_clksel[] = {
|
|
|
|
{ .parent = &core_l3_ck, .rates = gfx_l3_rates },
|
|
|
|
{ .parent = NULL },
|
|
|
|
};
|
|
|
|
|
2005-11-10 14:26:52 +00:00
|
|
|
static struct clk gfx_3d_fck = {
|
|
|
|
.name = "gfx_3d_fck",
|
2008-11-04 17:59:52 +00:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2005-11-10 14:26:52 +00:00
|
|
|
.parent = &core_l3_ck,
|
2008-08-19 08:08:44 +00:00
|
|
|
.clkdm_name = "gfx_clkdm",
|
2008-03-18 13:47:55 +00:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
|
|
|
|
.enable_bit = OMAP24XX_EN_3D_SHIFT,
|
|
|
|
.clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
|
|
|
|
.clksel_mask = OMAP_CLKSEL_GFX_MASK,
|
|
|
|
.clksel = gfx_fck_clksel,
|
2005-11-10 14:26:52 +00:00
|
|
|
.recalc = &omap2_clksel_recalc,
|
2008-03-18 13:47:55 +00:00
|
|
|
.round_rate = &omap2_clksel_round_rate,
|
|
|
|
.set_rate = &omap2_clksel_set_rate
|
2005-11-10 14:26:52 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk gfx_2d_fck = {
|
|
|
|
.name = "gfx_2d_fck",
|
2008-11-04 17:59:52 +00:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2005-11-10 14:26:52 +00:00
|
|
|
.parent = &core_l3_ck,
|
2008-08-19 08:08:44 +00:00
|
|
|
.clkdm_name = "gfx_clkdm",
|
2008-03-18 13:47:55 +00:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
|
|
|
|
.enable_bit = OMAP24XX_EN_2D_SHIFT,
|
|
|
|
.clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
|
|
|
|
.clksel_mask = OMAP_CLKSEL_GFX_MASK,
|
|
|
|
.clksel = gfx_fck_clksel,
|
2005-11-10 14:26:52 +00:00
|
|
|
.recalc = &omap2_clksel_recalc,
|
|
|
|
};
|
|
|
|
|
2011-02-25 22:39:30 +00:00
|
|
|
/* This interface clock does not have a CM_AUTOIDLE bit */
|
2005-11-10 14:26:52 +00:00
|
|
|
static struct clk gfx_ick = {
|
|
|
|
.name = "gfx_ick", /* From l3 */
|
2008-11-04 17:59:52 +00:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2005-11-10 14:26:52 +00:00
|
|
|
.parent = &core_l3_ck,
|
2008-08-19 08:08:44 +00:00
|
|
|
.clkdm_name = "gfx_clkdm",
|
2008-03-18 13:47:55 +00:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
|
|
|
|
.enable_bit = OMAP_EN_GFX_SHIFT,
|
|
|
|
.recalc = &followparent_recalc,
|
2005-11-10 14:26:52 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Modem clock domain (2430)
|
|
|
|
* CLOCKS:
|
|
|
|
* MDM_OSC_CLK
|
|
|
|
* MDM_ICLK
|
2008-03-18 13:47:55 +00:00
|
|
|
* These clocks are usable in chassis mode only.
|
2005-11-10 14:26:52 +00:00
|
|
|
*/
|
2008-03-18 13:47:55 +00:00
|
|
|
static const struct clksel_rate mdm_ick_core_rates[] = {
|
|
|
|
{ .div = 1, .val = 1, .flags = RATE_IN_243X },
|
2010-05-19 00:40:24 +00:00
|
|
|
{ .div = 4, .val = 4, .flags = RATE_IN_243X },
|
2008-03-18 13:47:55 +00:00
|
|
|
{ .div = 6, .val = 6, .flags = RATE_IN_243X },
|
|
|
|
{ .div = 9, .val = 9, .flags = RATE_IN_243X },
|
|
|
|
{ .div = 0 }
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct clksel mdm_ick_clksel[] = {
|
|
|
|
{ .parent = &core_ck, .rates = mdm_ick_core_rates },
|
|
|
|
{ .parent = NULL }
|
|
|
|
};
|
|
|
|
|
2005-11-10 14:26:52 +00:00
|
|
|
static struct clk mdm_ick = { /* used both as a ick and fck */
|
|
|
|
.name = "mdm_ick",
|
2011-02-25 22:39:30 +00:00
|
|
|
.ops = &clkops_omap2_iclk_dflt_wait,
|
2005-11-10 14:26:52 +00:00
|
|
|
.parent = &core_ck,
|
2008-08-19 08:08:44 +00:00
|
|
|
.clkdm_name = "mdm_clkdm",
|
2008-03-18 13:47:55 +00:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN),
|
|
|
|
.enable_bit = OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT,
|
|
|
|
.clksel_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_CLKSEL),
|
|
|
|
.clksel_mask = OMAP2430_CLKSEL_MDM_MASK,
|
|
|
|
.clksel = mdm_ick_clksel,
|
2005-11-10 14:26:52 +00:00
|
|
|
.recalc = &omap2_clksel_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk mdm_osc_ck = {
|
|
|
|
.name = "mdm_osc_ck",
|
2011-02-25 22:39:30 +00:00
|
|
|
.ops = &clkops_omap2_mdmclk_dflt_wait,
|
2005-11-10 14:26:52 +00:00
|
|
|
.parent = &osc_ck,
|
2008-08-19 08:08:44 +00:00
|
|
|
.clkdm_name = "mdm_clkdm",
|
2008-03-18 13:47:55 +00:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_FCLKEN),
|
|
|
|
.enable_bit = OMAP2430_EN_OSC_SHIFT,
|
|
|
|
.recalc = &followparent_recalc,
|
2005-11-10 14:26:52 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
/*
|
|
|
|
* DSS clock domain
|
|
|
|
* CLOCKs:
|
|
|
|
* DSS_L4_ICLK, DSS_L3_ICLK,
|
|
|
|
* DSS_CLK1, DSS_CLK2, DSS_54MHz_CLK
|
|
|
|
*
|
|
|
|
* DSS is both initiator and target.
|
|
|
|
*/
|
2008-03-18 13:47:55 +00:00
|
|
|
/* XXX Add RATE_NOT_VALIDATED */
|
|
|
|
|
|
|
|
static const struct clksel_rate dss1_fck_sys_rates[] = {
|
2010-05-19 00:40:24 +00:00
|
|
|
{ .div = 1, .val = 0, .flags = RATE_IN_24XX },
|
2008-03-18 13:47:55 +00:00
|
|
|
{ .div = 0 }
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct clksel_rate dss1_fck_core_rates[] = {
|
|
|
|
{ .div = 1, .val = 1, .flags = RATE_IN_24XX },
|
|
|
|
{ .div = 2, .val = 2, .flags = RATE_IN_24XX },
|
|
|
|
{ .div = 3, .val = 3, .flags = RATE_IN_24XX },
|
|
|
|
{ .div = 4, .val = 4, .flags = RATE_IN_24XX },
|
|
|
|
{ .div = 5, .val = 5, .flags = RATE_IN_24XX },
|
|
|
|
{ .div = 6, .val = 6, .flags = RATE_IN_24XX },
|
|
|
|
{ .div = 8, .val = 8, .flags = RATE_IN_24XX },
|
|
|
|
{ .div = 9, .val = 9, .flags = RATE_IN_24XX },
|
|
|
|
{ .div = 12, .val = 12, .flags = RATE_IN_24XX },
|
2010-05-19 00:40:24 +00:00
|
|
|
{ .div = 16, .val = 16, .flags = RATE_IN_24XX },
|
2008-03-18 13:47:55 +00:00
|
|
|
{ .div = 0 }
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct clksel dss1_fck_clksel[] = {
|
|
|
|
{ .parent = &sys_ck, .rates = dss1_fck_sys_rates },
|
|
|
|
{ .parent = &core_ck, .rates = dss1_fck_core_rates },
|
|
|
|
{ .parent = NULL },
|
|
|
|
};
|
|
|
|
|
2005-11-10 14:26:52 +00:00
|
|
|
static struct clk dss_ick = { /* Enables both L3,L4 ICLK's */
|
|
|
|
.name = "dss_ick",
|
2011-02-25 22:39:30 +00:00
|
|
|
.ops = &clkops_omap2_iclk_dflt,
|
2005-11-10 14:26:52 +00:00
|
|
|
.parent = &l4_ck, /* really both l3 and l4 */
|
2008-08-19 08:08:44 +00:00
|
|
|
.clkdm_name = "dss_clkdm",
|
2008-03-18 13:47:55 +00:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
|
|
|
|
.enable_bit = OMAP24XX_EN_DSS1_SHIFT,
|
|
|
|
.recalc = &followparent_recalc,
|
2005-11-10 14:26:52 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk dss1_fck = {
|
|
|
|
.name = "dss1_fck",
|
2008-11-04 18:59:32 +00:00
|
|
|
.ops = &clkops_omap2_dflt,
|
2005-11-10 14:26:52 +00:00
|
|
|
.parent = &core_ck, /* Core or sys */
|
2008-08-19 08:08:44 +00:00
|
|
|
.clkdm_name = "dss_clkdm",
|
2008-03-18 13:47:55 +00:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
|
|
|
|
.enable_bit = OMAP24XX_EN_DSS1_SHIFT,
|
|
|
|
.init = &omap2_init_clksel_parent,
|
|
|
|
.clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
|
|
|
|
.clksel_mask = OMAP24XX_CLKSEL_DSS1_MASK,
|
|
|
|
.clksel = dss1_fck_clksel,
|
2005-11-10 14:26:52 +00:00
|
|
|
.recalc = &omap2_clksel_recalc,
|
2008-03-18 13:47:55 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static const struct clksel_rate dss2_fck_sys_rates[] = {
|
2010-05-19 00:40:24 +00:00
|
|
|
{ .div = 1, .val = 0, .flags = RATE_IN_24XX },
|
2008-03-18 13:47:55 +00:00
|
|
|
{ .div = 0 }
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct clksel_rate dss2_fck_48m_rates[] = {
|
2010-05-19 00:40:24 +00:00
|
|
|
{ .div = 1, .val = 1, .flags = RATE_IN_24XX },
|
2008-03-18 13:47:55 +00:00
|
|
|
{ .div = 0 }
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct clksel dss2_fck_clksel[] = {
|
|
|
|
{ .parent = &sys_ck, .rates = dss2_fck_sys_rates },
|
|
|
|
{ .parent = &func_48m_ck, .rates = dss2_fck_48m_rates },
|
|
|
|
{ .parent = NULL }
|
2005-11-10 14:26:52 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk dss2_fck = { /* Alt clk used in power management */
|
|
|
|
.name = "dss2_fck",
|
2008-11-04 18:59:32 +00:00
|
|
|
.ops = &clkops_omap2_dflt,
|
2005-11-10 14:26:52 +00:00
|
|
|
.parent = &sys_ck, /* fixed at sys_ck or 48MHz */
|
2008-08-19 08:08:44 +00:00
|
|
|
.clkdm_name = "dss_clkdm",
|
2008-03-18 13:47:55 +00:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
|
|
|
|
.enable_bit = OMAP24XX_EN_DSS2_SHIFT,
|
|
|
|
.init = &omap2_init_clksel_parent,
|
|
|
|
.clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
|
|
|
|
.clksel_mask = OMAP24XX_CLKSEL_DSS2_MASK,
|
|
|
|
.clksel = dss2_fck_clksel,
|
2010-12-22 04:08:14 +00:00
|
|
|
.recalc = &omap2_clksel_recalc,
|
2005-11-10 14:26:52 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk dss_54m_fck = { /* Alt clk used in power management */
|
|
|
|
.name = "dss_54m_fck", /* 54m tv clk */
|
2008-11-04 17:59:52 +00:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2005-11-10 14:26:52 +00:00
|
|
|
.parent = &func_54m_ck,
|
2008-08-19 08:08:44 +00:00
|
|
|
.clkdm_name = "dss_clkdm",
|
2008-03-18 13:47:55 +00:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
|
|
|
|
.enable_bit = OMAP24XX_EN_TV_SHIFT,
|
|
|
|
.recalc = &followparent_recalc,
|
2005-11-10 14:26:52 +00:00
|
|
|
};
|
|
|
|
|
OMAP2xxx: clock: fix interface clocks and clockdomains for modules in the WKUP domain
The parent of the interface clocks for GPTIMER1, MPU_WDT,
SYNCTIMER_32K, SCM, WDT1, and the ICR (2430 only) were all listed as
being l4_ck. This isn't accurate; these modules exist inside the WKUP
domain, and the interface clock to these modules runs at the SYS_CLK
rate rather than the CORE L4 rate.
So, create a new clock "wu_l4_ick", similar to the OMAP3
"wkup_l4_ick", that serves as the parent for these clocks.
Also, these clocks were listed as existing inside core_l4_clkdm;
wkup_clkdm is probably more accurate.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
2011-02-16 22:38:38 +00:00
|
|
|
static struct clk wu_l4_ick = {
|
|
|
|
.name = "wu_l4_ick",
|
|
|
|
.ops = &clkops_null,
|
|
|
|
.parent = &sys_ck,
|
|
|
|
.clkdm_name = "wkup_clkdm",
|
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
2005-11-10 14:26:52 +00:00
|
|
|
/*
|
|
|
|
* CORE power domain ICLK & FCLK defines.
|
|
|
|
* Many of the these can have more than one possible parent. Entries
|
|
|
|
* here will likely have an L4 interface parent, and may have multiple
|
|
|
|
* functional clock parents.
|
|
|
|
*/
|
2008-03-18 13:47:55 +00:00
|
|
|
static const struct clksel_rate gpt_alt_rates[] = {
|
2010-05-19 00:40:24 +00:00
|
|
|
{ .div = 1, .val = 2, .flags = RATE_IN_24XX },
|
2008-03-18 13:47:55 +00:00
|
|
|
{ .div = 0 }
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct clksel omap24xx_gpt_clksel[] = {
|
|
|
|
{ .parent = &func_32k_ck, .rates = gpt_32k_rates },
|
|
|
|
{ .parent = &sys_ck, .rates = gpt_sys_rates },
|
|
|
|
{ .parent = &alt_ck, .rates = gpt_alt_rates },
|
|
|
|
{ .parent = NULL },
|
|
|
|
};
|
|
|
|
|
2005-11-10 14:26:52 +00:00
|
|
|
static struct clk gpt1_ick = {
|
|
|
|
.name = "gpt1_ick",
|
2011-02-25 22:39:30 +00:00
|
|
|
.ops = &clkops_omap2_iclk_dflt_wait,
|
OMAP2xxx: clock: fix interface clocks and clockdomains for modules in the WKUP domain
The parent of the interface clocks for GPTIMER1, MPU_WDT,
SYNCTIMER_32K, SCM, WDT1, and the ICR (2430 only) were all listed as
being l4_ck. This isn't accurate; these modules exist inside the WKUP
domain, and the interface clock to these modules runs at the SYS_CLK
rate rather than the CORE L4 rate.
So, create a new clock "wu_l4_ick", similar to the OMAP3
"wkup_l4_ick", that serves as the parent for these clocks.
Also, these clocks were listed as existing inside core_l4_clkdm;
wkup_clkdm is probably more accurate.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
2011-02-16 22:38:38 +00:00
|
|
|
.parent = &wu_l4_ick,
|
|
|
|
.clkdm_name = "wkup_clkdm",
|
2008-03-18 13:47:55 +00:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
|
|
|
|
.enable_bit = OMAP24XX_EN_GPT1_SHIFT,
|
|
|
|
.recalc = &followparent_recalc,
|
2005-11-10 14:26:52 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk gpt1_fck = {
|
|
|
|
.name = "gpt1_fck",
|
2008-11-04 17:59:52 +00:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2005-11-10 14:26:52 +00:00
|
|
|
.parent = &func_32k_ck,
|
2008-08-19 08:08:44 +00:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 13:47:55 +00:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
|
|
|
|
.enable_bit = OMAP24XX_EN_GPT1_SHIFT,
|
|
|
|
.init = &omap2_init_clksel_parent,
|
|
|
|
.clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL1),
|
|
|
|
.clksel_mask = OMAP24XX_CLKSEL_GPT1_MASK,
|
|
|
|
.clksel = omap24xx_gpt_clksel,
|
|
|
|
.recalc = &omap2_clksel_recalc,
|
|
|
|
.round_rate = &omap2_clksel_round_rate,
|
|
|
|
.set_rate = &omap2_clksel_set_rate
|
2005-11-10 14:26:52 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk gpt2_ick = {
|
|
|
|
.name = "gpt2_ick",
|
2011-02-25 22:39:30 +00:00
|
|
|
.ops = &clkops_omap2_iclk_dflt_wait,
|
2005-11-10 14:26:52 +00:00
|
|
|
.parent = &l4_ck,
|
2008-08-19 08:08:44 +00:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 13:47:55 +00:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
|
|
|
|
.enable_bit = OMAP24XX_EN_GPT2_SHIFT,
|
|
|
|
.recalc = &followparent_recalc,
|
2005-11-10 14:26:52 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk gpt2_fck = {
|
|
|
|
.name = "gpt2_fck",
|
2008-11-04 17:59:52 +00:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2005-11-10 14:26:52 +00:00
|
|
|
.parent = &func_32k_ck,
|
2008-08-19 08:08:44 +00:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 13:47:55 +00:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
|
|
|
|
.enable_bit = OMAP24XX_EN_GPT2_SHIFT,
|
|
|
|
.init = &omap2_init_clksel_parent,
|
|
|
|
.clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
|
|
|
|
.clksel_mask = OMAP24XX_CLKSEL_GPT2_MASK,
|
|
|
|
.clksel = omap24xx_gpt_clksel,
|
|
|
|
.recalc = &omap2_clksel_recalc,
|
2005-11-10 14:26:52 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk gpt3_ick = {
|
|
|
|
.name = "gpt3_ick",
|
2011-02-25 22:39:30 +00:00
|
|
|
.ops = &clkops_omap2_iclk_dflt_wait,
|
2005-11-10 14:26:52 +00:00
|
|
|
.parent = &l4_ck,
|
2008-08-19 08:08:44 +00:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 13:47:55 +00:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
|
|
|
|
.enable_bit = OMAP24XX_EN_GPT3_SHIFT,
|
|
|
|
.recalc = &followparent_recalc,
|
2005-11-10 14:26:52 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk gpt3_fck = {
|
|
|
|
.name = "gpt3_fck",
|
2008-11-04 17:59:52 +00:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2005-11-10 14:26:52 +00:00
|
|
|
.parent = &func_32k_ck,
|
2008-08-19 08:08:44 +00:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 13:47:55 +00:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
|
|
|
|
.enable_bit = OMAP24XX_EN_GPT3_SHIFT,
|
|
|
|
.init = &omap2_init_clksel_parent,
|
|
|
|
.clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
|
|
|
|
.clksel_mask = OMAP24XX_CLKSEL_GPT3_MASK,
|
|
|
|
.clksel = omap24xx_gpt_clksel,
|
|
|
|
.recalc = &omap2_clksel_recalc,
|
2005-11-10 14:26:52 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk gpt4_ick = {
|
|
|
|
.name = "gpt4_ick",
|
2011-02-25 22:39:30 +00:00
|
|
|
.ops = &clkops_omap2_iclk_dflt_wait,
|
2005-11-10 14:26:52 +00:00
|
|
|
.parent = &l4_ck,
|
2008-08-19 08:08:44 +00:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 13:47:55 +00:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
|
|
|
|
.enable_bit = OMAP24XX_EN_GPT4_SHIFT,
|
|
|
|
.recalc = &followparent_recalc,
|
2005-11-10 14:26:52 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk gpt4_fck = {
|
|
|
|
.name = "gpt4_fck",
|
2008-11-04 17:59:52 +00:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2005-11-10 14:26:52 +00:00
|
|
|
.parent = &func_32k_ck,
|
2008-08-19 08:08:44 +00:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 13:47:55 +00:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
|
|
|
|
.enable_bit = OMAP24XX_EN_GPT4_SHIFT,
|
|
|
|
.init = &omap2_init_clksel_parent,
|
|
|
|
.clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
|
|
|
|
.clksel_mask = OMAP24XX_CLKSEL_GPT4_MASK,
|
|
|
|
.clksel = omap24xx_gpt_clksel,
|
|
|
|
.recalc = &omap2_clksel_recalc,
|
2005-11-10 14:26:52 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk gpt5_ick = {
|
|
|
|
.name = "gpt5_ick",
|
2011-02-25 22:39:30 +00:00
|
|
|
.ops = &clkops_omap2_iclk_dflt_wait,
|
2005-11-10 14:26:52 +00:00
|
|
|
.parent = &l4_ck,
|
2008-08-19 08:08:44 +00:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 13:47:55 +00:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
|
|
|
|
.enable_bit = OMAP24XX_EN_GPT5_SHIFT,
|
|
|
|
.recalc = &followparent_recalc,
|
2005-11-10 14:26:52 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk gpt5_fck = {
|
|
|
|
.name = "gpt5_fck",
|
2008-11-04 17:59:52 +00:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2005-11-10 14:26:52 +00:00
|
|
|
.parent = &func_32k_ck,
|
2008-08-19 08:08:44 +00:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 13:47:55 +00:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
|
|
|
|
.enable_bit = OMAP24XX_EN_GPT5_SHIFT,
|
|
|
|
.init = &omap2_init_clksel_parent,
|
|
|
|
.clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
|
|
|
|
.clksel_mask = OMAP24XX_CLKSEL_GPT5_MASK,
|
|
|
|
.clksel = omap24xx_gpt_clksel,
|
|
|
|
.recalc = &omap2_clksel_recalc,
|
2005-11-10 14:26:52 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk gpt6_ick = {
|
|
|
|
.name = "gpt6_ick",
|
2011-02-25 22:39:30 +00:00
|
|
|
.ops = &clkops_omap2_iclk_dflt_wait,
|
2005-11-10 14:26:52 +00:00
|
|
|
.parent = &l4_ck,
|
2008-08-19 08:08:44 +00:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 13:47:55 +00:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
|
|
|
|
.enable_bit = OMAP24XX_EN_GPT6_SHIFT,
|
|
|
|
.recalc = &followparent_recalc,
|
2005-11-10 14:26:52 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk gpt6_fck = {
|
|
|
|
.name = "gpt6_fck",
|
2008-11-04 17:59:52 +00:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2005-11-10 14:26:52 +00:00
|
|
|
.parent = &func_32k_ck,
|
2008-08-19 08:08:44 +00:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 13:47:55 +00:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
|
|
|
|
.enable_bit = OMAP24XX_EN_GPT6_SHIFT,
|
|
|
|
.init = &omap2_init_clksel_parent,
|
|
|
|
.clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
|
|
|
|
.clksel_mask = OMAP24XX_CLKSEL_GPT6_MASK,
|
|
|
|
.clksel = omap24xx_gpt_clksel,
|
|
|
|
.recalc = &omap2_clksel_recalc,
|
2005-11-10 14:26:52 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk gpt7_ick = {
|
|
|
|
.name = "gpt7_ick",
|
2011-02-25 22:39:30 +00:00
|
|
|
.ops = &clkops_omap2_iclk_dflt_wait,
|
2005-11-10 14:26:52 +00:00
|
|
|
.parent = &l4_ck,
|
2011-02-25 21:53:40 +00:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 13:47:55 +00:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
|
|
|
|
.enable_bit = OMAP24XX_EN_GPT7_SHIFT,
|
|
|
|
.recalc = &followparent_recalc,
|
2005-11-10 14:26:52 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk gpt7_fck = {
|
|
|
|
.name = "gpt7_fck",
|
2008-11-04 17:59:52 +00:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2005-11-10 14:26:52 +00:00
|
|
|
.parent = &func_32k_ck,
|
2008-08-19 08:08:44 +00:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 13:47:55 +00:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
|
|
|
|
.enable_bit = OMAP24XX_EN_GPT7_SHIFT,
|
|
|
|
.init = &omap2_init_clksel_parent,
|
|
|
|
.clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
|
|
|
|
.clksel_mask = OMAP24XX_CLKSEL_GPT7_MASK,
|
|
|
|
.clksel = omap24xx_gpt_clksel,
|
|
|
|
.recalc = &omap2_clksel_recalc,
|
2005-11-10 14:26:52 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk gpt8_ick = {
|
|
|
|
.name = "gpt8_ick",
|
2011-02-25 22:39:30 +00:00
|
|
|
.ops = &clkops_omap2_iclk_dflt_wait,
|
2005-11-10 14:26:52 +00:00
|
|
|
.parent = &l4_ck,
|
2008-08-19 08:08:44 +00:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 13:47:55 +00:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
|
|
|
|
.enable_bit = OMAP24XX_EN_GPT8_SHIFT,
|
|
|
|
.recalc = &followparent_recalc,
|
2005-11-10 14:26:52 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk gpt8_fck = {
|
|
|
|
.name = "gpt8_fck",
|
2008-11-04 17:59:52 +00:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2005-11-10 14:26:52 +00:00
|
|
|
.parent = &func_32k_ck,
|
2008-08-19 08:08:44 +00:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 13:47:55 +00:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
|
|
|
|
.enable_bit = OMAP24XX_EN_GPT8_SHIFT,
|
|
|
|
.init = &omap2_init_clksel_parent,
|
|
|
|
.clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
|
|
|
|
.clksel_mask = OMAP24XX_CLKSEL_GPT8_MASK,
|
|
|
|
.clksel = omap24xx_gpt_clksel,
|
|
|
|
.recalc = &omap2_clksel_recalc,
|
2005-11-10 14:26:52 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk gpt9_ick = {
|
|
|
|
.name = "gpt9_ick",
|
2011-02-25 22:39:30 +00:00
|
|
|
.ops = &clkops_omap2_iclk_dflt_wait,
|
2005-11-10 14:26:52 +00:00
|
|
|
.parent = &l4_ck,
|
2008-08-19 08:08:44 +00:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 13:47:55 +00:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
|
|
|
|
.enable_bit = OMAP24XX_EN_GPT9_SHIFT,
|
|
|
|
.recalc = &followparent_recalc,
|
2005-11-10 14:26:52 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk gpt9_fck = {
|
|
|
|
.name = "gpt9_fck",
|
2008-11-04 17:59:52 +00:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2005-11-10 14:26:52 +00:00
|
|
|
.parent = &func_32k_ck,
|
2008-08-19 08:08:44 +00:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 13:47:55 +00:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
|
|
|
|
.enable_bit = OMAP24XX_EN_GPT9_SHIFT,
|
|
|
|
.init = &omap2_init_clksel_parent,
|
|
|
|
.clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
|
|
|
|
.clksel_mask = OMAP24XX_CLKSEL_GPT9_MASK,
|
|
|
|
.clksel = omap24xx_gpt_clksel,
|
|
|
|
.recalc = &omap2_clksel_recalc,
|
2005-11-10 14:26:52 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk gpt10_ick = {
|
|
|
|
.name = "gpt10_ick",
|
2011-02-25 22:39:30 +00:00
|
|
|
.ops = &clkops_omap2_iclk_dflt_wait,
|
2005-11-10 14:26:52 +00:00
|
|
|
.parent = &l4_ck,
|
2008-08-19 08:08:44 +00:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 13:47:55 +00:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
|
|
|
|
.enable_bit = OMAP24XX_EN_GPT10_SHIFT,
|
|
|
|
.recalc = &followparent_recalc,
|
2005-11-10 14:26:52 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk gpt10_fck = {
|
|
|
|
.name = "gpt10_fck",
|
2008-11-04 17:59:52 +00:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2005-11-10 14:26:52 +00:00
|
|
|
.parent = &func_32k_ck,
|
2008-08-19 08:08:44 +00:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 13:47:55 +00:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
|
|
|
|
.enable_bit = OMAP24XX_EN_GPT10_SHIFT,
|
|
|
|
.init = &omap2_init_clksel_parent,
|
|
|
|
.clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
|
|
|
|
.clksel_mask = OMAP24XX_CLKSEL_GPT10_MASK,
|
|
|
|
.clksel = omap24xx_gpt_clksel,
|
|
|
|
.recalc = &omap2_clksel_recalc,
|
2005-11-10 14:26:52 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk gpt11_ick = {
|
|
|
|
.name = "gpt11_ick",
|
2011-02-25 22:39:30 +00:00
|
|
|
.ops = &clkops_omap2_iclk_dflt_wait,
|
2005-11-10 14:26:52 +00:00
|
|
|
.parent = &l4_ck,
|
2008-08-19 08:08:44 +00:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 13:47:55 +00:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
|
|
|
|
.enable_bit = OMAP24XX_EN_GPT11_SHIFT,
|
|
|
|
.recalc = &followparent_recalc,
|
2005-11-10 14:26:52 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk gpt11_fck = {
|
|
|
|
.name = "gpt11_fck",
|
2008-11-04 17:59:52 +00:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2005-11-10 14:26:52 +00:00
|
|
|
.parent = &func_32k_ck,
|
2008-08-19 08:08:44 +00:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 13:47:55 +00:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
|
|
|
|
.enable_bit = OMAP24XX_EN_GPT11_SHIFT,
|
|
|
|
.init = &omap2_init_clksel_parent,
|
|
|
|
.clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
|
|
|
|
.clksel_mask = OMAP24XX_CLKSEL_GPT11_MASK,
|
|
|
|
.clksel = omap24xx_gpt_clksel,
|
|
|
|
.recalc = &omap2_clksel_recalc,
|
2005-11-10 14:26:52 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk gpt12_ick = {
|
|
|
|
.name = "gpt12_ick",
|
2011-02-25 22:39:30 +00:00
|
|
|
.ops = &clkops_omap2_iclk_dflt_wait,
|
2005-11-10 14:26:52 +00:00
|
|
|
.parent = &l4_ck,
|
2008-08-19 08:08:44 +00:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 13:47:55 +00:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
|
|
|
|
.enable_bit = OMAP24XX_EN_GPT12_SHIFT,
|
|
|
|
.recalc = &followparent_recalc,
|
2005-11-10 14:26:52 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk gpt12_fck = {
|
|
|
|
.name = "gpt12_fck",
|
2008-11-04 17:59:52 +00:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
OMAP2/3 GPTIMER: allow system tick GPTIMER to be changed in board-*.c files
Add a function omap2_gp_clockevent_set_gptimer() for board-*.c files
to use in .init_irq functions to configure the system tick GPTIMER.
Practical choices at this point are GPTIMER1 or GPTIMER12. Both of
these timers are in the WKUP powerdomain, and so are unaffected by
chip power management. GPTIMER1 can use sys_clk as a source, for
applications where a high-resolution timer is more important than
power management. GPTIMER12 has the special property that it has the
secure 32kHz oscillator as its source clock, which may be less prone
to glitches than the off-chip 32kHz oscillator. But on HS devices, it
may not be available for Linux use.
It appears that most boards are fine with GPTIMER1, but BeagleBoard
should use GPTIMER12 when using a 32KiHz timer source, due to hardware bugs
in revisions B4 and below. Modify board-omap3beagle.c to use GPTIMER12.
This patch originally used a Kbuild config option to select the GPTIMER,
but was changed to allow this to be specified in board-*.c files, per
Tony's request.
Kalle Vallo <kalle.valo@nokia.com> found a bug in an earlier version of
this patch - thanks Kalle.
Tested on Beagle rev B4 ES2.1, with and without CONFIG_OMAP_32K_TIMER, and
3430SDP.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Cc: Kalle Valo <kalle.valo@nokia.com>
2009-04-24 03:11:10 +00:00
|
|
|
.parent = &secure_32k_ck,
|
2008-08-19 08:08:44 +00:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 13:47:55 +00:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
|
|
|
|
.enable_bit = OMAP24XX_EN_GPT12_SHIFT,
|
|
|
|
.init = &omap2_init_clksel_parent,
|
|
|
|
.clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
|
|
|
|
.clksel_mask = OMAP24XX_CLKSEL_GPT12_MASK,
|
|
|
|
.clksel = omap24xx_gpt_clksel,
|
|
|
|
.recalc = &omap2_clksel_recalc,
|
2005-11-10 14:26:52 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk mcbsp1_ick = {
|
2010-02-23 05:09:19 +00:00
|
|
|
.name = "mcbsp1_ick",
|
2011-02-25 22:39:30 +00:00
|
|
|
.ops = &clkops_omap2_iclk_dflt_wait,
|
2005-11-10 14:26:52 +00:00
|
|
|
.parent = &l4_ck,
|
2008-08-19 08:08:44 +00:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 13:47:55 +00:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
|
|
|
|
.enable_bit = OMAP24XX_EN_MCBSP1_SHIFT,
|
|
|
|
.recalc = &followparent_recalc,
|
2005-11-10 14:26:52 +00:00
|
|
|
};
|
|
|
|
|
2010-10-08 17:40:18 +00:00
|
|
|
static const struct clksel_rate common_mcbsp_96m_rates[] = {
|
|
|
|
{ .div = 1, .val = 0, .flags = RATE_IN_24XX },
|
|
|
|
{ .div = 0 }
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
|
|
|
|
{ .div = 1, .val = 1, .flags = RATE_IN_24XX },
|
|
|
|
{ .div = 0 }
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct clksel mcbsp_fck_clksel[] = {
|
|
|
|
{ .parent = &func_96m_ck, .rates = common_mcbsp_96m_rates },
|
|
|
|
{ .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
|
|
|
|
{ .parent = NULL }
|
|
|
|
};
|
|
|
|
|
2005-11-10 14:26:52 +00:00
|
|
|
static struct clk mcbsp1_fck = {
|
2010-02-23 05:09:19 +00:00
|
|
|
.name = "mcbsp1_fck",
|
2008-11-04 17:59:52 +00:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2005-11-10 14:26:52 +00:00
|
|
|
.parent = &func_96m_ck,
|
2010-10-08 17:40:18 +00:00
|
|
|
.init = &omap2_init_clksel_parent,
|
2008-08-19 08:08:44 +00:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 13:47:55 +00:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
|
|
|
|
.enable_bit = OMAP24XX_EN_MCBSP1_SHIFT,
|
2010-10-08 17:40:18 +00:00
|
|
|
.clksel_reg = OMAP243X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
|
|
|
|
.clksel_mask = OMAP2_MCBSP1_CLKS_MASK,
|
|
|
|
.clksel = mcbsp_fck_clksel,
|
|
|
|
.recalc = &omap2_clksel_recalc,
|
2005-11-10 14:26:52 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk mcbsp2_ick = {
|
2010-02-23 05:09:19 +00:00
|
|
|
.name = "mcbsp2_ick",
|
2011-02-25 22:39:30 +00:00
|
|
|
.ops = &clkops_omap2_iclk_dflt_wait,
|
2005-11-10 14:26:52 +00:00
|
|
|
.parent = &l4_ck,
|
2008-08-19 08:08:44 +00:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 13:47:55 +00:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
|
|
|
|
.enable_bit = OMAP24XX_EN_MCBSP2_SHIFT,
|
|
|
|
.recalc = &followparent_recalc,
|
2005-11-10 14:26:52 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk mcbsp2_fck = {
|
2010-02-23 05:09:19 +00:00
|
|
|
.name = "mcbsp2_fck",
|
2008-11-04 17:59:52 +00:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2005-11-10 14:26:52 +00:00
|
|
|
.parent = &func_96m_ck,
|
2010-10-08 17:40:18 +00:00
|
|
|
.init = &omap2_init_clksel_parent,
|
2008-08-19 08:08:44 +00:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 13:47:55 +00:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
|
|
|
|
.enable_bit = OMAP24XX_EN_MCBSP2_SHIFT,
|
2010-10-08 17:40:18 +00:00
|
|
|
.clksel_reg = OMAP243X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
|
|
|
|
.clksel_mask = OMAP2_MCBSP2_CLKS_MASK,
|
|
|
|
.clksel = mcbsp_fck_clksel,
|
|
|
|
.recalc = &omap2_clksel_recalc,
|
2005-11-10 14:26:52 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk mcbsp3_ick = {
|
2010-02-23 05:09:19 +00:00
|
|
|
.name = "mcbsp3_ick",
|
2011-02-25 22:39:30 +00:00
|
|
|
.ops = &clkops_omap2_iclk_dflt_wait,
|
2005-11-10 14:26:52 +00:00
|
|
|
.parent = &l4_ck,
|
2008-08-19 08:08:44 +00:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 13:47:55 +00:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
|
|
|
|
.enable_bit = OMAP2430_EN_MCBSP3_SHIFT,
|
|
|
|
.recalc = &followparent_recalc,
|
2005-11-10 14:26:52 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk mcbsp3_fck = {
|
2010-02-23 05:09:19 +00:00
|
|
|
.name = "mcbsp3_fck",
|
2008-11-04 17:59:52 +00:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2005-11-10 14:26:52 +00:00
|
|
|
.parent = &func_96m_ck,
|
2010-10-08 17:40:18 +00:00
|
|
|
.init = &omap2_init_clksel_parent,
|
2008-08-19 08:08:44 +00:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 13:47:55 +00:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
|
|
|
|
.enable_bit = OMAP2430_EN_MCBSP3_SHIFT,
|
2010-10-08 17:40:18 +00:00
|
|
|
.clksel_reg = OMAP243X_CTRL_REGADDR(OMAP243X_CONTROL_DEVCONF1),
|
|
|
|
.clksel_mask = OMAP2_MCBSP3_CLKS_MASK,
|
|
|
|
.clksel = mcbsp_fck_clksel,
|
|
|
|
.recalc = &omap2_clksel_recalc,
|
2005-11-10 14:26:52 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk mcbsp4_ick = {
|
2010-02-23 05:09:19 +00:00
|
|
|
.name = "mcbsp4_ick",
|
2011-02-25 22:39:30 +00:00
|
|
|
.ops = &clkops_omap2_iclk_dflt_wait,
|
2005-11-10 14:26:52 +00:00
|
|
|
.parent = &l4_ck,
|
2008-08-19 08:08:44 +00:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 13:47:55 +00:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
|
|
|
|
.enable_bit = OMAP2430_EN_MCBSP4_SHIFT,
|
|
|
|
.recalc = &followparent_recalc,
|
2005-11-10 14:26:52 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk mcbsp4_fck = {
|
2010-02-23 05:09:19 +00:00
|
|
|
.name = "mcbsp4_fck",
|
2008-11-04 17:59:52 +00:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2005-11-10 14:26:52 +00:00
|
|
|
.parent = &func_96m_ck,
|
2010-10-08 17:40:18 +00:00
|
|
|
.init = &omap2_init_clksel_parent,
|
2008-08-19 08:08:44 +00:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 13:47:55 +00:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
|
|
|
|
.enable_bit = OMAP2430_EN_MCBSP4_SHIFT,
|
2010-10-08 17:40:18 +00:00
|
|
|
.clksel_reg = OMAP243X_CTRL_REGADDR(OMAP243X_CONTROL_DEVCONF1),
|
|
|
|
.clksel_mask = OMAP2_MCBSP4_CLKS_MASK,
|
|
|
|
.clksel = mcbsp_fck_clksel,
|
|
|
|
.recalc = &omap2_clksel_recalc,
|
2005-11-10 14:26:52 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk mcbsp5_ick = {
|
2010-02-23 05:09:19 +00:00
|
|
|
.name = "mcbsp5_ick",
|
2011-02-25 22:39:30 +00:00
|
|
|
.ops = &clkops_omap2_iclk_dflt_wait,
|
2005-11-10 14:26:52 +00:00
|
|
|
.parent = &l4_ck,
|
2008-08-19 08:08:44 +00:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 13:47:55 +00:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
|
|
|
|
.enable_bit = OMAP2430_EN_MCBSP5_SHIFT,
|
|
|
|
.recalc = &followparent_recalc,
|
2005-11-10 14:26:52 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk mcbsp5_fck = {
|
2010-02-23 05:09:19 +00:00
|
|
|
.name = "mcbsp5_fck",
|
2008-11-04 17:59:52 +00:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2005-11-10 14:26:52 +00:00
|
|
|
.parent = &func_96m_ck,
|
2010-10-08 17:40:18 +00:00
|
|
|
.init = &omap2_init_clksel_parent,
|
2008-08-19 08:08:44 +00:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 13:47:55 +00:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
|
|
|
|
.enable_bit = OMAP2430_EN_MCBSP5_SHIFT,
|
2010-10-08 17:40:18 +00:00
|
|
|
.clksel_reg = OMAP243X_CTRL_REGADDR(OMAP243X_CONTROL_DEVCONF1),
|
|
|
|
.clksel_mask = OMAP2_MCBSP5_CLKS_MASK,
|
|
|
|
.clksel = mcbsp_fck_clksel,
|
|
|
|
.recalc = &omap2_clksel_recalc,
|
2005-11-10 14:26:52 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk mcspi1_ick = {
|
2010-02-23 05:09:19 +00:00
|
|
|
.name = "mcspi1_ick",
|
2011-02-25 22:39:30 +00:00
|
|
|
.ops = &clkops_omap2_iclk_dflt_wait,
|
2005-11-10 14:26:52 +00:00
|
|
|
.parent = &l4_ck,
|
2008-08-19 08:08:44 +00:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 13:47:55 +00:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
|
|
|
|
.enable_bit = OMAP24XX_EN_MCSPI1_SHIFT,
|
|
|
|
.recalc = &followparent_recalc,
|
2005-11-10 14:26:52 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk mcspi1_fck = {
|
2010-02-23 05:09:19 +00:00
|
|
|
.name = "mcspi1_fck",
|
2008-11-04 17:59:52 +00:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2005-11-10 14:26:52 +00:00
|
|
|
.parent = &func_48m_ck,
|
2008-08-19 08:08:44 +00:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 13:47:55 +00:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
|
|
|
|
.enable_bit = OMAP24XX_EN_MCSPI1_SHIFT,
|
|
|
|
.recalc = &followparent_recalc,
|
2005-11-10 14:26:52 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk mcspi2_ick = {
|
2010-02-23 05:09:19 +00:00
|
|
|
.name = "mcspi2_ick",
|
2011-02-25 22:39:30 +00:00
|
|
|
.ops = &clkops_omap2_iclk_dflt_wait,
|
2005-11-10 14:26:52 +00:00
|
|
|
.parent = &l4_ck,
|
2008-08-19 08:08:44 +00:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 13:47:55 +00:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
|
|
|
|
.enable_bit = OMAP24XX_EN_MCSPI2_SHIFT,
|
|
|
|
.recalc = &followparent_recalc,
|
2005-11-10 14:26:52 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk mcspi2_fck = {
|
2010-02-23 05:09:19 +00:00
|
|
|
.name = "mcspi2_fck",
|
2008-11-04 17:59:52 +00:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2005-11-10 14:26:52 +00:00
|
|
|
.parent = &func_48m_ck,
|
2008-08-19 08:08:44 +00:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 13:47:55 +00:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
|
|
|
|
.enable_bit = OMAP24XX_EN_MCSPI2_SHIFT,
|
|
|
|
.recalc = &followparent_recalc,
|
2005-11-10 14:26:52 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk mcspi3_ick = {
|
2010-02-23 05:09:19 +00:00
|
|
|
.name = "mcspi3_ick",
|
2011-02-25 22:39:30 +00:00
|
|
|
.ops = &clkops_omap2_iclk_dflt_wait,
|
2005-11-10 14:26:52 +00:00
|
|
|
.parent = &l4_ck,
|
2008-08-19 08:08:44 +00:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 13:47:55 +00:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
|
|
|
|
.enable_bit = OMAP2430_EN_MCSPI3_SHIFT,
|
|
|
|
.recalc = &followparent_recalc,
|
2005-11-10 14:26:52 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk mcspi3_fck = {
|
2010-02-23 05:09:19 +00:00
|
|
|
.name = "mcspi3_fck",
|
2008-11-04 17:59:52 +00:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2005-11-10 14:26:52 +00:00
|
|
|
.parent = &func_48m_ck,
|
2008-08-19 08:08:44 +00:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 13:47:55 +00:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
|
|
|
|
.enable_bit = OMAP2430_EN_MCSPI3_SHIFT,
|
|
|
|
.recalc = &followparent_recalc,
|
2005-11-10 14:26:52 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk uart1_ick = {
|
|
|
|
.name = "uart1_ick",
|
2011-02-25 22:39:30 +00:00
|
|
|
.ops = &clkops_omap2_iclk_dflt_wait,
|
2005-11-10 14:26:52 +00:00
|
|
|
.parent = &l4_ck,
|
2008-08-19 08:08:44 +00:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 13:47:55 +00:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
|
|
|
|
.enable_bit = OMAP24XX_EN_UART1_SHIFT,
|
|
|
|
.recalc = &followparent_recalc,
|
2005-11-10 14:26:52 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk uart1_fck = {
|
|
|
|
.name = "uart1_fck",
|
2008-11-04 17:59:52 +00:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2005-11-10 14:26:52 +00:00
|
|
|
.parent = &func_48m_ck,
|
2008-08-19 08:08:44 +00:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 13:47:55 +00:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
|
|
|
|
.enable_bit = OMAP24XX_EN_UART1_SHIFT,
|
|
|
|
.recalc = &followparent_recalc,
|
2005-11-10 14:26:52 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk uart2_ick = {
|
|
|
|
.name = "uart2_ick",
|
2011-02-25 22:39:30 +00:00
|
|
|
.ops = &clkops_omap2_iclk_dflt_wait,
|
2005-11-10 14:26:52 +00:00
|
|
|
.parent = &l4_ck,
|
2008-08-19 08:08:44 +00:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 13:47:55 +00:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
|
|
|
|
.enable_bit = OMAP24XX_EN_UART2_SHIFT,
|
|
|
|
.recalc = &followparent_recalc,
|
2005-11-10 14:26:52 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk uart2_fck = {
|
|
|
|
.name = "uart2_fck",
|
2008-11-04 17:59:52 +00:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2005-11-10 14:26:52 +00:00
|
|
|
.parent = &func_48m_ck,
|
2008-08-19 08:08:44 +00:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 13:47:55 +00:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
|
|
|
|
.enable_bit = OMAP24XX_EN_UART2_SHIFT,
|
|
|
|
.recalc = &followparent_recalc,
|
2005-11-10 14:26:52 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk uart3_ick = {
|
|
|
|
.name = "uart3_ick",
|
2011-02-25 22:39:30 +00:00
|
|
|
.ops = &clkops_omap2_iclk_dflt_wait,
|
2005-11-10 14:26:52 +00:00
|
|
|
.parent = &l4_ck,
|
2008-08-19 08:08:44 +00:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 13:47:55 +00:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
|
|
|
|
.enable_bit = OMAP24XX_EN_UART3_SHIFT,
|
|
|
|
.recalc = &followparent_recalc,
|
2005-11-10 14:26:52 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk uart3_fck = {
|
|
|
|
.name = "uart3_fck",
|
2008-11-04 17:59:52 +00:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2005-11-10 14:26:52 +00:00
|
|
|
.parent = &func_48m_ck,
|
2008-08-19 08:08:44 +00:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 13:47:55 +00:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
|
|
|
|
.enable_bit = OMAP24XX_EN_UART3_SHIFT,
|
|
|
|
.recalc = &followparent_recalc,
|
2005-11-10 14:26:52 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk gpios_ick = {
|
|
|
|
.name = "gpios_ick",
|
2011-02-25 22:39:30 +00:00
|
|
|
.ops = &clkops_omap2_iclk_dflt_wait,
|
OMAP2xxx: clock: fix interface clocks and clockdomains for modules in the WKUP domain
The parent of the interface clocks for GPTIMER1, MPU_WDT,
SYNCTIMER_32K, SCM, WDT1, and the ICR (2430 only) were all listed as
being l4_ck. This isn't accurate; these modules exist inside the WKUP
domain, and the interface clock to these modules runs at the SYS_CLK
rate rather than the CORE L4 rate.
So, create a new clock "wu_l4_ick", similar to the OMAP3
"wkup_l4_ick", that serves as the parent for these clocks.
Also, these clocks were listed as existing inside core_l4_clkdm;
wkup_clkdm is probably more accurate.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
2011-02-16 22:38:38 +00:00
|
|
|
.parent = &wu_l4_ick,
|
|
|
|
.clkdm_name = "wkup_clkdm",
|
2008-03-18 13:47:55 +00:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
|
|
|
|
.enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
|
|
|
|
.recalc = &followparent_recalc,
|
2005-11-10 14:26:52 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk gpios_fck = {
|
|
|
|
.name = "gpios_fck",
|
2008-11-04 17:59:52 +00:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2005-11-10 14:26:52 +00:00
|
|
|
.parent = &func_32k_ck,
|
2008-08-19 08:08:44 +00:00
|
|
|
.clkdm_name = "wkup_clkdm",
|
2008-03-18 13:47:55 +00:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
|
|
|
|
.enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
|
|
|
|
.recalc = &followparent_recalc,
|
2005-11-10 14:26:52 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk mpu_wdt_ick = {
|
|
|
|
.name = "mpu_wdt_ick",
|
2011-02-25 22:39:30 +00:00
|
|
|
.ops = &clkops_omap2_iclk_dflt_wait,
|
OMAP2xxx: clock: fix interface clocks and clockdomains for modules in the WKUP domain
The parent of the interface clocks for GPTIMER1, MPU_WDT,
SYNCTIMER_32K, SCM, WDT1, and the ICR (2430 only) were all listed as
being l4_ck. This isn't accurate; these modules exist inside the WKUP
domain, and the interface clock to these modules runs at the SYS_CLK
rate rather than the CORE L4 rate.
So, create a new clock "wu_l4_ick", similar to the OMAP3
"wkup_l4_ick", that serves as the parent for these clocks.
Also, these clocks were listed as existing inside core_l4_clkdm;
wkup_clkdm is probably more accurate.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
2011-02-16 22:38:38 +00:00
|
|
|
.parent = &wu_l4_ick,
|
|
|
|
.clkdm_name = "wkup_clkdm",
|
2008-03-18 13:47:55 +00:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
|
|
|
|
.enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
|
|
|
|
.recalc = &followparent_recalc,
|
2005-11-10 14:26:52 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk mpu_wdt_fck = {
|
|
|
|
.name = "mpu_wdt_fck",
|
2008-11-04 17:59:52 +00:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2005-11-10 14:26:52 +00:00
|
|
|
.parent = &func_32k_ck,
|
2008-08-19 08:08:44 +00:00
|
|
|
.clkdm_name = "wkup_clkdm",
|
2008-03-18 13:47:55 +00:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
|
|
|
|
.enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
|
|
|
|
.recalc = &followparent_recalc,
|
2005-11-10 14:26:52 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk sync_32k_ick = {
|
|
|
|
.name = "sync_32k_ick",
|
2011-02-25 22:39:30 +00:00
|
|
|
.ops = &clkops_omap2_iclk_dflt_wait,
|
2009-01-19 15:27:29 +00:00
|
|
|
.flags = ENABLE_ON_INIT,
|
OMAP2xxx: clock: fix interface clocks and clockdomains for modules in the WKUP domain
The parent of the interface clocks for GPTIMER1, MPU_WDT,
SYNCTIMER_32K, SCM, WDT1, and the ICR (2430 only) were all listed as
being l4_ck. This isn't accurate; these modules exist inside the WKUP
domain, and the interface clock to these modules runs at the SYS_CLK
rate rather than the CORE L4 rate.
So, create a new clock "wu_l4_ick", similar to the OMAP3
"wkup_l4_ick", that serves as the parent for these clocks.
Also, these clocks were listed as existing inside core_l4_clkdm;
wkup_clkdm is probably more accurate.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
2011-02-16 22:38:38 +00:00
|
|
|
.parent = &wu_l4_ick,
|
|
|
|
.clkdm_name = "wkup_clkdm",
|
2008-03-18 13:47:55 +00:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
|
|
|
|
.enable_bit = OMAP24XX_EN_32KSYNC_SHIFT,
|
|
|
|
.recalc = &followparent_recalc,
|
2005-11-10 14:26:52 +00:00
|
|
|
};
|
2008-08-19 08:08:44 +00:00
|
|
|
|
2005-11-10 14:26:52 +00:00
|
|
|
static struct clk wdt1_ick = {
|
|
|
|
.name = "wdt1_ick",
|
2011-02-25 22:39:30 +00:00
|
|
|
.ops = &clkops_omap2_iclk_dflt_wait,
|
OMAP2xxx: clock: fix interface clocks and clockdomains for modules in the WKUP domain
The parent of the interface clocks for GPTIMER1, MPU_WDT,
SYNCTIMER_32K, SCM, WDT1, and the ICR (2430 only) were all listed as
being l4_ck. This isn't accurate; these modules exist inside the WKUP
domain, and the interface clock to these modules runs at the SYS_CLK
rate rather than the CORE L4 rate.
So, create a new clock "wu_l4_ick", similar to the OMAP3
"wkup_l4_ick", that serves as the parent for these clocks.
Also, these clocks were listed as existing inside core_l4_clkdm;
wkup_clkdm is probably more accurate.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
2011-02-16 22:38:38 +00:00
|
|
|
.parent = &wu_l4_ick,
|
|
|
|
.clkdm_name = "wkup_clkdm",
|
2008-03-18 13:47:55 +00:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
|
|
|
|
.enable_bit = OMAP24XX_EN_WDT1_SHIFT,
|
|
|
|
.recalc = &followparent_recalc,
|
2005-11-10 14:26:52 +00:00
|
|
|
};
|
2008-08-19 08:08:44 +00:00
|
|
|
|
2005-11-10 14:26:52 +00:00
|
|
|
static struct clk omapctrl_ick = {
|
|
|
|
.name = "omapctrl_ick",
|
2011-02-25 22:39:30 +00:00
|
|
|
.ops = &clkops_omap2_iclk_dflt_wait,
|
2009-01-19 15:27:29 +00:00
|
|
|
.flags = ENABLE_ON_INIT,
|
OMAP2xxx: clock: fix interface clocks and clockdomains for modules in the WKUP domain
The parent of the interface clocks for GPTIMER1, MPU_WDT,
SYNCTIMER_32K, SCM, WDT1, and the ICR (2430 only) were all listed as
being l4_ck. This isn't accurate; these modules exist inside the WKUP
domain, and the interface clock to these modules runs at the SYS_CLK
rate rather than the CORE L4 rate.
So, create a new clock "wu_l4_ick", similar to the OMAP3
"wkup_l4_ick", that serves as the parent for these clocks.
Also, these clocks were listed as existing inside core_l4_clkdm;
wkup_clkdm is probably more accurate.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
2011-02-16 22:38:38 +00:00
|
|
|
.parent = &wu_l4_ick,
|
|
|
|
.clkdm_name = "wkup_clkdm",
|
2008-03-18 13:47:55 +00:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
|
|
|
|
.enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT,
|
|
|
|
.recalc = &followparent_recalc,
|
2005-11-10 14:26:52 +00:00
|
|
|
};
|
2008-08-19 08:08:44 +00:00
|
|
|
|
2005-11-10 14:26:52 +00:00
|
|
|
static struct clk icr_ick = {
|
|
|
|
.name = "icr_ick",
|
2011-02-25 22:39:30 +00:00
|
|
|
.ops = &clkops_omap2_iclk_dflt_wait,
|
OMAP2xxx: clock: fix interface clocks and clockdomains for modules in the WKUP domain
The parent of the interface clocks for GPTIMER1, MPU_WDT,
SYNCTIMER_32K, SCM, WDT1, and the ICR (2430 only) were all listed as
being l4_ck. This isn't accurate; these modules exist inside the WKUP
domain, and the interface clock to these modules runs at the SYS_CLK
rate rather than the CORE L4 rate.
So, create a new clock "wu_l4_ick", similar to the OMAP3
"wkup_l4_ick", that serves as the parent for these clocks.
Also, these clocks were listed as existing inside core_l4_clkdm;
wkup_clkdm is probably more accurate.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
2011-02-16 22:38:38 +00:00
|
|
|
.parent = &wu_l4_ick,
|
|
|
|
.clkdm_name = "wkup_clkdm",
|
2008-03-18 13:47:55 +00:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
|
|
|
|
.enable_bit = OMAP2430_EN_ICR_SHIFT,
|
|
|
|
.recalc = &followparent_recalc,
|
2005-11-10 14:26:52 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk cam_ick = {
|
|
|
|
.name = "cam_ick",
|
2011-02-25 22:39:30 +00:00
|
|
|
.ops = &clkops_omap2_iclk_dflt,
|
2005-11-10 14:26:52 +00:00
|
|
|
.parent = &l4_ck,
|
2008-08-19 08:08:44 +00:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 13:47:55 +00:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
|
|
|
|
.enable_bit = OMAP24XX_EN_CAM_SHIFT,
|
|
|
|
.recalc = &followparent_recalc,
|
2005-11-10 14:26:52 +00:00
|
|
|
};
|
|
|
|
|
2008-08-19 08:08:44 +00:00
|
|
|
/*
|
|
|
|
* cam_fck controls both CAM_MCLK and CAM_FCLK. It should probably be
|
|
|
|
* split into two separate clocks, since the parent clocks are different
|
|
|
|
* and the clockdomains are also different.
|
|
|
|
*/
|
2005-11-10 14:26:52 +00:00
|
|
|
static struct clk cam_fck = {
|
|
|
|
.name = "cam_fck",
|
2008-11-04 18:59:32 +00:00
|
|
|
.ops = &clkops_omap2_dflt,
|
2005-11-10 14:26:52 +00:00
|
|
|
.parent = &func_96m_ck,
|
2008-08-19 08:08:44 +00:00
|
|
|
.clkdm_name = "core_l3_clkdm",
|
2008-03-18 13:47:55 +00:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
|
|
|
|
.enable_bit = OMAP24XX_EN_CAM_SHIFT,
|
|
|
|
.recalc = &followparent_recalc,
|
2005-11-10 14:26:52 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk mailboxes_ick = {
|
|
|
|
.name = "mailboxes_ick",
|
2011-02-25 22:39:30 +00:00
|
|
|
.ops = &clkops_omap2_iclk_dflt_wait,
|
2005-11-10 14:26:52 +00:00
|
|
|
.parent = &l4_ck,
|
2008-08-19 08:08:44 +00:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 13:47:55 +00:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
|
|
|
|
.enable_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
|
|
|
|
.recalc = &followparent_recalc,
|
2005-11-10 14:26:52 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk wdt4_ick = {
|
|
|
|
.name = "wdt4_ick",
|
2011-02-25 22:39:30 +00:00
|
|
|
.ops = &clkops_omap2_iclk_dflt_wait,
|
2005-11-10 14:26:52 +00:00
|
|
|
.parent = &l4_ck,
|
2008-08-19 08:08:44 +00:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 13:47:55 +00:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
|
|
|
|
.enable_bit = OMAP24XX_EN_WDT4_SHIFT,
|
|
|
|
.recalc = &followparent_recalc,
|
2005-11-10 14:26:52 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk wdt4_fck = {
|
|
|
|
.name = "wdt4_fck",
|
2008-11-04 17:59:52 +00:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2005-11-10 14:26:52 +00:00
|
|
|
.parent = &func_32k_ck,
|
2008-08-19 08:08:44 +00:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 13:47:55 +00:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
|
|
|
|
.enable_bit = OMAP24XX_EN_WDT4_SHIFT,
|
|
|
|
.recalc = &followparent_recalc,
|
2005-11-10 14:26:52 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk mspro_ick = {
|
|
|
|
.name = "mspro_ick",
|
2011-02-25 22:39:30 +00:00
|
|
|
.ops = &clkops_omap2_iclk_dflt_wait,
|
2005-11-10 14:26:52 +00:00
|
|
|
.parent = &l4_ck,
|
2008-08-19 08:08:44 +00:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 13:47:55 +00:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
|
|
|
|
.enable_bit = OMAP24XX_EN_MSPRO_SHIFT,
|
|
|
|
.recalc = &followparent_recalc,
|
2005-11-10 14:26:52 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk mspro_fck = {
|
|
|
|
.name = "mspro_fck",
|
2008-11-04 17:59:52 +00:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2005-11-10 14:26:52 +00:00
|
|
|
.parent = &func_96m_ck,
|
2008-08-19 08:08:44 +00:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 13:47:55 +00:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
|
|
|
|
.enable_bit = OMAP24XX_EN_MSPRO_SHIFT,
|
|
|
|
.recalc = &followparent_recalc,
|
2005-11-10 14:26:52 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk fac_ick = {
|
|
|
|
.name = "fac_ick",
|
2011-02-25 22:39:30 +00:00
|
|
|
.ops = &clkops_omap2_iclk_dflt_wait,
|
2005-11-10 14:26:52 +00:00
|
|
|
.parent = &l4_ck,
|
2008-08-19 08:08:44 +00:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 13:47:55 +00:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
|
|
|
|
.enable_bit = OMAP24XX_EN_FAC_SHIFT,
|
|
|
|
.recalc = &followparent_recalc,
|
2005-11-10 14:26:52 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk fac_fck = {
|
|
|
|
.name = "fac_fck",
|
2008-11-04 17:59:52 +00:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2005-11-10 14:26:52 +00:00
|
|
|
.parent = &func_12m_ck,
|
2008-08-19 08:08:44 +00:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 13:47:55 +00:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
|
|
|
|
.enable_bit = OMAP24XX_EN_FAC_SHIFT,
|
|
|
|
.recalc = &followparent_recalc,
|
2005-11-10 14:26:52 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk hdq_ick = {
|
|
|
|
.name = "hdq_ick",
|
2011-02-25 22:39:30 +00:00
|
|
|
.ops = &clkops_omap2_iclk_dflt_wait,
|
2005-11-10 14:26:52 +00:00
|
|
|
.parent = &l4_ck,
|
2008-08-19 08:08:44 +00:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 13:47:55 +00:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
|
|
|
|
.enable_bit = OMAP24XX_EN_HDQ_SHIFT,
|
|
|
|
.recalc = &followparent_recalc,
|
2005-11-10 14:26:52 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk hdq_fck = {
|
|
|
|
.name = "hdq_fck",
|
2008-11-04 17:59:52 +00:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2005-11-10 14:26:52 +00:00
|
|
|
.parent = &func_12m_ck,
|
2008-08-19 08:08:44 +00:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 13:47:55 +00:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
|
|
|
|
.enable_bit = OMAP24XX_EN_HDQ_SHIFT,
|
|
|
|
.recalc = &followparent_recalc,
|
2005-11-10 14:26:52 +00:00
|
|
|
};
|
|
|
|
|
OMAP2 clock: split OMAP2420, OMAP2430 clock data into their own files
In preparation for multi-OMAP2 kernels, split
mach-omap2/clock2xxx_data.c into mach-omap2/clock2420_data.c and
mach-omap2/clock2430_data.c. 2430 uses a different device space
physical memory layout than past or future OMAPs, and we use a
different virtual memory layout as well, which causes trouble for
architecture-level code/data that tries to support both. We tried
using offsets from the virtual base last year, but those patches never
made it upstream; so after some discussion with Tony about the best
all-around approach, we'll just grit our teeth and duplicate the
structures. The maintenance advantages of a single kernel config that
can compile and boot on OMAP2, 3, and 4 platforms are simply too
compelling.
This approach does have some nice benefits beyond multi-OMAP 2 kernel
support. The runtime size of OMAP2420-specific and OMAP2430-specific
kernels is smaller, since unused clocks for the other OMAP2 chip will
no longer be compiled in. (At some point we will mark the clock data
__initdata and allocate it during registration, which will eliminate
the runtime memory advantage.) It also makes the clock trees slightly
easier to read, since 2420-specific and 2430-specific clocks are no
longer mixed together.
This patch also splits 2430-specific clock code into its own file,
mach-omap2/clock2430.c, which is only compiled in for 2430 builds -
mostly for organizational clarity.
While here, fix a bug in the OMAP2430 clock tree: "emul_ck" was
incorrectly marked as being 2420-only, when actually it is present on
both OMAP2420 and OMAP2430.
Thanks to Tony for some good discussions about how to approach this
problem.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Richard Woodruff <r-woodruff2@ti.com>
2010-02-23 05:09:22 +00:00
|
|
|
/*
|
|
|
|
* XXX This is marked as a 2420-only define, but it claims to be present
|
|
|
|
* on 2430 also. Double-check.
|
|
|
|
*/
|
2005-11-10 14:26:52 +00:00
|
|
|
static struct clk i2c2_ick = {
|
2010-02-23 05:09:19 +00:00
|
|
|
.name = "i2c2_ick",
|
2011-02-25 22:39:30 +00:00
|
|
|
.ops = &clkops_omap2_iclk_dflt_wait,
|
2005-11-10 14:26:52 +00:00
|
|
|
.parent = &l4_ck,
|
2008-08-19 08:08:44 +00:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 13:47:55 +00:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
|
|
|
|
.enable_bit = OMAP2420_EN_I2C2_SHIFT,
|
|
|
|
.recalc = &followparent_recalc,
|
2005-11-10 14:26:52 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk i2chs2_fck = {
|
2010-02-23 05:09:19 +00:00
|
|
|
.name = "i2chs2_fck",
|
2009-07-25 01:44:04 +00:00
|
|
|
.ops = &clkops_omap2430_i2chs_wait,
|
2005-11-10 14:26:52 +00:00
|
|
|
.parent = &func_96m_ck,
|
2008-08-19 08:08:44 +00:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 13:47:55 +00:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
|
|
|
|
.enable_bit = OMAP2430_EN_I2CHS2_SHIFT,
|
|
|
|
.recalc = &followparent_recalc,
|
2005-11-10 14:26:52 +00:00
|
|
|
};
|
|
|
|
|
OMAP2 clock: split OMAP2420, OMAP2430 clock data into their own files
In preparation for multi-OMAP2 kernels, split
mach-omap2/clock2xxx_data.c into mach-omap2/clock2420_data.c and
mach-omap2/clock2430_data.c. 2430 uses a different device space
physical memory layout than past or future OMAPs, and we use a
different virtual memory layout as well, which causes trouble for
architecture-level code/data that tries to support both. We tried
using offsets from the virtual base last year, but those patches never
made it upstream; so after some discussion with Tony about the best
all-around approach, we'll just grit our teeth and duplicate the
structures. The maintenance advantages of a single kernel config that
can compile and boot on OMAP2, 3, and 4 platforms are simply too
compelling.
This approach does have some nice benefits beyond multi-OMAP 2 kernel
support. The runtime size of OMAP2420-specific and OMAP2430-specific
kernels is smaller, since unused clocks for the other OMAP2 chip will
no longer be compiled in. (At some point we will mark the clock data
__initdata and allocate it during registration, which will eliminate
the runtime memory advantage.) It also makes the clock trees slightly
easier to read, since 2420-specific and 2430-specific clocks are no
longer mixed together.
This patch also splits 2430-specific clock code into its own file,
mach-omap2/clock2430.c, which is only compiled in for 2430 builds -
mostly for organizational clarity.
While here, fix a bug in the OMAP2430 clock tree: "emul_ck" was
incorrectly marked as being 2420-only, when actually it is present on
both OMAP2420 and OMAP2430.
Thanks to Tony for some good discussions about how to approach this
problem.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Richard Woodruff <r-woodruff2@ti.com>
2010-02-23 05:09:22 +00:00
|
|
|
/*
|
|
|
|
* XXX This is marked as a 2420-only define, but it claims to be present
|
|
|
|
* on 2430 also. Double-check.
|
|
|
|
*/
|
2005-11-10 14:26:52 +00:00
|
|
|
static struct clk i2c1_ick = {
|
2010-02-23 05:09:19 +00:00
|
|
|
.name = "i2c1_ick",
|
2011-02-25 22:39:30 +00:00
|
|
|
.ops = &clkops_omap2_iclk_dflt_wait,
|
2005-11-10 14:26:52 +00:00
|
|
|
.parent = &l4_ck,
|
2008-08-19 08:08:44 +00:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 13:47:55 +00:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
|
|
|
|
.enable_bit = OMAP2420_EN_I2C1_SHIFT,
|
|
|
|
.recalc = &followparent_recalc,
|
2005-11-10 14:26:52 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk i2chs1_fck = {
|
2010-02-23 05:09:19 +00:00
|
|
|
.name = "i2chs1_fck",
|
2009-07-25 01:44:04 +00:00
|
|
|
.ops = &clkops_omap2430_i2chs_wait,
|
2005-11-10 14:26:52 +00:00
|
|
|
.parent = &func_96m_ck,
|
2008-08-19 08:08:44 +00:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 13:47:55 +00:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
|
|
|
|
.enable_bit = OMAP2430_EN_I2CHS1_SHIFT,
|
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
2011-02-25 22:39:30 +00:00
|
|
|
/*
|
|
|
|
* The enable_reg/enable_bit in this clock is only used for CM_AUTOIDLE
|
|
|
|
* accesses derived from this data.
|
|
|
|
*/
|
2008-03-18 13:47:55 +00:00
|
|
|
static struct clk gpmc_fck = {
|
|
|
|
.name = "gpmc_fck",
|
2011-02-25 22:39:30 +00:00
|
|
|
.ops = &clkops_omap2_iclk_idle_only,
|
2008-03-18 13:47:55 +00:00
|
|
|
.parent = &core_l3_ck,
|
2009-01-19 15:27:29 +00:00
|
|
|
.flags = ENABLE_ON_INIT,
|
2008-08-19 08:08:44 +00:00
|
|
|
.clkdm_name = "core_l3_clkdm",
|
2011-02-25 22:39:30 +00:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
|
|
|
|
.enable_bit = OMAP24XX_AUTO_GPMC_SHIFT,
|
2008-03-18 13:47:55 +00:00
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk sdma_fck = {
|
|
|
|
.name = "sdma_fck",
|
2008-11-04 16:35:03 +00:00
|
|
|
.ops = &clkops_null, /* RMK: missing? */
|
2008-03-18 13:47:55 +00:00
|
|
|
.parent = &core_l3_ck,
|
2008-08-19 08:08:44 +00:00
|
|
|
.clkdm_name = "core_l3_clkdm",
|
2008-03-18 13:47:55 +00:00
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
2011-02-25 22:39:30 +00:00
|
|
|
/*
|
|
|
|
* The enable_reg/enable_bit in this clock is only used for CM_AUTOIDLE
|
|
|
|
* accesses derived from this data.
|
|
|
|
*/
|
2008-03-18 13:47:55 +00:00
|
|
|
static struct clk sdma_ick = {
|
|
|
|
.name = "sdma_ick",
|
2011-02-25 22:39:30 +00:00
|
|
|
.ops = &clkops_omap2_iclk_idle_only,
|
2011-02-25 22:51:02 +00:00
|
|
|
.parent = &core_l3_ck,
|
2008-08-19 08:08:44 +00:00
|
|
|
.clkdm_name = "core_l3_clkdm",
|
2011-02-25 22:39:30 +00:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
|
|
|
|
.enable_bit = OMAP24XX_AUTO_SDMA_SHIFT,
|
2008-03-18 13:47:55 +00:00
|
|
|
.recalc = &followparent_recalc,
|
2005-11-10 14:26:52 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk sdrc_ick = {
|
|
|
|
.name = "sdrc_ick",
|
2011-02-25 22:39:30 +00:00
|
|
|
.ops = &clkops_omap2_iclk_idle_only,
|
2011-02-25 22:51:02 +00:00
|
|
|
.parent = &core_l3_ck,
|
2009-01-19 15:27:29 +00:00
|
|
|
.flags = ENABLE_ON_INIT,
|
2011-02-25 22:51:02 +00:00
|
|
|
.clkdm_name = "core_l3_clkdm",
|
2008-03-18 13:47:55 +00:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
|
|
|
|
.enable_bit = OMAP2430_EN_SDRC_SHIFT,
|
|
|
|
.recalc = &followparent_recalc,
|
2005-11-10 14:26:52 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk des_ick = {
|
|
|
|
.name = "des_ick",
|
2011-02-25 22:39:30 +00:00
|
|
|
.ops = &clkops_omap2_iclk_dflt_wait,
|
2005-11-10 14:26:52 +00:00
|
|
|
.parent = &l4_ck,
|
2008-08-19 08:08:44 +00:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 13:47:55 +00:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
|
|
|
|
.enable_bit = OMAP24XX_EN_DES_SHIFT,
|
|
|
|
.recalc = &followparent_recalc,
|
2005-11-10 14:26:52 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk sha_ick = {
|
|
|
|
.name = "sha_ick",
|
2011-02-25 22:39:30 +00:00
|
|
|
.ops = &clkops_omap2_iclk_dflt_wait,
|
2005-11-10 14:26:52 +00:00
|
|
|
.parent = &l4_ck,
|
2008-08-19 08:08:44 +00:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 13:47:55 +00:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
|
|
|
|
.enable_bit = OMAP24XX_EN_SHA_SHIFT,
|
|
|
|
.recalc = &followparent_recalc,
|
2005-11-10 14:26:52 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk rng_ick = {
|
|
|
|
.name = "rng_ick",
|
2011-02-25 22:39:30 +00:00
|
|
|
.ops = &clkops_omap2_iclk_dflt_wait,
|
2005-11-10 14:26:52 +00:00
|
|
|
.parent = &l4_ck,
|
2008-08-19 08:08:44 +00:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 13:47:55 +00:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
|
|
|
|
.enable_bit = OMAP24XX_EN_RNG_SHIFT,
|
|
|
|
.recalc = &followparent_recalc,
|
2005-11-10 14:26:52 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk aes_ick = {
|
|
|
|
.name = "aes_ick",
|
2011-02-25 22:39:30 +00:00
|
|
|
.ops = &clkops_omap2_iclk_dflt_wait,
|
2005-11-10 14:26:52 +00:00
|
|
|
.parent = &l4_ck,
|
2008-08-19 08:08:44 +00:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 13:47:55 +00:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
|
|
|
|
.enable_bit = OMAP24XX_EN_AES_SHIFT,
|
|
|
|
.recalc = &followparent_recalc,
|
2005-11-10 14:26:52 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk pka_ick = {
|
|
|
|
.name = "pka_ick",
|
2011-02-25 22:39:30 +00:00
|
|
|
.ops = &clkops_omap2_iclk_dflt_wait,
|
2005-11-10 14:26:52 +00:00
|
|
|
.parent = &l4_ck,
|
2008-08-19 08:08:44 +00:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 13:47:55 +00:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
|
|
|
|
.enable_bit = OMAP24XX_EN_PKA_SHIFT,
|
|
|
|
.recalc = &followparent_recalc,
|
2005-11-10 14:26:52 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk usb_fck = {
|
|
|
|
.name = "usb_fck",
|
2008-11-04 17:59:52 +00:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2005-11-10 14:26:52 +00:00
|
|
|
.parent = &func_48m_ck,
|
2008-08-19 08:08:44 +00:00
|
|
|
.clkdm_name = "core_l3_clkdm",
|
2008-03-18 13:47:55 +00:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
|
|
|
|
.enable_bit = OMAP24XX_EN_USB_SHIFT,
|
|
|
|
.recalc = &followparent_recalc,
|
2005-11-10 14:26:52 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk usbhs_ick = {
|
|
|
|
.name = "usbhs_ick",
|
2011-02-25 22:39:30 +00:00
|
|
|
.ops = &clkops_omap2_iclk_dflt_wait,
|
2006-01-17 23:31:18 +00:00
|
|
|
.parent = &core_l3_ck,
|
2008-08-19 08:08:44 +00:00
|
|
|
.clkdm_name = "core_l3_clkdm",
|
2008-03-18 13:47:55 +00:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
|
|
|
|
.enable_bit = OMAP2430_EN_USBHS_SHIFT,
|
|
|
|
.recalc = &followparent_recalc,
|
2005-11-10 14:26:52 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk mmchs1_ick = {
|
2010-02-23 05:09:19 +00:00
|
|
|
.name = "mmchs1_ick",
|
2011-02-25 22:39:30 +00:00
|
|
|
.ops = &clkops_omap2_iclk_dflt_wait,
|
2005-11-10 14:26:52 +00:00
|
|
|
.parent = &l4_ck,
|
2008-08-19 08:08:44 +00:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 13:47:55 +00:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
|
|
|
|
.enable_bit = OMAP2430_EN_MMCHS1_SHIFT,
|
|
|
|
.recalc = &followparent_recalc,
|
2005-11-10 14:26:52 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk mmchs1_fck = {
|
2010-02-23 05:09:19 +00:00
|
|
|
.name = "mmchs1_fck",
|
2008-11-04 17:59:52 +00:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2005-11-10 14:26:52 +00:00
|
|
|
.parent = &func_96m_ck,
|
2011-02-25 21:53:40 +00:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 13:47:55 +00:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
|
|
|
|
.enable_bit = OMAP2430_EN_MMCHS1_SHIFT,
|
|
|
|
.recalc = &followparent_recalc,
|
2005-11-10 14:26:52 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk mmchs2_ick = {
|
2010-02-23 05:09:19 +00:00
|
|
|
.name = "mmchs2_ick",
|
2011-02-25 22:39:30 +00:00
|
|
|
.ops = &clkops_omap2_iclk_dflt_wait,
|
2005-11-10 14:26:52 +00:00
|
|
|
.parent = &l4_ck,
|
2008-08-19 08:08:44 +00:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 13:47:55 +00:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
|
|
|
|
.enable_bit = OMAP2430_EN_MMCHS2_SHIFT,
|
|
|
|
.recalc = &followparent_recalc,
|
2005-11-10 14:26:52 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk mmchs2_fck = {
|
2010-02-23 05:09:19 +00:00
|
|
|
.name = "mmchs2_fck",
|
2008-11-04 17:59:52 +00:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2005-11-10 14:26:52 +00:00
|
|
|
.parent = &func_96m_ck,
|
2011-02-25 21:53:40 +00:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 13:47:55 +00:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
|
|
|
|
.enable_bit = OMAP2430_EN_MMCHS2_SHIFT,
|
|
|
|
.recalc = &followparent_recalc,
|
2005-11-10 14:26:52 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk gpio5_ick = {
|
|
|
|
.name = "gpio5_ick",
|
2011-02-25 22:39:30 +00:00
|
|
|
.ops = &clkops_omap2_iclk_dflt_wait,
|
2005-11-10 14:26:52 +00:00
|
|
|
.parent = &l4_ck,
|
2008-08-19 08:08:44 +00:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 13:47:55 +00:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
|
|
|
|
.enable_bit = OMAP2430_EN_GPIO5_SHIFT,
|
|
|
|
.recalc = &followparent_recalc,
|
2005-11-10 14:26:52 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk gpio5_fck = {
|
|
|
|
.name = "gpio5_fck",
|
2008-11-04 17:59:52 +00:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2005-11-10 14:26:52 +00:00
|
|
|
.parent = &func_32k_ck,
|
2008-08-19 08:08:44 +00:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 13:47:55 +00:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
|
|
|
|
.enable_bit = OMAP2430_EN_GPIO5_SHIFT,
|
|
|
|
.recalc = &followparent_recalc,
|
2005-11-10 14:26:52 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk mdm_intc_ick = {
|
|
|
|
.name = "mdm_intc_ick",
|
2011-02-25 22:39:30 +00:00
|
|
|
.ops = &clkops_omap2_iclk_dflt_wait,
|
2005-11-10 14:26:52 +00:00
|
|
|
.parent = &l4_ck,
|
2008-08-19 08:08:44 +00:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 13:47:55 +00:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
|
|
|
|
.enable_bit = OMAP2430_EN_MDM_INTC_SHIFT,
|
|
|
|
.recalc = &followparent_recalc,
|
2005-11-10 14:26:52 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk mmchsdb1_fck = {
|
2010-02-23 05:09:19 +00:00
|
|
|
.name = "mmchsdb1_fck",
|
2008-11-04 17:59:52 +00:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2005-11-10 14:26:52 +00:00
|
|
|
.parent = &func_32k_ck,
|
2008-08-19 08:08:44 +00:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 13:47:55 +00:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
|
|
|
|
.enable_bit = OMAP2430_EN_MMCHSDB1_SHIFT,
|
|
|
|
.recalc = &followparent_recalc,
|
2005-11-10 14:26:52 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk mmchsdb2_fck = {
|
2010-02-23 05:09:19 +00:00
|
|
|
.name = "mmchsdb2_fck",
|
2008-11-04 17:59:52 +00:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2005-11-10 14:26:52 +00:00
|
|
|
.parent = &func_32k_ck,
|
2008-08-19 08:08:44 +00:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 13:47:55 +00:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
|
|
|
|
.enable_bit = OMAP2430_EN_MMCHSDB2_SHIFT,
|
|
|
|
.recalc = &followparent_recalc,
|
2005-11-10 14:26:52 +00:00
|
|
|
};
|
2008-03-18 13:47:55 +00:00
|
|
|
|
2005-11-10 14:26:52 +00:00
|
|
|
/*
|
|
|
|
* This clock is a composite clock which does entire set changes then
|
|
|
|
* forces a rebalance. It keys on the MPU speed, but it really could
|
|
|
|
* be any key speed part of a set in the rate table.
|
|
|
|
*
|
|
|
|
* to really change a set, you need memory table sets which get changed
|
|
|
|
* in sram, pre-notifiers & post notifiers, changing the top set, without
|
|
|
|
* having low level display recalc's won't work... this is why dpm notifiers
|
|
|
|
* work, isr's off, walk a list of clocks already _off_ and not messing with
|
|
|
|
* the bus.
|
|
|
|
*
|
|
|
|
* This clock should have no parent. It embodies the entire upper level
|
|
|
|
* active set. A parent will mess up some of the init also.
|
|
|
|
*/
|
|
|
|
static struct clk virt_prcm_set = {
|
|
|
|
.name = "virt_prcm_set",
|
2008-11-04 16:35:03 +00:00
|
|
|
.ops = &clkops_null,
|
2005-11-10 14:26:52 +00:00
|
|
|
.parent = &mpu_ck, /* Indexed by mpu speed, no parent */
|
2008-03-18 13:47:55 +00:00
|
|
|
.recalc = &omap2_table_mpu_recalc, /* sets are keyed on mpu rate */
|
2005-11-10 14:26:52 +00:00
|
|
|
.set_rate = &omap2_select_table_rate,
|
|
|
|
.round_rate = &omap2_round_to_table_rate,
|
|
|
|
};
|
2008-03-18 13:47:55 +00:00
|
|
|
|
2009-12-08 23:21:29 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* clkdev integration
|
|
|
|
*/
|
|
|
|
|
OMAP2 clock: split OMAP2420, OMAP2430 clock data into their own files
In preparation for multi-OMAP2 kernels, split
mach-omap2/clock2xxx_data.c into mach-omap2/clock2420_data.c and
mach-omap2/clock2430_data.c. 2430 uses a different device space
physical memory layout than past or future OMAPs, and we use a
different virtual memory layout as well, which causes trouble for
architecture-level code/data that tries to support both. We tried
using offsets from the virtual base last year, but those patches never
made it upstream; so after some discussion with Tony about the best
all-around approach, we'll just grit our teeth and duplicate the
structures. The maintenance advantages of a single kernel config that
can compile and boot on OMAP2, 3, and 4 platforms are simply too
compelling.
This approach does have some nice benefits beyond multi-OMAP 2 kernel
support. The runtime size of OMAP2420-specific and OMAP2430-specific
kernels is smaller, since unused clocks for the other OMAP2 chip will
no longer be compiled in. (At some point we will mark the clock data
__initdata and allocate it during registration, which will eliminate
the runtime memory advantage.) It also makes the clock trees slightly
easier to read, since 2420-specific and 2430-specific clocks are no
longer mixed together.
This patch also splits 2430-specific clock code into its own file,
mach-omap2/clock2430.c, which is only compiled in for 2430 builds -
mostly for organizational clarity.
While here, fix a bug in the OMAP2430 clock tree: "emul_ck" was
incorrectly marked as being 2420-only, when actually it is present on
both OMAP2420 and OMAP2430.
Thanks to Tony for some good discussions about how to approach this
problem.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Richard Woodruff <r-woodruff2@ti.com>
2010-02-23 05:09:22 +00:00
|
|
|
static struct omap_clk omap2430_clks[] = {
|
2009-12-08 23:21:29 +00:00
|
|
|
/* external root sources */
|
OMAP2 clock: split OMAP2420, OMAP2430 clock data into their own files
In preparation for multi-OMAP2 kernels, split
mach-omap2/clock2xxx_data.c into mach-omap2/clock2420_data.c and
mach-omap2/clock2430_data.c. 2430 uses a different device space
physical memory layout than past or future OMAPs, and we use a
different virtual memory layout as well, which causes trouble for
architecture-level code/data that tries to support both. We tried
using offsets from the virtual base last year, but those patches never
made it upstream; so after some discussion with Tony about the best
all-around approach, we'll just grit our teeth and duplicate the
structures. The maintenance advantages of a single kernel config that
can compile and boot on OMAP2, 3, and 4 platforms are simply too
compelling.
This approach does have some nice benefits beyond multi-OMAP 2 kernel
support. The runtime size of OMAP2420-specific and OMAP2430-specific
kernels is smaller, since unused clocks for the other OMAP2 chip will
no longer be compiled in. (At some point we will mark the clock data
__initdata and allocate it during registration, which will eliminate
the runtime memory advantage.) It also makes the clock trees slightly
easier to read, since 2420-specific and 2430-specific clocks are no
longer mixed together.
This patch also splits 2430-specific clock code into its own file,
mach-omap2/clock2430.c, which is only compiled in for 2430 builds -
mostly for organizational clarity.
While here, fix a bug in the OMAP2430 clock tree: "emul_ck" was
incorrectly marked as being 2420-only, when actually it is present on
both OMAP2420 and OMAP2430.
Thanks to Tony for some good discussions about how to approach this
problem.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Richard Woodruff <r-woodruff2@ti.com>
2010-02-23 05:09:22 +00:00
|
|
|
CLK(NULL, "func_32k_ck", &func_32k_ck, CK_243X),
|
|
|
|
CLK(NULL, "secure_32k_ck", &secure_32k_ck, CK_243X),
|
|
|
|
CLK(NULL, "osc_ck", &osc_ck, CK_243X),
|
|
|
|
CLK(NULL, "sys_ck", &sys_ck, CK_243X),
|
|
|
|
CLK(NULL, "alt_ck", &alt_ck, CK_243X),
|
2010-10-08 17:40:18 +00:00
|
|
|
CLK("omap-mcbsp.1", "pad_fck", &mcbsp_clks, CK_243X),
|
|
|
|
CLK("omap-mcbsp.2", "pad_fck", &mcbsp_clks, CK_243X),
|
|
|
|
CLK("omap-mcbsp.3", "pad_fck", &mcbsp_clks, CK_243X),
|
|
|
|
CLK("omap-mcbsp.4", "pad_fck", &mcbsp_clks, CK_243X),
|
|
|
|
CLK("omap-mcbsp.5", "pad_fck", &mcbsp_clks, CK_243X),
|
|
|
|
CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_243X),
|
2009-12-08 23:21:29 +00:00
|
|
|
/* internal analog sources */
|
OMAP2 clock: split OMAP2420, OMAP2430 clock data into their own files
In preparation for multi-OMAP2 kernels, split
mach-omap2/clock2xxx_data.c into mach-omap2/clock2420_data.c and
mach-omap2/clock2430_data.c. 2430 uses a different device space
physical memory layout than past or future OMAPs, and we use a
different virtual memory layout as well, which causes trouble for
architecture-level code/data that tries to support both. We tried
using offsets from the virtual base last year, but those patches never
made it upstream; so after some discussion with Tony about the best
all-around approach, we'll just grit our teeth and duplicate the
structures. The maintenance advantages of a single kernel config that
can compile and boot on OMAP2, 3, and 4 platforms are simply too
compelling.
This approach does have some nice benefits beyond multi-OMAP 2 kernel
support. The runtime size of OMAP2420-specific and OMAP2430-specific
kernels is smaller, since unused clocks for the other OMAP2 chip will
no longer be compiled in. (At some point we will mark the clock data
__initdata and allocate it during registration, which will eliminate
the runtime memory advantage.) It also makes the clock trees slightly
easier to read, since 2420-specific and 2430-specific clocks are no
longer mixed together.
This patch also splits 2430-specific clock code into its own file,
mach-omap2/clock2430.c, which is only compiled in for 2430 builds -
mostly for organizational clarity.
While here, fix a bug in the OMAP2430 clock tree: "emul_ck" was
incorrectly marked as being 2420-only, when actually it is present on
both OMAP2420 and OMAP2430.
Thanks to Tony for some good discussions about how to approach this
problem.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Richard Woodruff <r-woodruff2@ti.com>
2010-02-23 05:09:22 +00:00
|
|
|
CLK(NULL, "dpll_ck", &dpll_ck, CK_243X),
|
|
|
|
CLK(NULL, "apll96_ck", &apll96_ck, CK_243X),
|
|
|
|
CLK(NULL, "apll54_ck", &apll54_ck, CK_243X),
|
2009-12-08 23:21:29 +00:00
|
|
|
/* internal prcm root sources */
|
OMAP2 clock: split OMAP2420, OMAP2430 clock data into their own files
In preparation for multi-OMAP2 kernels, split
mach-omap2/clock2xxx_data.c into mach-omap2/clock2420_data.c and
mach-omap2/clock2430_data.c. 2430 uses a different device space
physical memory layout than past or future OMAPs, and we use a
different virtual memory layout as well, which causes trouble for
architecture-level code/data that tries to support both. We tried
using offsets from the virtual base last year, but those patches never
made it upstream; so after some discussion with Tony about the best
all-around approach, we'll just grit our teeth and duplicate the
structures. The maintenance advantages of a single kernel config that
can compile and boot on OMAP2, 3, and 4 platforms are simply too
compelling.
This approach does have some nice benefits beyond multi-OMAP 2 kernel
support. The runtime size of OMAP2420-specific and OMAP2430-specific
kernels is smaller, since unused clocks for the other OMAP2 chip will
no longer be compiled in. (At some point we will mark the clock data
__initdata and allocate it during registration, which will eliminate
the runtime memory advantage.) It also makes the clock trees slightly
easier to read, since 2420-specific and 2430-specific clocks are no
longer mixed together.
This patch also splits 2430-specific clock code into its own file,
mach-omap2/clock2430.c, which is only compiled in for 2430 builds -
mostly for organizational clarity.
While here, fix a bug in the OMAP2430 clock tree: "emul_ck" was
incorrectly marked as being 2420-only, when actually it is present on
both OMAP2420 and OMAP2430.
Thanks to Tony for some good discussions about how to approach this
problem.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Richard Woodruff <r-woodruff2@ti.com>
2010-02-23 05:09:22 +00:00
|
|
|
CLK(NULL, "func_54m_ck", &func_54m_ck, CK_243X),
|
|
|
|
CLK(NULL, "core_ck", &core_ck, CK_243X),
|
2010-10-08 17:40:18 +00:00
|
|
|
CLK("omap-mcbsp.1", "prcm_fck", &func_96m_ck, CK_243X),
|
|
|
|
CLK("omap-mcbsp.2", "prcm_fck", &func_96m_ck, CK_243X),
|
|
|
|
CLK("omap-mcbsp.3", "prcm_fck", &func_96m_ck, CK_243X),
|
|
|
|
CLK("omap-mcbsp.4", "prcm_fck", &func_96m_ck, CK_243X),
|
|
|
|
CLK("omap-mcbsp.5", "prcm_fck", &func_96m_ck, CK_243X),
|
OMAP2 clock: split OMAP2420, OMAP2430 clock data into their own files
In preparation for multi-OMAP2 kernels, split
mach-omap2/clock2xxx_data.c into mach-omap2/clock2420_data.c and
mach-omap2/clock2430_data.c. 2430 uses a different device space
physical memory layout than past or future OMAPs, and we use a
different virtual memory layout as well, which causes trouble for
architecture-level code/data that tries to support both. We tried
using offsets from the virtual base last year, but those patches never
made it upstream; so after some discussion with Tony about the best
all-around approach, we'll just grit our teeth and duplicate the
structures. The maintenance advantages of a single kernel config that
can compile and boot on OMAP2, 3, and 4 platforms are simply too
compelling.
This approach does have some nice benefits beyond multi-OMAP 2 kernel
support. The runtime size of OMAP2420-specific and OMAP2430-specific
kernels is smaller, since unused clocks for the other OMAP2 chip will
no longer be compiled in. (At some point we will mark the clock data
__initdata and allocate it during registration, which will eliminate
the runtime memory advantage.) It also makes the clock trees slightly
easier to read, since 2420-specific and 2430-specific clocks are no
longer mixed together.
This patch also splits 2430-specific clock code into its own file,
mach-omap2/clock2430.c, which is only compiled in for 2430 builds -
mostly for organizational clarity.
While here, fix a bug in the OMAP2430 clock tree: "emul_ck" was
incorrectly marked as being 2420-only, when actually it is present on
both OMAP2420 and OMAP2430.
Thanks to Tony for some good discussions about how to approach this
problem.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Richard Woodruff <r-woodruff2@ti.com>
2010-02-23 05:09:22 +00:00
|
|
|
CLK(NULL, "func_96m_ck", &func_96m_ck, CK_243X),
|
|
|
|
CLK(NULL, "func_48m_ck", &func_48m_ck, CK_243X),
|
|
|
|
CLK(NULL, "func_12m_ck", &func_12m_ck, CK_243X),
|
|
|
|
CLK(NULL, "ck_wdt1_osc", &wdt1_osc_ck, CK_243X),
|
|
|
|
CLK(NULL, "sys_clkout_src", &sys_clkout_src, CK_243X),
|
|
|
|
CLK(NULL, "sys_clkout", &sys_clkout, CK_243X),
|
|
|
|
CLK(NULL, "emul_ck", &emul_ck, CK_243X),
|
2009-12-08 23:21:29 +00:00
|
|
|
/* mpu domain clocks */
|
OMAP2 clock: split OMAP2420, OMAP2430 clock data into their own files
In preparation for multi-OMAP2 kernels, split
mach-omap2/clock2xxx_data.c into mach-omap2/clock2420_data.c and
mach-omap2/clock2430_data.c. 2430 uses a different device space
physical memory layout than past or future OMAPs, and we use a
different virtual memory layout as well, which causes trouble for
architecture-level code/data that tries to support both. We tried
using offsets from the virtual base last year, but those patches never
made it upstream; so after some discussion with Tony about the best
all-around approach, we'll just grit our teeth and duplicate the
structures. The maintenance advantages of a single kernel config that
can compile and boot on OMAP2, 3, and 4 platforms are simply too
compelling.
This approach does have some nice benefits beyond multi-OMAP 2 kernel
support. The runtime size of OMAP2420-specific and OMAP2430-specific
kernels is smaller, since unused clocks for the other OMAP2 chip will
no longer be compiled in. (At some point we will mark the clock data
__initdata and allocate it during registration, which will eliminate
the runtime memory advantage.) It also makes the clock trees slightly
easier to read, since 2420-specific and 2430-specific clocks are no
longer mixed together.
This patch also splits 2430-specific clock code into its own file,
mach-omap2/clock2430.c, which is only compiled in for 2430 builds -
mostly for organizational clarity.
While here, fix a bug in the OMAP2430 clock tree: "emul_ck" was
incorrectly marked as being 2420-only, when actually it is present on
both OMAP2420 and OMAP2430.
Thanks to Tony for some good discussions about how to approach this
problem.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Richard Woodruff <r-woodruff2@ti.com>
2010-02-23 05:09:22 +00:00
|
|
|
CLK(NULL, "mpu_ck", &mpu_ck, CK_243X),
|
2009-12-08 23:21:29 +00:00
|
|
|
/* dsp domain clocks */
|
OMAP2 clock: split OMAP2420, OMAP2430 clock data into their own files
In preparation for multi-OMAP2 kernels, split
mach-omap2/clock2xxx_data.c into mach-omap2/clock2420_data.c and
mach-omap2/clock2430_data.c. 2430 uses a different device space
physical memory layout than past or future OMAPs, and we use a
different virtual memory layout as well, which causes trouble for
architecture-level code/data that tries to support both. We tried
using offsets from the virtual base last year, but those patches never
made it upstream; so after some discussion with Tony about the best
all-around approach, we'll just grit our teeth and duplicate the
structures. The maintenance advantages of a single kernel config that
can compile and boot on OMAP2, 3, and 4 platforms are simply too
compelling.
This approach does have some nice benefits beyond multi-OMAP 2 kernel
support. The runtime size of OMAP2420-specific and OMAP2430-specific
kernels is smaller, since unused clocks for the other OMAP2 chip will
no longer be compiled in. (At some point we will mark the clock data
__initdata and allocate it during registration, which will eliminate
the runtime memory advantage.) It also makes the clock trees slightly
easier to read, since 2420-specific and 2430-specific clocks are no
longer mixed together.
This patch also splits 2430-specific clock code into its own file,
mach-omap2/clock2430.c, which is only compiled in for 2430 builds -
mostly for organizational clarity.
While here, fix a bug in the OMAP2430 clock tree: "emul_ck" was
incorrectly marked as being 2420-only, when actually it is present on
both OMAP2420 and OMAP2430.
Thanks to Tony for some good discussions about how to approach this
problem.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Richard Woodruff <r-woodruff2@ti.com>
2010-02-23 05:09:22 +00:00
|
|
|
CLK(NULL, "dsp_fck", &dsp_fck, CK_243X),
|
2009-12-08 23:21:29 +00:00
|
|
|
CLK(NULL, "iva2_1_ick", &iva2_1_ick, CK_243X),
|
|
|
|
/* GFX domain clocks */
|
OMAP2 clock: split OMAP2420, OMAP2430 clock data into their own files
In preparation for multi-OMAP2 kernels, split
mach-omap2/clock2xxx_data.c into mach-omap2/clock2420_data.c and
mach-omap2/clock2430_data.c. 2430 uses a different device space
physical memory layout than past or future OMAPs, and we use a
different virtual memory layout as well, which causes trouble for
architecture-level code/data that tries to support both. We tried
using offsets from the virtual base last year, but those patches never
made it upstream; so after some discussion with Tony about the best
all-around approach, we'll just grit our teeth and duplicate the
structures. The maintenance advantages of a single kernel config that
can compile and boot on OMAP2, 3, and 4 platforms are simply too
compelling.
This approach does have some nice benefits beyond multi-OMAP 2 kernel
support. The runtime size of OMAP2420-specific and OMAP2430-specific
kernels is smaller, since unused clocks for the other OMAP2 chip will
no longer be compiled in. (At some point we will mark the clock data
__initdata and allocate it during registration, which will eliminate
the runtime memory advantage.) It also makes the clock trees slightly
easier to read, since 2420-specific and 2430-specific clocks are no
longer mixed together.
This patch also splits 2430-specific clock code into its own file,
mach-omap2/clock2430.c, which is only compiled in for 2430 builds -
mostly for organizational clarity.
While here, fix a bug in the OMAP2430 clock tree: "emul_ck" was
incorrectly marked as being 2420-only, when actually it is present on
both OMAP2420 and OMAP2430.
Thanks to Tony for some good discussions about how to approach this
problem.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Richard Woodruff <r-woodruff2@ti.com>
2010-02-23 05:09:22 +00:00
|
|
|
CLK(NULL, "gfx_3d_fck", &gfx_3d_fck, CK_243X),
|
|
|
|
CLK(NULL, "gfx_2d_fck", &gfx_2d_fck, CK_243X),
|
|
|
|
CLK(NULL, "gfx_ick", &gfx_ick, CK_243X),
|
2009-12-08 23:21:29 +00:00
|
|
|
/* Modem domain clocks */
|
|
|
|
CLK(NULL, "mdm_ick", &mdm_ick, CK_243X),
|
|
|
|
CLK(NULL, "mdm_osc_ck", &mdm_osc_ck, CK_243X),
|
|
|
|
/* DSS domain clocks */
|
2011-01-24 06:21:58 +00:00
|
|
|
CLK("omapdss_dss", "ick", &dss_ick, CK_243X),
|
2011-07-10 11:54:12 +00:00
|
|
|
CLK(NULL, "dss1_fck", &dss1_fck, CK_243X),
|
|
|
|
CLK(NULL, "dss2_fck", &dss2_fck, CK_243X),
|
|
|
|
CLK(NULL, "dss_54m_fck", &dss_54m_fck, CK_243X),
|
2009-12-08 23:21:29 +00:00
|
|
|
/* L3 domain clocks */
|
OMAP2 clock: split OMAP2420, OMAP2430 clock data into their own files
In preparation for multi-OMAP2 kernels, split
mach-omap2/clock2xxx_data.c into mach-omap2/clock2420_data.c and
mach-omap2/clock2430_data.c. 2430 uses a different device space
physical memory layout than past or future OMAPs, and we use a
different virtual memory layout as well, which causes trouble for
architecture-level code/data that tries to support both. We tried
using offsets from the virtual base last year, but those patches never
made it upstream; so after some discussion with Tony about the best
all-around approach, we'll just grit our teeth and duplicate the
structures. The maintenance advantages of a single kernel config that
can compile and boot on OMAP2, 3, and 4 platforms are simply too
compelling.
This approach does have some nice benefits beyond multi-OMAP 2 kernel
support. The runtime size of OMAP2420-specific and OMAP2430-specific
kernels is smaller, since unused clocks for the other OMAP2 chip will
no longer be compiled in. (At some point we will mark the clock data
__initdata and allocate it during registration, which will eliminate
the runtime memory advantage.) It also makes the clock trees slightly
easier to read, since 2420-specific and 2430-specific clocks are no
longer mixed together.
This patch also splits 2430-specific clock code into its own file,
mach-omap2/clock2430.c, which is only compiled in for 2430 builds -
mostly for organizational clarity.
While here, fix a bug in the OMAP2430 clock tree: "emul_ck" was
incorrectly marked as being 2420-only, when actually it is present on
both OMAP2420 and OMAP2430.
Thanks to Tony for some good discussions about how to approach this
problem.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Richard Woodruff <r-woodruff2@ti.com>
2010-02-23 05:09:22 +00:00
|
|
|
CLK(NULL, "core_l3_ck", &core_l3_ck, CK_243X),
|
|
|
|
CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_243X),
|
|
|
|
CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_243X),
|
2009-12-08 23:21:29 +00:00
|
|
|
/* L4 domain clocks */
|
OMAP2 clock: split OMAP2420, OMAP2430 clock data into their own files
In preparation for multi-OMAP2 kernels, split
mach-omap2/clock2xxx_data.c into mach-omap2/clock2420_data.c and
mach-omap2/clock2430_data.c. 2430 uses a different device space
physical memory layout than past or future OMAPs, and we use a
different virtual memory layout as well, which causes trouble for
architecture-level code/data that tries to support both. We tried
using offsets from the virtual base last year, but those patches never
made it upstream; so after some discussion with Tony about the best
all-around approach, we'll just grit our teeth and duplicate the
structures. The maintenance advantages of a single kernel config that
can compile and boot on OMAP2, 3, and 4 platforms are simply too
compelling.
This approach does have some nice benefits beyond multi-OMAP 2 kernel
support. The runtime size of OMAP2420-specific and OMAP2430-specific
kernels is smaller, since unused clocks for the other OMAP2 chip will
no longer be compiled in. (At some point we will mark the clock data
__initdata and allocate it during registration, which will eliminate
the runtime memory advantage.) It also makes the clock trees slightly
easier to read, since 2420-specific and 2430-specific clocks are no
longer mixed together.
This patch also splits 2430-specific clock code into its own file,
mach-omap2/clock2430.c, which is only compiled in for 2430 builds -
mostly for organizational clarity.
While here, fix a bug in the OMAP2430 clock tree: "emul_ck" was
incorrectly marked as being 2420-only, when actually it is present on
both OMAP2420 and OMAP2430.
Thanks to Tony for some good discussions about how to approach this
problem.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Richard Woodruff <r-woodruff2@ti.com>
2010-02-23 05:09:22 +00:00
|
|
|
CLK(NULL, "l4_ck", &l4_ck, CK_243X),
|
|
|
|
CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_243X),
|
OMAP2xxx: clock: fix interface clocks and clockdomains for modules in the WKUP domain
The parent of the interface clocks for GPTIMER1, MPU_WDT,
SYNCTIMER_32K, SCM, WDT1, and the ICR (2430 only) were all listed as
being l4_ck. This isn't accurate; these modules exist inside the WKUP
domain, and the interface clock to these modules runs at the SYS_CLK
rate rather than the CORE L4 rate.
So, create a new clock "wu_l4_ick", similar to the OMAP3
"wkup_l4_ick", that serves as the parent for these clocks.
Also, these clocks were listed as existing inside core_l4_clkdm;
wkup_clkdm is probably more accurate.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
2011-02-16 22:38:38 +00:00
|
|
|
CLK(NULL, "wu_l4_ick", &wu_l4_ick, CK_243X),
|
2009-12-08 23:21:29 +00:00
|
|
|
/* virtual meta-group clock */
|
OMAP2 clock: split OMAP2420, OMAP2430 clock data into their own files
In preparation for multi-OMAP2 kernels, split
mach-omap2/clock2xxx_data.c into mach-omap2/clock2420_data.c and
mach-omap2/clock2430_data.c. 2430 uses a different device space
physical memory layout than past or future OMAPs, and we use a
different virtual memory layout as well, which causes trouble for
architecture-level code/data that tries to support both. We tried
using offsets from the virtual base last year, but those patches never
made it upstream; so after some discussion with Tony about the best
all-around approach, we'll just grit our teeth and duplicate the
structures. The maintenance advantages of a single kernel config that
can compile and boot on OMAP2, 3, and 4 platforms are simply too
compelling.
This approach does have some nice benefits beyond multi-OMAP 2 kernel
support. The runtime size of OMAP2420-specific and OMAP2430-specific
kernels is smaller, since unused clocks for the other OMAP2 chip will
no longer be compiled in. (At some point we will mark the clock data
__initdata and allocate it during registration, which will eliminate
the runtime memory advantage.) It also makes the clock trees slightly
easier to read, since 2420-specific and 2430-specific clocks are no
longer mixed together.
This patch also splits 2430-specific clock code into its own file,
mach-omap2/clock2430.c, which is only compiled in for 2430 builds -
mostly for organizational clarity.
While here, fix a bug in the OMAP2430 clock tree: "emul_ck" was
incorrectly marked as being 2420-only, when actually it is present on
both OMAP2420 and OMAP2430.
Thanks to Tony for some good discussions about how to approach this
problem.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Richard Woodruff <r-woodruff2@ti.com>
2010-02-23 05:09:22 +00:00
|
|
|
CLK(NULL, "virt_prcm_set", &virt_prcm_set, CK_243X),
|
2009-12-08 23:21:29 +00:00
|
|
|
/* general l4 interface ck, multi-parent functional clk */
|
OMAP2 clock: split OMAP2420, OMAP2430 clock data into their own files
In preparation for multi-OMAP2 kernels, split
mach-omap2/clock2xxx_data.c into mach-omap2/clock2420_data.c and
mach-omap2/clock2430_data.c. 2430 uses a different device space
physical memory layout than past or future OMAPs, and we use a
different virtual memory layout as well, which causes trouble for
architecture-level code/data that tries to support both. We tried
using offsets from the virtual base last year, but those patches never
made it upstream; so after some discussion with Tony about the best
all-around approach, we'll just grit our teeth and duplicate the
structures. The maintenance advantages of a single kernel config that
can compile and boot on OMAP2, 3, and 4 platforms are simply too
compelling.
This approach does have some nice benefits beyond multi-OMAP 2 kernel
support. The runtime size of OMAP2420-specific and OMAP2430-specific
kernels is smaller, since unused clocks for the other OMAP2 chip will
no longer be compiled in. (At some point we will mark the clock data
__initdata and allocate it during registration, which will eliminate
the runtime memory advantage.) It also makes the clock trees slightly
easier to read, since 2420-specific and 2430-specific clocks are no
longer mixed together.
This patch also splits 2430-specific clock code into its own file,
mach-omap2/clock2430.c, which is only compiled in for 2430 builds -
mostly for organizational clarity.
While here, fix a bug in the OMAP2430 clock tree: "emul_ck" was
incorrectly marked as being 2420-only, when actually it is present on
both OMAP2420 and OMAP2430.
Thanks to Tony for some good discussions about how to approach this
problem.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Richard Woodruff <r-woodruff2@ti.com>
2010-02-23 05:09:22 +00:00
|
|
|
CLK(NULL, "gpt1_ick", &gpt1_ick, CK_243X),
|
|
|
|
CLK(NULL, "gpt1_fck", &gpt1_fck, CK_243X),
|
|
|
|
CLK(NULL, "gpt2_ick", &gpt2_ick, CK_243X),
|
|
|
|
CLK(NULL, "gpt2_fck", &gpt2_fck, CK_243X),
|
|
|
|
CLK(NULL, "gpt3_ick", &gpt3_ick, CK_243X),
|
|
|
|
CLK(NULL, "gpt3_fck", &gpt3_fck, CK_243X),
|
|
|
|
CLK(NULL, "gpt4_ick", &gpt4_ick, CK_243X),
|
|
|
|
CLK(NULL, "gpt4_fck", &gpt4_fck, CK_243X),
|
|
|
|
CLK(NULL, "gpt5_ick", &gpt5_ick, CK_243X),
|
|
|
|
CLK(NULL, "gpt5_fck", &gpt5_fck, CK_243X),
|
|
|
|
CLK(NULL, "gpt6_ick", &gpt6_ick, CK_243X),
|
|
|
|
CLK(NULL, "gpt6_fck", &gpt6_fck, CK_243X),
|
|
|
|
CLK(NULL, "gpt7_ick", &gpt7_ick, CK_243X),
|
|
|
|
CLK(NULL, "gpt7_fck", &gpt7_fck, CK_243X),
|
|
|
|
CLK(NULL, "gpt8_ick", &gpt8_ick, CK_243X),
|
|
|
|
CLK(NULL, "gpt8_fck", &gpt8_fck, CK_243X),
|
|
|
|
CLK(NULL, "gpt9_ick", &gpt9_ick, CK_243X),
|
|
|
|
CLK(NULL, "gpt9_fck", &gpt9_fck, CK_243X),
|
|
|
|
CLK(NULL, "gpt10_ick", &gpt10_ick, CK_243X),
|
|
|
|
CLK(NULL, "gpt10_fck", &gpt10_fck, CK_243X),
|
|
|
|
CLK(NULL, "gpt11_ick", &gpt11_ick, CK_243X),
|
|
|
|
CLK(NULL, "gpt11_fck", &gpt11_fck, CK_243X),
|
|
|
|
CLK(NULL, "gpt12_ick", &gpt12_ick, CK_243X),
|
|
|
|
CLK(NULL, "gpt12_fck", &gpt12_fck, CK_243X),
|
|
|
|
CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_243X),
|
2011-07-10 11:54:12 +00:00
|
|
|
CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_243X),
|
OMAP2 clock: split OMAP2420, OMAP2430 clock data into their own files
In preparation for multi-OMAP2 kernels, split
mach-omap2/clock2xxx_data.c into mach-omap2/clock2420_data.c and
mach-omap2/clock2430_data.c. 2430 uses a different device space
physical memory layout than past or future OMAPs, and we use a
different virtual memory layout as well, which causes trouble for
architecture-level code/data that tries to support both. We tried
using offsets from the virtual base last year, but those patches never
made it upstream; so after some discussion with Tony about the best
all-around approach, we'll just grit our teeth and duplicate the
structures. The maintenance advantages of a single kernel config that
can compile and boot on OMAP2, 3, and 4 platforms are simply too
compelling.
This approach does have some nice benefits beyond multi-OMAP 2 kernel
support. The runtime size of OMAP2420-specific and OMAP2430-specific
kernels is smaller, since unused clocks for the other OMAP2 chip will
no longer be compiled in. (At some point we will mark the clock data
__initdata and allocate it during registration, which will eliminate
the runtime memory advantage.) It also makes the clock trees slightly
easier to read, since 2420-specific and 2430-specific clocks are no
longer mixed together.
This patch also splits 2430-specific clock code into its own file,
mach-omap2/clock2430.c, which is only compiled in for 2430 builds -
mostly for organizational clarity.
While here, fix a bug in the OMAP2430 clock tree: "emul_ck" was
incorrectly marked as being 2420-only, when actually it is present on
both OMAP2420 and OMAP2430.
Thanks to Tony for some good discussions about how to approach this
problem.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Richard Woodruff <r-woodruff2@ti.com>
2010-02-23 05:09:22 +00:00
|
|
|
CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_243X),
|
2011-07-10 11:54:12 +00:00
|
|
|
CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_243X),
|
2009-12-08 23:21:29 +00:00
|
|
|
CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_243X),
|
2011-07-10 11:54:12 +00:00
|
|
|
CLK(NULL, "mcbsp3_fck", &mcbsp3_fck, CK_243X),
|
2009-12-08 23:21:29 +00:00
|
|
|
CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_243X),
|
2011-07-10 11:54:12 +00:00
|
|
|
CLK(NULL, "mcbsp4_fck", &mcbsp4_fck, CK_243X),
|
2009-12-08 23:21:29 +00:00
|
|
|
CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_243X),
|
2011-07-10 11:54:12 +00:00
|
|
|
CLK(NULL, "mcbsp5_fck", &mcbsp5_fck, CK_243X),
|
OMAP2 clock: split OMAP2420, OMAP2430 clock data into their own files
In preparation for multi-OMAP2 kernels, split
mach-omap2/clock2xxx_data.c into mach-omap2/clock2420_data.c and
mach-omap2/clock2430_data.c. 2430 uses a different device space
physical memory layout than past or future OMAPs, and we use a
different virtual memory layout as well, which causes trouble for
architecture-level code/data that tries to support both. We tried
using offsets from the virtual base last year, but those patches never
made it upstream; so after some discussion with Tony about the best
all-around approach, we'll just grit our teeth and duplicate the
structures. The maintenance advantages of a single kernel config that
can compile and boot on OMAP2, 3, and 4 platforms are simply too
compelling.
This approach does have some nice benefits beyond multi-OMAP 2 kernel
support. The runtime size of OMAP2420-specific and OMAP2430-specific
kernels is smaller, since unused clocks for the other OMAP2 chip will
no longer be compiled in. (At some point we will mark the clock data
__initdata and allocate it during registration, which will eliminate
the runtime memory advantage.) It also makes the clock trees slightly
easier to read, since 2420-specific and 2430-specific clocks are no
longer mixed together.
This patch also splits 2430-specific clock code into its own file,
mach-omap2/clock2430.c, which is only compiled in for 2430 builds -
mostly for organizational clarity.
While here, fix a bug in the OMAP2430 clock tree: "emul_ck" was
incorrectly marked as being 2420-only, when actually it is present on
both OMAP2420 and OMAP2430.
Thanks to Tony for some good discussions about how to approach this
problem.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Richard Woodruff <r-woodruff2@ti.com>
2010-02-23 05:09:22 +00:00
|
|
|
CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_243X),
|
2011-07-10 11:54:12 +00:00
|
|
|
CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_243X),
|
OMAP2 clock: split OMAP2420, OMAP2430 clock data into their own files
In preparation for multi-OMAP2 kernels, split
mach-omap2/clock2xxx_data.c into mach-omap2/clock2420_data.c and
mach-omap2/clock2430_data.c. 2430 uses a different device space
physical memory layout than past or future OMAPs, and we use a
different virtual memory layout as well, which causes trouble for
architecture-level code/data that tries to support both. We tried
using offsets from the virtual base last year, but those patches never
made it upstream; so after some discussion with Tony about the best
all-around approach, we'll just grit our teeth and duplicate the
structures. The maintenance advantages of a single kernel config that
can compile and boot on OMAP2, 3, and 4 platforms are simply too
compelling.
This approach does have some nice benefits beyond multi-OMAP 2 kernel
support. The runtime size of OMAP2420-specific and OMAP2430-specific
kernels is smaller, since unused clocks for the other OMAP2 chip will
no longer be compiled in. (At some point we will mark the clock data
__initdata and allocate it during registration, which will eliminate
the runtime memory advantage.) It also makes the clock trees slightly
easier to read, since 2420-specific and 2430-specific clocks are no
longer mixed together.
This patch also splits 2430-specific clock code into its own file,
mach-omap2/clock2430.c, which is only compiled in for 2430 builds -
mostly for organizational clarity.
While here, fix a bug in the OMAP2430 clock tree: "emul_ck" was
incorrectly marked as being 2420-only, when actually it is present on
both OMAP2420 and OMAP2430.
Thanks to Tony for some good discussions about how to approach this
problem.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Richard Woodruff <r-woodruff2@ti.com>
2010-02-23 05:09:22 +00:00
|
|
|
CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_243X),
|
2011-07-10 11:54:12 +00:00
|
|
|
CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_243X),
|
2009-12-08 23:21:29 +00:00
|
|
|
CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_243X),
|
2011-07-10 11:54:12 +00:00
|
|
|
CLK(NULL, "mcspi3_fck", &mcspi3_fck, CK_243X),
|
OMAP2 clock: split OMAP2420, OMAP2430 clock data into their own files
In preparation for multi-OMAP2 kernels, split
mach-omap2/clock2xxx_data.c into mach-omap2/clock2420_data.c and
mach-omap2/clock2430_data.c. 2430 uses a different device space
physical memory layout than past or future OMAPs, and we use a
different virtual memory layout as well, which causes trouble for
architecture-level code/data that tries to support both. We tried
using offsets from the virtual base last year, but those patches never
made it upstream; so after some discussion with Tony about the best
all-around approach, we'll just grit our teeth and duplicate the
structures. The maintenance advantages of a single kernel config that
can compile and boot on OMAP2, 3, and 4 platforms are simply too
compelling.
This approach does have some nice benefits beyond multi-OMAP 2 kernel
support. The runtime size of OMAP2420-specific and OMAP2430-specific
kernels is smaller, since unused clocks for the other OMAP2 chip will
no longer be compiled in. (At some point we will mark the clock data
__initdata and allocate it during registration, which will eliminate
the runtime memory advantage.) It also makes the clock trees slightly
easier to read, since 2420-specific and 2430-specific clocks are no
longer mixed together.
This patch also splits 2430-specific clock code into its own file,
mach-omap2/clock2430.c, which is only compiled in for 2430 builds -
mostly for organizational clarity.
While here, fix a bug in the OMAP2430 clock tree: "emul_ck" was
incorrectly marked as being 2420-only, when actually it is present on
both OMAP2420 and OMAP2430.
Thanks to Tony for some good discussions about how to approach this
problem.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Richard Woodruff <r-woodruff2@ti.com>
2010-02-23 05:09:22 +00:00
|
|
|
CLK(NULL, "uart1_ick", &uart1_ick, CK_243X),
|
|
|
|
CLK(NULL, "uart1_fck", &uart1_fck, CK_243X),
|
|
|
|
CLK(NULL, "uart2_ick", &uart2_ick, CK_243X),
|
|
|
|
CLK(NULL, "uart2_fck", &uart2_fck, CK_243X),
|
|
|
|
CLK(NULL, "uart3_ick", &uart3_ick, CK_243X),
|
|
|
|
CLK(NULL, "uart3_fck", &uart3_fck, CK_243X),
|
|
|
|
CLK(NULL, "gpios_ick", &gpios_ick, CK_243X),
|
|
|
|
CLK(NULL, "gpios_fck", &gpios_fck, CK_243X),
|
|
|
|
CLK("omap_wdt", "ick", &mpu_wdt_ick, CK_243X),
|
2011-07-10 11:54:12 +00:00
|
|
|
CLK(NULL, "mpu_wdt_fck", &mpu_wdt_fck, CK_243X),
|
OMAP2 clock: split OMAP2420, OMAP2430 clock data into their own files
In preparation for multi-OMAP2 kernels, split
mach-omap2/clock2xxx_data.c into mach-omap2/clock2420_data.c and
mach-omap2/clock2430_data.c. 2430 uses a different device space
physical memory layout than past or future OMAPs, and we use a
different virtual memory layout as well, which causes trouble for
architecture-level code/data that tries to support both. We tried
using offsets from the virtual base last year, but those patches never
made it upstream; so after some discussion with Tony about the best
all-around approach, we'll just grit our teeth and duplicate the
structures. The maintenance advantages of a single kernel config that
can compile and boot on OMAP2, 3, and 4 platforms are simply too
compelling.
This approach does have some nice benefits beyond multi-OMAP 2 kernel
support. The runtime size of OMAP2420-specific and OMAP2430-specific
kernels is smaller, since unused clocks for the other OMAP2 chip will
no longer be compiled in. (At some point we will mark the clock data
__initdata and allocate it during registration, which will eliminate
the runtime memory advantage.) It also makes the clock trees slightly
easier to read, since 2420-specific and 2430-specific clocks are no
longer mixed together.
This patch also splits 2430-specific clock code into its own file,
mach-omap2/clock2430.c, which is only compiled in for 2430 builds -
mostly for organizational clarity.
While here, fix a bug in the OMAP2430 clock tree: "emul_ck" was
incorrectly marked as being 2420-only, when actually it is present on
both OMAP2420 and OMAP2430.
Thanks to Tony for some good discussions about how to approach this
problem.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Richard Woodruff <r-woodruff2@ti.com>
2010-02-23 05:09:22 +00:00
|
|
|
CLK(NULL, "sync_32k_ick", &sync_32k_ick, CK_243X),
|
|
|
|
CLK(NULL, "wdt1_ick", &wdt1_ick, CK_243X),
|
|
|
|
CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_243X),
|
2009-12-08 23:21:29 +00:00
|
|
|
CLK(NULL, "icr_ick", &icr_ick, CK_243X),
|
OMAP2 clock: split OMAP2420, OMAP2430 clock data into their own files
In preparation for multi-OMAP2 kernels, split
mach-omap2/clock2xxx_data.c into mach-omap2/clock2420_data.c and
mach-omap2/clock2430_data.c. 2430 uses a different device space
physical memory layout than past or future OMAPs, and we use a
different virtual memory layout as well, which causes trouble for
architecture-level code/data that tries to support both. We tried
using offsets from the virtual base last year, but those patches never
made it upstream; so after some discussion with Tony about the best
all-around approach, we'll just grit our teeth and duplicate the
structures. The maintenance advantages of a single kernel config that
can compile and boot on OMAP2, 3, and 4 platforms are simply too
compelling.
This approach does have some nice benefits beyond multi-OMAP 2 kernel
support. The runtime size of OMAP2420-specific and OMAP2430-specific
kernels is smaller, since unused clocks for the other OMAP2 chip will
no longer be compiled in. (At some point we will mark the clock data
__initdata and allocate it during registration, which will eliminate
the runtime memory advantage.) It also makes the clock trees slightly
easier to read, since 2420-specific and 2430-specific clocks are no
longer mixed together.
This patch also splits 2430-specific clock code into its own file,
mach-omap2/clock2430.c, which is only compiled in for 2430 builds -
mostly for organizational clarity.
While here, fix a bug in the OMAP2430 clock tree: "emul_ck" was
incorrectly marked as being 2420-only, when actually it is present on
both OMAP2420 and OMAP2430.
Thanks to Tony for some good discussions about how to approach this
problem.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Richard Woodruff <r-woodruff2@ti.com>
2010-02-23 05:09:22 +00:00
|
|
|
CLK("omap24xxcam", "fck", &cam_fck, CK_243X),
|
|
|
|
CLK("omap24xxcam", "ick", &cam_ick, CK_243X),
|
|
|
|
CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_243X),
|
|
|
|
CLK(NULL, "wdt4_ick", &wdt4_ick, CK_243X),
|
|
|
|
CLK(NULL, "wdt4_fck", &wdt4_fck, CK_243X),
|
|
|
|
CLK(NULL, "mspro_ick", &mspro_ick, CK_243X),
|
|
|
|
CLK(NULL, "mspro_fck", &mspro_fck, CK_243X),
|
|
|
|
CLK(NULL, "fac_ick", &fac_ick, CK_243X),
|
|
|
|
CLK(NULL, "fac_fck", &fac_fck, CK_243X),
|
|
|
|
CLK("omap_hdq.0", "ick", &hdq_ick, CK_243X),
|
|
|
|
CLK("omap_hdq.1", "fck", &hdq_fck, CK_243X),
|
2010-12-09 14:24:16 +00:00
|
|
|
CLK("omap_i2c.1", "ick", &i2c1_ick, CK_243X),
|
2011-07-10 11:54:12 +00:00
|
|
|
CLK(NULL, "i2chs1_fck", &i2chs1_fck, CK_243X),
|
2010-12-09 14:24:16 +00:00
|
|
|
CLK("omap_i2c.2", "ick", &i2c2_ick, CK_243X),
|
2011-07-10 11:54:12 +00:00
|
|
|
CLK(NULL, "i2chs2_fck", &i2chs2_fck, CK_243X),
|
OMAP2 clock: split OMAP2420, OMAP2430 clock data into their own files
In preparation for multi-OMAP2 kernels, split
mach-omap2/clock2xxx_data.c into mach-omap2/clock2420_data.c and
mach-omap2/clock2430_data.c. 2430 uses a different device space
physical memory layout than past or future OMAPs, and we use a
different virtual memory layout as well, which causes trouble for
architecture-level code/data that tries to support both. We tried
using offsets from the virtual base last year, but those patches never
made it upstream; so after some discussion with Tony about the best
all-around approach, we'll just grit our teeth and duplicate the
structures. The maintenance advantages of a single kernel config that
can compile and boot on OMAP2, 3, and 4 platforms are simply too
compelling.
This approach does have some nice benefits beyond multi-OMAP 2 kernel
support. The runtime size of OMAP2420-specific and OMAP2430-specific
kernels is smaller, since unused clocks for the other OMAP2 chip will
no longer be compiled in. (At some point we will mark the clock data
__initdata and allocate it during registration, which will eliminate
the runtime memory advantage.) It also makes the clock trees slightly
easier to read, since 2420-specific and 2430-specific clocks are no
longer mixed together.
This patch also splits 2430-specific clock code into its own file,
mach-omap2/clock2430.c, which is only compiled in for 2430 builds -
mostly for organizational clarity.
While here, fix a bug in the OMAP2430 clock tree: "emul_ck" was
incorrectly marked as being 2420-only, when actually it is present on
both OMAP2420 and OMAP2430.
Thanks to Tony for some good discussions about how to approach this
problem.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Richard Woodruff <r-woodruff2@ti.com>
2010-02-23 05:09:22 +00:00
|
|
|
CLK(NULL, "gpmc_fck", &gpmc_fck, CK_243X),
|
|
|
|
CLK(NULL, "sdma_fck", &sdma_fck, CK_243X),
|
|
|
|
CLK(NULL, "sdma_ick", &sdma_ick, CK_243X),
|
2009-12-08 23:21:29 +00:00
|
|
|
CLK(NULL, "sdrc_ick", &sdrc_ick, CK_243X),
|
OMAP2 clock: split OMAP2420, OMAP2430 clock data into their own files
In preparation for multi-OMAP2 kernels, split
mach-omap2/clock2xxx_data.c into mach-omap2/clock2420_data.c and
mach-omap2/clock2430_data.c. 2430 uses a different device space
physical memory layout than past or future OMAPs, and we use a
different virtual memory layout as well, which causes trouble for
architecture-level code/data that tries to support both. We tried
using offsets from the virtual base last year, but those patches never
made it upstream; so after some discussion with Tony about the best
all-around approach, we'll just grit our teeth and duplicate the
structures. The maintenance advantages of a single kernel config that
can compile and boot on OMAP2, 3, and 4 platforms are simply too
compelling.
This approach does have some nice benefits beyond multi-OMAP 2 kernel
support. The runtime size of OMAP2420-specific and OMAP2430-specific
kernels is smaller, since unused clocks for the other OMAP2 chip will
no longer be compiled in. (At some point we will mark the clock data
__initdata and allocate it during registration, which will eliminate
the runtime memory advantage.) It also makes the clock trees slightly
easier to read, since 2420-specific and 2430-specific clocks are no
longer mixed together.
This patch also splits 2430-specific clock code into its own file,
mach-omap2/clock2430.c, which is only compiled in for 2430 builds -
mostly for organizational clarity.
While here, fix a bug in the OMAP2430 clock tree: "emul_ck" was
incorrectly marked as being 2420-only, when actually it is present on
both OMAP2420 and OMAP2430.
Thanks to Tony for some good discussions about how to approach this
problem.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Richard Woodruff <r-woodruff2@ti.com>
2010-02-23 05:09:22 +00:00
|
|
|
CLK(NULL, "des_ick", &des_ick, CK_243X),
|
2010-05-03 03:10:03 +00:00
|
|
|
CLK("omap-sham", "ick", &sha_ick, CK_243X),
|
OMAP2 clock: split OMAP2420, OMAP2430 clock data into their own files
In preparation for multi-OMAP2 kernels, split
mach-omap2/clock2xxx_data.c into mach-omap2/clock2420_data.c and
mach-omap2/clock2430_data.c. 2430 uses a different device space
physical memory layout than past or future OMAPs, and we use a
different virtual memory layout as well, which causes trouble for
architecture-level code/data that tries to support both. We tried
using offsets from the virtual base last year, but those patches never
made it upstream; so after some discussion with Tony about the best
all-around approach, we'll just grit our teeth and duplicate the
structures. The maintenance advantages of a single kernel config that
can compile and boot on OMAP2, 3, and 4 platforms are simply too
compelling.
This approach does have some nice benefits beyond multi-OMAP 2 kernel
support. The runtime size of OMAP2420-specific and OMAP2430-specific
kernels is smaller, since unused clocks for the other OMAP2 chip will
no longer be compiled in. (At some point we will mark the clock data
__initdata and allocate it during registration, which will eliminate
the runtime memory advantage.) It also makes the clock trees slightly
easier to read, since 2420-specific and 2430-specific clocks are no
longer mixed together.
This patch also splits 2430-specific clock code into its own file,
mach-omap2/clock2430.c, which is only compiled in for 2430 builds -
mostly for organizational clarity.
While here, fix a bug in the OMAP2430 clock tree: "emul_ck" was
incorrectly marked as being 2420-only, when actually it is present on
both OMAP2420 and OMAP2430.
Thanks to Tony for some good discussions about how to approach this
problem.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Richard Woodruff <r-woodruff2@ti.com>
2010-02-23 05:09:22 +00:00
|
|
|
CLK("omap_rng", "ick", &rng_ick, CK_243X),
|
2010-08-20 13:44:46 +00:00
|
|
|
CLK("omap-aes", "ick", &aes_ick, CK_243X),
|
OMAP2 clock: split OMAP2420, OMAP2430 clock data into their own files
In preparation for multi-OMAP2 kernels, split
mach-omap2/clock2xxx_data.c into mach-omap2/clock2420_data.c and
mach-omap2/clock2430_data.c. 2430 uses a different device space
physical memory layout than past or future OMAPs, and we use a
different virtual memory layout as well, which causes trouble for
architecture-level code/data that tries to support both. We tried
using offsets from the virtual base last year, but those patches never
made it upstream; so after some discussion with Tony about the best
all-around approach, we'll just grit our teeth and duplicate the
structures. The maintenance advantages of a single kernel config that
can compile and boot on OMAP2, 3, and 4 platforms are simply too
compelling.
This approach does have some nice benefits beyond multi-OMAP 2 kernel
support. The runtime size of OMAP2420-specific and OMAP2430-specific
kernels is smaller, since unused clocks for the other OMAP2 chip will
no longer be compiled in. (At some point we will mark the clock data
__initdata and allocate it during registration, which will eliminate
the runtime memory advantage.) It also makes the clock trees slightly
easier to read, since 2420-specific and 2430-specific clocks are no
longer mixed together.
This patch also splits 2430-specific clock code into its own file,
mach-omap2/clock2430.c, which is only compiled in for 2430 builds -
mostly for organizational clarity.
While here, fix a bug in the OMAP2430 clock tree: "emul_ck" was
incorrectly marked as being 2420-only, when actually it is present on
both OMAP2420 and OMAP2430.
Thanks to Tony for some good discussions about how to approach this
problem.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Richard Woodruff <r-woodruff2@ti.com>
2010-02-23 05:09:22 +00:00
|
|
|
CLK(NULL, "pka_ick", &pka_ick, CK_243X),
|
|
|
|
CLK(NULL, "usb_fck", &usb_fck, CK_243X),
|
2010-12-02 07:57:08 +00:00
|
|
|
CLK("musb-omap2430", "ick", &usbhs_ick, CK_243X),
|
2011-02-28 15:18:05 +00:00
|
|
|
CLK("omap_hsmmc.0", "ick", &mmchs1_ick, CK_243X),
|
2011-07-10 11:54:12 +00:00
|
|
|
CLK(NULL, "mmchs1_fck", &mmchs1_fck, CK_243X),
|
2011-02-28 15:18:05 +00:00
|
|
|
CLK("omap_hsmmc.1", "ick", &mmchs2_ick, CK_243X),
|
2011-07-10 11:54:12 +00:00
|
|
|
CLK(NULL, "mmchs2_fck", &mmchs2_fck, CK_243X),
|
2009-12-08 23:21:29 +00:00
|
|
|
CLK(NULL, "gpio5_ick", &gpio5_ick, CK_243X),
|
|
|
|
CLK(NULL, "gpio5_fck", &gpio5_fck, CK_243X),
|
|
|
|
CLK(NULL, "mdm_intc_ick", &mdm_intc_ick, CK_243X),
|
2011-02-28 15:18:05 +00:00
|
|
|
CLK("omap_hsmmc.0", "mmchsdb_fck", &mmchsdb1_fck, CK_243X),
|
|
|
|
CLK("omap_hsmmc.1", "mmchsdb_fck", &mmchsdb2_fck, CK_243X),
|
2011-09-20 11:30:16 +00:00
|
|
|
CLK("omap_timer.1", "32k_ck", &func_32k_ck, CK_243X),
|
|
|
|
CLK("omap_timer.2", "32k_ck", &func_32k_ck, CK_243X),
|
|
|
|
CLK("omap_timer.3", "32k_ck", &func_32k_ck, CK_243X),
|
|
|
|
CLK("omap_timer.4", "32k_ck", &func_32k_ck, CK_243X),
|
|
|
|
CLK("omap_timer.5", "32k_ck", &func_32k_ck, CK_243X),
|
|
|
|
CLK("omap_timer.6", "32k_ck", &func_32k_ck, CK_243X),
|
|
|
|
CLK("omap_timer.7", "32k_ck", &func_32k_ck, CK_243X),
|
|
|
|
CLK("omap_timer.8", "32k_ck", &func_32k_ck, CK_243X),
|
|
|
|
CLK("omap_timer.9", "32k_ck", &func_32k_ck, CK_243X),
|
|
|
|
CLK("omap_timer.10", "32k_ck", &func_32k_ck, CK_243X),
|
|
|
|
CLK("omap_timer.11", "32k_ck", &func_32k_ck, CK_243X),
|
|
|
|
CLK("omap_timer.12", "32k_ck", &func_32k_ck, CK_243X),
|
|
|
|
CLK("omap_timer.1", "sys_ck", &sys_ck, CK_243X),
|
|
|
|
CLK("omap_timer.2", "sys_ck", &sys_ck, CK_243X),
|
|
|
|
CLK("omap_timer.3", "sys_ck", &sys_ck, CK_243X),
|
|
|
|
CLK("omap_timer.4", "sys_ck", &sys_ck, CK_243X),
|
|
|
|
CLK("omap_timer.5", "sys_ck", &sys_ck, CK_243X),
|
|
|
|
CLK("omap_timer.6", "sys_ck", &sys_ck, CK_243X),
|
|
|
|
CLK("omap_timer.7", "sys_ck", &sys_ck, CK_243X),
|
|
|
|
CLK("omap_timer.8", "sys_ck", &sys_ck, CK_243X),
|
|
|
|
CLK("omap_timer.9", "sys_ck", &sys_ck, CK_243X),
|
|
|
|
CLK("omap_timer.10", "sys_ck", &sys_ck, CK_243X),
|
|
|
|
CLK("omap_timer.11", "sys_ck", &sys_ck, CK_243X),
|
|
|
|
CLK("omap_timer.12", "sys_ck", &sys_ck, CK_243X),
|
|
|
|
CLK("omap_timer.1", "alt_ck", &alt_ck, CK_243X),
|
|
|
|
CLK("omap_timer.2", "alt_ck", &alt_ck, CK_243X),
|
|
|
|
CLK("omap_timer.3", "alt_ck", &alt_ck, CK_243X),
|
|
|
|
CLK("omap_timer.4", "alt_ck", &alt_ck, CK_243X),
|
|
|
|
CLK("omap_timer.5", "alt_ck", &alt_ck, CK_243X),
|
|
|
|
CLK("omap_timer.6", "alt_ck", &alt_ck, CK_243X),
|
|
|
|
CLK("omap_timer.7", "alt_ck", &alt_ck, CK_243X),
|
|
|
|
CLK("omap_timer.8", "alt_ck", &alt_ck, CK_243X),
|
|
|
|
CLK("omap_timer.9", "alt_ck", &alt_ck, CK_243X),
|
|
|
|
CLK("omap_timer.10", "alt_ck", &alt_ck, CK_243X),
|
|
|
|
CLK("omap_timer.11", "alt_ck", &alt_ck, CK_243X),
|
|
|
|
CLK("omap_timer.12", "alt_ck", &alt_ck, CK_243X),
|
2009-12-08 23:21:29 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
/*
|
|
|
|
* init code
|
|
|
|
*/
|
|
|
|
|
OMAP2 clock: split OMAP2420, OMAP2430 clock data into their own files
In preparation for multi-OMAP2 kernels, split
mach-omap2/clock2xxx_data.c into mach-omap2/clock2420_data.c and
mach-omap2/clock2430_data.c. 2430 uses a different device space
physical memory layout than past or future OMAPs, and we use a
different virtual memory layout as well, which causes trouble for
architecture-level code/data that tries to support both. We tried
using offsets from the virtual base last year, but those patches never
made it upstream; so after some discussion with Tony about the best
all-around approach, we'll just grit our teeth and duplicate the
structures. The maintenance advantages of a single kernel config that
can compile and boot on OMAP2, 3, and 4 platforms are simply too
compelling.
This approach does have some nice benefits beyond multi-OMAP 2 kernel
support. The runtime size of OMAP2420-specific and OMAP2430-specific
kernels is smaller, since unused clocks for the other OMAP2 chip will
no longer be compiled in. (At some point we will mark the clock data
__initdata and allocate it during registration, which will eliminate
the runtime memory advantage.) It also makes the clock trees slightly
easier to read, since 2420-specific and 2430-specific clocks are no
longer mixed together.
This patch also splits 2430-specific clock code into its own file,
mach-omap2/clock2430.c, which is only compiled in for 2430 builds -
mostly for organizational clarity.
While here, fix a bug in the OMAP2430 clock tree: "emul_ck" was
incorrectly marked as being 2420-only, when actually it is present on
both OMAP2420 and OMAP2430.
Thanks to Tony for some good discussions about how to approach this
problem.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Richard Woodruff <r-woodruff2@ti.com>
2010-02-23 05:09:22 +00:00
|
|
|
int __init omap2430_clk_init(void)
|
2009-12-08 23:21:29 +00:00
|
|
|
{
|
|
|
|
const struct prcm_config *prcm;
|
|
|
|
struct omap_clk *c;
|
|
|
|
u32 clkrate;
|
OMAP2 clock: split OMAP2420, OMAP2430 clock data into their own files
In preparation for multi-OMAP2 kernels, split
mach-omap2/clock2xxx_data.c into mach-omap2/clock2420_data.c and
mach-omap2/clock2430_data.c. 2430 uses a different device space
physical memory layout than past or future OMAPs, and we use a
different virtual memory layout as well, which causes trouble for
architecture-level code/data that tries to support both. We tried
using offsets from the virtual base last year, but those patches never
made it upstream; so after some discussion with Tony about the best
all-around approach, we'll just grit our teeth and duplicate the
structures. The maintenance advantages of a single kernel config that
can compile and boot on OMAP2, 3, and 4 platforms are simply too
compelling.
This approach does have some nice benefits beyond multi-OMAP 2 kernel
support. The runtime size of OMAP2420-specific and OMAP2430-specific
kernels is smaller, since unused clocks for the other OMAP2 chip will
no longer be compiled in. (At some point we will mark the clock data
__initdata and allocate it during registration, which will eliminate
the runtime memory advantage.) It also makes the clock trees slightly
easier to read, since 2420-specific and 2430-specific clocks are no
longer mixed together.
This patch also splits 2430-specific clock code into its own file,
mach-omap2/clock2430.c, which is only compiled in for 2430 builds -
mostly for organizational clarity.
While here, fix a bug in the OMAP2430 clock tree: "emul_ck" was
incorrectly marked as being 2420-only, when actually it is present on
both OMAP2420 and OMAP2430.
Thanks to Tony for some good discussions about how to approach this
problem.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Richard Woodruff <r-woodruff2@ti.com>
2010-02-23 05:09:22 +00:00
|
|
|
|
|
|
|
prcm_clksrc_ctrl = OMAP2430_PRCM_CLKSRC_CTRL;
|
|
|
|
cm_idlest_pll = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST);
|
|
|
|
cpu_mask = RATE_IN_243X;
|
|
|
|
rate_table = omap2430_rate_table;
|
2009-12-08 23:21:29 +00:00
|
|
|
|
|
|
|
clk_init(&omap2_clk_functions);
|
|
|
|
|
OMAP2 clock: split OMAP2420, OMAP2430 clock data into their own files
In preparation for multi-OMAP2 kernels, split
mach-omap2/clock2xxx_data.c into mach-omap2/clock2420_data.c and
mach-omap2/clock2430_data.c. 2430 uses a different device space
physical memory layout than past or future OMAPs, and we use a
different virtual memory layout as well, which causes trouble for
architecture-level code/data that tries to support both. We tried
using offsets from the virtual base last year, but those patches never
made it upstream; so after some discussion with Tony about the best
all-around approach, we'll just grit our teeth and duplicate the
structures. The maintenance advantages of a single kernel config that
can compile and boot on OMAP2, 3, and 4 platforms are simply too
compelling.
This approach does have some nice benefits beyond multi-OMAP 2 kernel
support. The runtime size of OMAP2420-specific and OMAP2430-specific
kernels is smaller, since unused clocks for the other OMAP2 chip will
no longer be compiled in. (At some point we will mark the clock data
__initdata and allocate it during registration, which will eliminate
the runtime memory advantage.) It also makes the clock trees slightly
easier to read, since 2420-specific and 2430-specific clocks are no
longer mixed together.
This patch also splits 2430-specific clock code into its own file,
mach-omap2/clock2430.c, which is only compiled in for 2430 builds -
mostly for organizational clarity.
While here, fix a bug in the OMAP2430 clock tree: "emul_ck" was
incorrectly marked as being 2420-only, when actually it is present on
both OMAP2420 and OMAP2430.
Thanks to Tony for some good discussions about how to approach this
problem.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Richard Woodruff <r-woodruff2@ti.com>
2010-02-23 05:09:22 +00:00
|
|
|
for (c = omap2430_clks; c < omap2430_clks + ARRAY_SIZE(omap2430_clks);
|
|
|
|
c++)
|
2009-12-08 23:21:29 +00:00
|
|
|
clk_preinit(c->lk.clk);
|
|
|
|
|
|
|
|
osc_ck.rate = omap2_osc_clk_recalc(&osc_ck);
|
|
|
|
propagate_rate(&osc_ck);
|
2010-01-27 03:13:08 +00:00
|
|
|
sys_ck.rate = omap2xxx_sys_clk_recalc(&sys_ck);
|
2009-12-08 23:21:29 +00:00
|
|
|
propagate_rate(&sys_ck);
|
|
|
|
|
OMAP2 clock: split OMAP2420, OMAP2430 clock data into their own files
In preparation for multi-OMAP2 kernels, split
mach-omap2/clock2xxx_data.c into mach-omap2/clock2420_data.c and
mach-omap2/clock2430_data.c. 2430 uses a different device space
physical memory layout than past or future OMAPs, and we use a
different virtual memory layout as well, which causes trouble for
architecture-level code/data that tries to support both. We tried
using offsets from the virtual base last year, but those patches never
made it upstream; so after some discussion with Tony about the best
all-around approach, we'll just grit our teeth and duplicate the
structures. The maintenance advantages of a single kernel config that
can compile and boot on OMAP2, 3, and 4 platforms are simply too
compelling.
This approach does have some nice benefits beyond multi-OMAP 2 kernel
support. The runtime size of OMAP2420-specific and OMAP2430-specific
kernels is smaller, since unused clocks for the other OMAP2 chip will
no longer be compiled in. (At some point we will mark the clock data
__initdata and allocate it during registration, which will eliminate
the runtime memory advantage.) It also makes the clock trees slightly
easier to read, since 2420-specific and 2430-specific clocks are no
longer mixed together.
This patch also splits 2430-specific clock code into its own file,
mach-omap2/clock2430.c, which is only compiled in for 2430 builds -
mostly for organizational clarity.
While here, fix a bug in the OMAP2430 clock tree: "emul_ck" was
incorrectly marked as being 2420-only, when actually it is present on
both OMAP2420 and OMAP2430.
Thanks to Tony for some good discussions about how to approach this
problem.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Richard Woodruff <r-woodruff2@ti.com>
2010-02-23 05:09:22 +00:00
|
|
|
for (c = omap2430_clks; c < omap2430_clks + ARRAY_SIZE(omap2430_clks);
|
|
|
|
c++) {
|
|
|
|
clkdev_add(&c->lk);
|
|
|
|
clk_register(c->lk.clk);
|
|
|
|
omap2_init_clk_clkdm(c->lk.clk);
|
|
|
|
}
|
2009-12-08 23:21:29 +00:00
|
|
|
|
2011-02-25 22:49:53 +00:00
|
|
|
/* Disable autoidle on all clocks; let the PM code enable it later */
|
|
|
|
omap_clk_disable_autoidle_all();
|
|
|
|
|
2009-12-08 23:21:29 +00:00
|
|
|
/* Check the MPU rate set by bootloader */
|
|
|
|
clkrate = omap2xxx_clk_get_core_rate(&dpll_ck);
|
|
|
|
for (prcm = rate_table; prcm->mpu_speed; prcm++) {
|
|
|
|
if (!(prcm->flags & cpu_mask))
|
|
|
|
continue;
|
|
|
|
if (prcm->xtal_speed != sys_ck.rate)
|
|
|
|
continue;
|
|
|
|
if (prcm->dpll_speed <= clkrate)
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
curr_prcm_set = prcm;
|
|
|
|
|
|
|
|
recalculate_root_clocks();
|
|
|
|
|
OMAP2 clock: split OMAP2420, OMAP2430 clock data into their own files
In preparation for multi-OMAP2 kernels, split
mach-omap2/clock2xxx_data.c into mach-omap2/clock2420_data.c and
mach-omap2/clock2430_data.c. 2430 uses a different device space
physical memory layout than past or future OMAPs, and we use a
different virtual memory layout as well, which causes trouble for
architecture-level code/data that tries to support both. We tried
using offsets from the virtual base last year, but those patches never
made it upstream; so after some discussion with Tony about the best
all-around approach, we'll just grit our teeth and duplicate the
structures. The maintenance advantages of a single kernel config that
can compile and boot on OMAP2, 3, and 4 platforms are simply too
compelling.
This approach does have some nice benefits beyond multi-OMAP 2 kernel
support. The runtime size of OMAP2420-specific and OMAP2430-specific
kernels is smaller, since unused clocks for the other OMAP2 chip will
no longer be compiled in. (At some point we will mark the clock data
__initdata and allocate it during registration, which will eliminate
the runtime memory advantage.) It also makes the clock trees slightly
easier to read, since 2420-specific and 2430-specific clocks are no
longer mixed together.
This patch also splits 2430-specific clock code into its own file,
mach-omap2/clock2430.c, which is only compiled in for 2430 builds -
mostly for organizational clarity.
While here, fix a bug in the OMAP2430 clock tree: "emul_ck" was
incorrectly marked as being 2420-only, when actually it is present on
both OMAP2420 and OMAP2430.
Thanks to Tony for some good discussions about how to approach this
problem.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Richard Woodruff <r-woodruff2@ti.com>
2010-02-23 05:09:22 +00:00
|
|
|
pr_info("Clocking rate (Crystal/DPLL/MPU): %ld.%01ld/%ld/%ld MHz\n",
|
|
|
|
(sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
|
|
|
|
(dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
|
2009-12-08 23:21:29 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Only enable those clocks we will need, let the drivers
|
|
|
|
* enable other clocks as necessary
|
|
|
|
*/
|
|
|
|
clk_enable_init_clocks();
|
|
|
|
|
|
|
|
/* Avoid sleeping sleeping during omap2_clk_prepare_for_reboot() */
|
|
|
|
vclk = clk_get(NULL, "virt_prcm_set");
|
|
|
|
sclk = clk_get(NULL, "sys_ck");
|
|
|
|
dclk = clk_get(NULL, "dpll_ck");
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
2008-03-18 08:35:15 +00:00
|
|
|
|