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linux/drivers/mailbox/Kconfig

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ARM / highbank: add support for pl320 IPC The pl320 IPC allows for interprocessor communication between the highbank A9 and the EnergyCore Management Engine. The pl320 implements a straightforward mailbox protocol. Signed-off-by: Mark Langsdorf <mark.langsdorf@calxeda.com> Signed-off-by: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2013-01-28 16:13:14 +00:00
menuconfig MAILBOX
bool "Mailbox Hardware Support"
help
Mailbox is a framework to control hardware communication between
on-chip processors through queued messages and interrupt driven
signals. Say Y if your platform supports hardware mailboxes.
if MAILBOX
mailbox: arm_mhu: add driver for ARM MHU controller Add driver for the ARM Primecell Message-Handling-Unit(MHU) controller. Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org> Signed-off-by: Andy Green <andy.green@linaro.org> Signed-off-by: Vincent Yang <vincent.yang@socionext.com> Signed-off-by: Tetsuya Nuriya <nuriya.tetsuya@socionext.com>
2014-06-26 13:39:42 +00:00
config ARM_MHU
tristate "ARM MHU Mailbox"
depends on ARM_AMBA
help
Say Y here if you want to build the ARM MHU controller driver.
The controller has 3 mailbox channels, the last of which can be
used in Secure mode only.
ARM / highbank: add support for pl320 IPC The pl320 IPC allows for interprocessor communication between the highbank A9 and the EnergyCore Management Engine. The pl320 implements a straightforward mailbox protocol. Signed-off-by: Mark Langsdorf <mark.langsdorf@calxeda.com> Signed-off-by: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2013-01-28 16:13:14 +00:00
config PL320_MBOX
bool "ARM PL320 Mailbox"
depends on ARM_AMBA
help
An implementation of the ARM PL320 Interprocessor Communication
Mailbox (IPCM), tailored for the Calxeda Highbank. It is used to
send short messages between Highbank's A9 cores and the EnergyCore
Management Engine, primarily for cpufreq. Say Y here if you want
to use the PL320 IPCM support.
mailbox/omap: move the OMAP mailbox framework to drivers The mailbox hardware (in OMAP) uses a queued mailbox interrupt mechanism that provides a communication channel between processors through a set of registers and their associated interrupt signals by sending and receiving messages. The OMAP mailbox framework/driver code is moved to be under drivers/mailbox, in preparation for adapting to a common mailbox driver framework. This allows the build for OMAP mailbox to be enabled (it was disabled during the multi-platform support). As part of the migration from plat and mach code: - Kconfig symbols have been renamed to build OMAP1 or OMAP2+ drivers. - mailbox.h under plat-omap/plat/include has been split into a public and private header files. The public header has only the API related functions and types. - The module name mailbox.ko from plat-omap is changed to omap-mailbox.ko - The module name mailbox_mach.ko from mach-omapX is changed as mailbox_omap1.ko for OMAP1 mailbox_omap2.ko for OMAP2+ Cc: Tony Lindgren <tony@atomide.com> [gregkh@linuxfoundation.org: ack for staging part] Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Omar Ramirez Luna <omar.ramirez@copitl.com> Signed-off-by: Suman Anna <s-anna@ti.com>
2013-03-12 22:55:29 +00:00
config OMAP2PLUS_MBOX
tristate "OMAP2+ Mailbox framework support"
depends on ARCH_OMAP2PLUS
help
Mailbox implementation for OMAP family chips with hardware for
interprocessor communication involving DSP, IVA1.0 and IVA2 in
OMAP2/3; or IPU, IVA HD and DSP in OMAP4/5. Say Y here if you
want to use OMAP2+ Mailbox framework support.
config OMAP_MBOX_KFIFO_SIZE
int "Mailbox kfifo default buffer size (bytes)"
mailbox/omap: remove OMAP1 mailbox driver There are no existing users for OMAP1 mailbox driver in kernel. Commit ab6f775 "Removing dead OMAP_DSP" has cleaned up all the dead code related to the only possible user, including the creation of the mailbox platform device. Remove this stale driver so that the OMAP mailbox driver can be simplified and streamlined better for converting to mailbox framework. Signed-off-by: Suman Anna <s-anna@ti.com> Acked-by: Aaro Koskinen <aaro.koskinen@iki.fi> Signed-off-by: Tony Lindgren <tony@atomide.com>
2014-06-25 00:43:38 +00:00
depends on OMAP2PLUS_MBOX
mailbox/omap: move the OMAP mailbox framework to drivers The mailbox hardware (in OMAP) uses a queued mailbox interrupt mechanism that provides a communication channel between processors through a set of registers and their associated interrupt signals by sending and receiving messages. The OMAP mailbox framework/driver code is moved to be under drivers/mailbox, in preparation for adapting to a common mailbox driver framework. This allows the build for OMAP mailbox to be enabled (it was disabled during the multi-platform support). As part of the migration from plat and mach code: - Kconfig symbols have been renamed to build OMAP1 or OMAP2+ drivers. - mailbox.h under plat-omap/plat/include has been split into a public and private header files. The public header has only the API related functions and types. - The module name mailbox.ko from plat-omap is changed to omap-mailbox.ko - The module name mailbox_mach.ko from mach-omapX is changed as mailbox_omap1.ko for OMAP1 mailbox_omap2.ko for OMAP2+ Cc: Tony Lindgren <tony@atomide.com> [gregkh@linuxfoundation.org: ack for staging part] Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Omar Ramirez Luna <omar.ramirez@copitl.com> Signed-off-by: Suman Anna <s-anna@ti.com>
2013-03-12 22:55:29 +00:00
default 256
help
Specify the default size of mailbox's kfifo buffers (bytes).
This can also be changed at runtime (via the mbox_kfifo_size
module parameter).
Mailbox: Add support for Platform Communication Channel ACPI 5.0+ spec defines a generic mode of communication between the OS and a platform such as the BMC. This medium (PCC) is typically used by CPPC (ACPI CPU Performance management), RAS (ACPI reliability protocol) and MPST (ACPI Memory power states). This patch adds PCC support as a Mailbox Controller. As of ACPI v5.1 there is no provision for clients to lookup mailbox controllers in a way that Linux expects. e.g. in DT the clients can list the mailboxes they can associate with in the DT binding and then provide a unique index to lookup a channel within a mailbox. Since the ACPI spec doesn't have anything similar, we introduce a mailbox controller specific API so that when the client calls it, we know to lookup in the context of a specific controller. This also helps in keeping a consistent interface across DT and ACPI for such drivers. This patch implements basic PCC support using the ACPI v5.1 structures. IRQ mode support will be provided as follow up patches. Signed-off-by: Ashwin Chaugule <ashwin.chaugule@linaro.org> Reviewed-by: Mark Brown <broonie@kernel.org> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2014-11-13 00:59:38 +00:00
mailbox: rockchip: Add Rockchip mailbox driver This driver is found on RK3368 SoCs. The Mailbox module is a simple APB peripheral that allows both the Cortex-A53 MCU system to communicate by writing operation to generate interrupt. The registers are accessible by both CPU via APB interface. The Mailbox has the following main features: 1) Support dual-core system: Cortex-A53 and MCU. 2) Support APB interface. 3) Support four mailbox elements, each element includes one data word, one command word register and one flag bit that can represent one interrupt. 4) Four interrupts to Cortex-A53. 5) Four interrupts to MCU. 6) Provide 32 lock registers for software to use to indicate whether mailbox is occupied. [Jassi: Removed unused variable buf_base] Signed-off-by: Caesar Wang <wxt@rock-chips.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2015-10-27 07:31:45 +00:00
config ROCKCHIP_MBOX
bool "Rockchip Soc Intergrated Mailbox Support"
depends on ARCH_ROCKCHIP || COMPILE_TEST
help
This driver provides support for inter-processor communication
between CPU cores and MCU processor on Some Rockchip SOCs.
Please check it that the Soc you use have Mailbox hardware.
Say Y here if you want to use the Rockchip Mailbox support.
Mailbox: Add support for Platform Communication Channel ACPI 5.0+ spec defines a generic mode of communication between the OS and a platform such as the BMC. This medium (PCC) is typically used by CPPC (ACPI CPU Performance management), RAS (ACPI reliability protocol) and MPST (ACPI Memory power states). This patch adds PCC support as a Mailbox Controller. As of ACPI v5.1 there is no provision for clients to lookup mailbox controllers in a way that Linux expects. e.g. in DT the clients can list the mailboxes they can associate with in the DT binding and then provide a unique index to lookup a channel within a mailbox. Since the ACPI spec doesn't have anything similar, we introduce a mailbox controller specific API so that when the client calls it, we know to lookup in the context of a specific controller. This also helps in keeping a consistent interface across DT and ACPI for such drivers. This patch implements basic PCC support using the ACPI v5.1 structures. IRQ mode support will be provided as follow up patches. Signed-off-by: Ashwin Chaugule <ashwin.chaugule@linaro.org> Reviewed-by: Mark Brown <broonie@kernel.org> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2014-11-13 00:59:38 +00:00
config PCC
bool "Platform Communication Channel Driver"
depends on ACPI
PCC: Disable compilation by default PCC is made selectable only by clients which use it. e.g. CPPC Default it to disabled so that it is not included accidentally on platforms which dont use it. Signed-off-by: Ashwin Chaugule <ashwin.chaugule@linaro.org> Reviewed-by: Al Stone <al.stone@linaro.org> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2015-08-05 13:40:31 +00:00
default n
Mailbox: Add support for Platform Communication Channel ACPI 5.0+ spec defines a generic mode of communication between the OS and a platform such as the BMC. This medium (PCC) is typically used by CPPC (ACPI CPU Performance management), RAS (ACPI reliability protocol) and MPST (ACPI Memory power states). This patch adds PCC support as a Mailbox Controller. As of ACPI v5.1 there is no provision for clients to lookup mailbox controllers in a way that Linux expects. e.g. in DT the clients can list the mailboxes they can associate with in the DT binding and then provide a unique index to lookup a channel within a mailbox. Since the ACPI spec doesn't have anything similar, we introduce a mailbox controller specific API so that when the client calls it, we know to lookup in the context of a specific controller. This also helps in keeping a consistent interface across DT and ACPI for such drivers. This patch implements basic PCC support using the ACPI v5.1 structures. IRQ mode support will be provided as follow up patches. Signed-off-by: Ashwin Chaugule <ashwin.chaugule@linaro.org> Reviewed-by: Mark Brown <broonie@kernel.org> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2014-11-13 00:59:38 +00:00
help
ACPI 5.0+ spec defines a generic mode of communication
between the OS and a platform such as the BMC. This medium
(PCC) is typically used by CPPC (ACPI CPU Performance management),
RAS (ACPI reliability protocol) and MPST (ACPI Memory power
states). Select this driver if your platform implements the
PCC clients mentioned above.
mailbox: Add Altera mailbox driver The Altera mailbox allows for interprocessor communication. It supports only one channel and work as either sender or receiver. Signed-off-by: Ley Foon Tan <lftan@altera.com>
2015-02-04 08:32:18 +00:00
config ALTERA_MBOX
tristate "Altera Mailbox"
mailbox: altera: Add dependency on HAS_IOMEM Not all architectures have io memory. Fixes: drivers/built-in.o: In function `altera_mbox_probe': mailbox-altera.c:(.text+0x409fd2): undefined reference to `devm_ioremap_resource' Signed-off-by: Richard Weinberger <richard@nod.at> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2015-05-04 18:59:46 +00:00
depends on HAS_IOMEM
mailbox: Add Altera mailbox driver The Altera mailbox allows for interprocessor communication. It supports only one channel and work as either sender or receiver. Signed-off-by: Ley Foon Tan <lftan@altera.com>
2015-02-04 08:32:18 +00:00
help
An implementation of the Altera Mailbox soft core. It is used
to send message between processors. Say Y here if you want to use the
Altera mailbox support.
mailbox: Enable BCM2835 mailbox support This mailbox driver provides a single mailbox channel to write 32-bit values to the VPU and get a 32-bit response. The Raspberry Pi firmware uses this mailbox channel to implement firmware calls, while Roku 2 (despite being derived from the same firmware tree) doesn't. The driver was originally submitted by Lubomir, based on the out-of-tree 2708 mailbox driver. Eric Anholt fixed it up for upstreaming, with the major functional change being that it now has no notion of multiple channels (since that is a firmware-dependent concept) and instead the raspberrypi-firmware driver will do that bit-twiddling in its own messages. [Jassi: made the 'mbox_chan_ops' struct as const and removed a redundant variable] Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Signed-off-by: Craig McGeachie <slapdau@yahoo.com.au> Signed-off-by: Eric Anholt <eric@anholt.net> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2015-05-05 20:27:45 +00:00
config BCM2835_MBOX
tristate "BCM2835 Mailbox"
depends on ARCH_BCM2835
help
An implementation of the BCM2385 Mailbox. It is used to invoke
the services of the Videocore. Say Y here if you want to use the
BCM2835 Mailbox.
mailbox: Add support for ST's Mailbox IP ST's platforms currently support a maximum of 5 Mailboxes, one for each of the supported co-processors situated on the platform. Each Mailbox is divided up into 4 instances which consist of 32 channels. Messages are passed between the application and co-processors using shared memory areas. It is the Client's responsibility to manage these areas. Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2015-10-16 07:21:28 +00:00
config STI_MBOX
tristate "STI Mailbox framework support"
depends on ARCH_STI && OF
help
Mailbox implementation for STMicroelectonics family chips with
hardware for interprocessor communication.
mailbox: Hi6220: add mailbox driver Add driver for Hi6220 mailbox, the mailbox communicates with MCU; for sending data, it can support two methods for low level implementation: one is to use interrupt as acknowledge, another is automatic mode which without any acknowledge. These two methods have been supported in the driver. For receiving data, it will depend on the interrupt to notify the channel has incoming message. Now mailbox driver is used to send message to MCU to control dynamic voltage and frequency scaling for CPU, GPU and DDR. Signed-off-by: Leo Yan <leo.yan@linaro.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2016-02-15 13:50:24 +00:00
config HI6220_MBOX
tristate "Hi6220 Mailbox"
depends on ARCH_HISI
help
An implementation of the hi6220 mailbox. It is used to send message
between application processors and MCU. Say Y here if you want to
build Hi6220 mailbox controller driver.
mailbox: Add generic mechanism for testing Mailbox Controllers This particular Client implementation uses shared memory in order to pass messages between Mailbox users; however, it can be easily hacked to support any type of Controller. Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2015-10-16 07:21:30 +00:00
config MAILBOX_TEST
tristate "Mailbox Test Client"
depends on OF
mailbox: Fix dependencies for !HAS_IOMEM archs Not every arch has io memory. So, unbreak the build by fixing the dependencies. Signed-off-by: Richard Weinberger <richard@nod.at> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2016-01-25 22:24:09 +00:00
depends on HAS_IOMEM
mailbox: Add generic mechanism for testing Mailbox Controllers This particular Client implementation uses shared memory in order to pass messages between Mailbox users; however, it can be easily hacked to support any type of Controller. Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2015-10-16 07:21:30 +00:00
help
Test client to help with testing new Controller driver
implementations.
mailbox: Add support for APM X-Gene platform mailbox driver X-Gene mailbox controller provides 8 mailbox channels, with each channel has a dedicated interrupt line. Signed-off-by: Feng Kan <fkan@apm.com> Signed-off-by: Duc Dang <dhdang@apm.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2016-02-13 03:39:26 +00:00
config XGENE_SLIMPRO_MBOX
tristate "APM SoC X-Gene SLIMpro Mailbox Controller"
depends on ARCH_XGENE
help
An implementation of the APM X-Gene Interprocessor Communication
Mailbox (IPCM) between the ARM 64-bit cores and SLIMpro controller.
It is used to send short messages between ARM64-bit cores and
the SLIMpro Management Engine, primarily for PM. Say Y here if you
want to use the APM X-Gene SLIMpro IPCM support.
ARM / highbank: add support for pl320 IPC The pl320 IPC allows for interprocessor communication between the highbank A9 and the EnergyCore Management Engine. The pl320 implements a straightforward mailbox protocol. Signed-off-by: Mark Langsdorf <mark.langsdorf@calxeda.com> Signed-off-by: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2013-01-28 16:13:14 +00:00
endif
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