2008-10-23 07:20:33 +00:00
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#ifndef _ASM_X86_IRQ_REMAPPING_H
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#define _ASM_X86_IRQ_REMAPPING_H
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x64, x2apic/intr-remap: IO-APIC support for interrupt-remapping
IO-APIC support in the presence of interrupt-remapping infrastructure.
IO-APIC RTE will be programmed with interrupt-remapping table entry(IRTE)
index and the IRTE will contain information about the vector, cpu destination,
trigger mode etc, which traditionally was present in the IO-APIC RTE.
Introduce a new irq_chip for cleaner irq migration (in the process
context as opposed to the current irq migration in the context of an interrupt.
interrupt-remapping infrastructure will help us achieve this cleanly).
For edge triggered, irq migration is a simple atomic update(of vector
and cpu destination) of IRTE and flush the hardware cache.
For level triggered, we need to modify the io-apic RTE aswell with the update
vector information, along with modifying IRTE with vector and cpu destination.
So irq migration for level triggered is little bit more complex compared to
edge triggered migration. But the good news is, we use the same algorithm
for level triggered migration as we have today, only difference being,
we now initiate the irq migration from process context instead of the
interrupt context.
In future, when we do a directed EOI (combined with cpu EOI broadcast
suppression) to the IO-APIC, level triggered irq migration will also be
as simple as edge triggered migration and we can do the irq migration
with a simple atomic update to IO-APIC RTE.
TBD: some tests/changes needed in the presence of fixup_irqs() for
level triggered irq migration.
Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com>
Cc: akpm@linux-foundation.org
Cc: arjan@linux.intel.com
Cc: andi@firstfloor.org
Cc: ebiederm@xmission.com
Cc: jbarnes@virtuousgeek.org
Cc: steiner@sgi.com
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-07-10 18:16:56 +00:00
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2009-04-20 20:02:27 +00:00
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#define IRTE_DEST(dest) ((x2apic_mode) ? dest : dest << 8)
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x64, x2apic/intr-remap: IO-APIC support for interrupt-remapping
IO-APIC support in the presence of interrupt-remapping infrastructure.
IO-APIC RTE will be programmed with interrupt-remapping table entry(IRTE)
index and the IRTE will contain information about the vector, cpu destination,
trigger mode etc, which traditionally was present in the IO-APIC RTE.
Introduce a new irq_chip for cleaner irq migration (in the process
context as opposed to the current irq migration in the context of an interrupt.
interrupt-remapping infrastructure will help us achieve this cleanly).
For edge triggered, irq migration is a simple atomic update(of vector
and cpu destination) of IRTE and flush the hardware cache.
For level triggered, we need to modify the io-apic RTE aswell with the update
vector information, along with modifying IRTE with vector and cpu destination.
So irq migration for level triggered is little bit more complex compared to
edge triggered migration. But the good news is, we use the same algorithm
for level triggered migration as we have today, only difference being,
we now initiate the irq migration from process context instead of the
interrupt context.
In future, when we do a directed EOI (combined with cpu EOI broadcast
suppression) to the IO-APIC, level triggered irq migration will also be
as simple as edge triggered migration and we can do the irq migration
with a simple atomic update to IO-APIC RTE.
TBD: some tests/changes needed in the presence of fixup_irqs() for
level triggered irq migration.
Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com>
Cc: akpm@linux-foundation.org
Cc: arjan@linux.intel.com
Cc: andi@firstfloor.org
Cc: ebiederm@xmission.com
Cc: jbarnes@virtuousgeek.org
Cc: steiner@sgi.com
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-07-10 18:16:56 +00:00
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2011-08-24 00:05:25 +00:00
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#ifdef CONFIG_IRQ_REMAP
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2011-08-24 00:05:24 +00:00
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static void irq_remap_modify_chip_defaults(struct irq_chip *chip);
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2010-08-27 18:09:49 +00:00
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static inline void prepare_irte(struct irte *irte, int vector,
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unsigned int dest)
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{
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memset(irte, 0, sizeof(*irte));
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irte->present = 1;
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irte->dst_mode = apic->irq_dest_mode;
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/*
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* Trigger mode in the IRTE will always be edge, and for IO-APIC, the
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* actual level or edge trigger will be setup in the IO-APIC
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* RTE. This will help simplify level triggered irq migration.
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* For more details, see the comments (in io_apic.c) explainig IO-APIC
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* irq migration in the presence of interrupt-remapping.
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*/
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irte->trigger_mode = 0;
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irte->dlvry_mode = apic->irq_delivery_mode;
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irte->vector = vector;
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irte->dest_id = IRTE_DEST(dest);
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irte->redir_hint = 1;
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}
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2010-10-11 09:55:37 +00:00
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static inline bool irq_remapped(struct irq_cfg *cfg)
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{
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return cfg->irq_2_iommu.iommu != NULL;
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}
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2010-08-27 18:09:49 +00:00
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#else
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static void prepare_irte(struct irte *irte, int vector, unsigned int dest)
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{
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}
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2010-10-11 09:55:37 +00:00
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static inline bool irq_remapped(struct irq_cfg *cfg)
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{
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return false;
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}
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2011-08-24 00:05:24 +00:00
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static inline void irq_remap_modify_chip_defaults(struct irq_chip *chip)
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{
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}
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2010-08-27 18:09:49 +00:00
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#endif
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2008-10-23 07:20:33 +00:00
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#endif /* _ASM_X86_IRQ_REMAPPING_H */
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