2019-04-05 11:00:15 +00:00
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/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2019 Intel Corporation
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*/
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#ifndef __INTEL_PM_H__
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#define __INTEL_PM_H__
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#include <linux/types.h>
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2020-05-22 13:18:43 +00:00
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#include "display/intel_bw.h"
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2020-02-25 17:11:13 +00:00
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#include "display/intel_global_state.h"
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2019-04-29 12:29:37 +00:00
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#include "i915_reg.h"
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2019-04-05 11:00:15 +00:00
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struct drm_device;
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struct drm_i915_private;
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struct i915_request;
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2019-06-28 08:55:13 +00:00
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struct intel_atomic_state;
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2019-04-05 11:00:15 +00:00
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struct intel_crtc;
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struct intel_crtc_state;
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struct intel_plane;
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struct skl_ddb_entry;
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struct skl_pipe_wm;
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struct skl_wm_level;
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void intel_init_clock_gating(struct drm_i915_private *dev_priv);
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void intel_suspend_hw(struct drm_i915_private *dev_priv);
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int ilk_wm_max_level(const struct drm_i915_private *dev_priv);
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void intel_update_watermarks(struct intel_crtc *crtc);
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void intel_init_pm(struct drm_i915_private *dev_priv);
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void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
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void intel_pm_setup(struct drm_i915_private *dev_priv);
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void g4x_wm_get_hw_state(struct drm_i915_private *dev_priv);
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void vlv_wm_get_hw_state(struct drm_i915_private *dev_priv);
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void ilk_wm_get_hw_state(struct drm_i915_private *dev_priv);
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void skl_wm_get_hw_state(struct drm_i915_private *dev_priv);
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drm/i915: Manipulate DBuf slices properly
Start manipulating DBuf slices as a mask,
but not as a total number, as current approach
doesn't give us full control on all combinations
of slices, which we might need(like enabling S2
only can't enabled by setting enabled_slices=1).
Removed wrong code from intel_get_ddb_size as
it doesn't match to BSpec. For now still just
use DBuf slice until proper algorithm is implemented.
Other minor code refactoring to get prepared
for major DBuf assignment changes landed:
- As now enabled slices contain a mask
we still need some value which should
reflect how much DBuf slices are supported
by the platform, now device info contains
num_supported_dbuf_slices.
- Removed unneeded assertion as we are now
manipulating slices in a more proper way.
v2: Start using enabled_slices in dev_priv
v3: "enabled_slices" is now "enabled_dbuf_slices_mask",
as this now sits in dev_priv independently.
v4: - Fixed debug print formatting to hex(Matt Roper)
- Optimized dbuf slice updates to be used only
if slice union is different from current conf(Matt Roper)
- Fixed some functions to be static(Matt Roper)
- Created a parameterized version for DBUF_CTL to
simplify DBuf programming cycle(Matt Roper)
- Removed unrequred field from GEN10_FEATURES(Matt Roper)
v5: - Removed redundant programming dbuf slices helper(Ville Syrjälä)
- Started to use parameterized loop for hw readout to get slices
(Ville Syrjälä)
- Added back assertion checking amount of DBUF slices enabled
after DC states 5/6 transition, also added new assertion
as starting from ICL DMC seems to restore the last DBuf
power state set, rather than power up all dbuf slices
as assertion was previously expecting(Ville Syrjälä)
v6: - Now using enum for DBuf slices in this patch (Ville Syrjälä)
- Removed gen11_assert_dbuf_enabled and put gen9_assert_dbuf_enabled
back, as we really need to have a single unified assert here
however currently enabling always slice 1 is enforced by BSpec,
so we will have to OR enabled slices mask with 1 in order
to be consistent with BSpec, that way we can unify that
assertion and against the actual state from the driver, but
not some hardcoded value.(concluded with Ville)
- Remove parameterized DBUF_CTL version, to extract it to another
patch.(Ville Syrjälä)
v7:
- Removed unneeded hardcoded return value for older gens from
intel_enabled_dbuf_slices_mask - this now is handled in a
unified manner since device info anyway returns max dbuf slices
as 1 for older platforms(Matthew Roper)
- Now using INTEL_INFO(dev_priv)->num_supported_dbuf_slices instead
of intel_dbuf_max_slices function as it is trivial(Matthew Roper)
v8: - Fixed icl_dbuf_disable to disable all dbufs still(Ville Syrjälä)
v9: - Renamed _DBUF_CTL_S to DBUF_CTL_S(Ville Syrjälä)
- Now using power_domain mutex to protect from race condition, which
can occur because intel_dbuf_slices_update might be running in
parallel to gen9_dc_off_power_well_enable being called from
intel_dp_detect for instance, which causes assertion triggered by
race condition, as gen9_assert_dbuf_enabled might preempt this
when registers were already updated, while dev_priv was not.
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200202230630.8975-6-stanislav.lisovskiy@intel.com
2020-02-02 23:06:29 +00:00
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u8 intel_enabled_dbuf_slices_mask(struct drm_i915_private *dev_priv);
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2019-04-05 11:00:15 +00:00
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void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc,
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struct skl_ddb_entry *ddb_y,
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struct skl_ddb_entry *ddb_uv);
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2020-05-20 15:00:58 +00:00
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void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv);
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u16 intel_get_ddb_size(struct drm_i915_private *dev_priv);
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u32 skl_ddb_dbuf_slice_mask(struct drm_i915_private *dev_priv,
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const struct skl_ddb_entry *entry);
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2019-04-05 11:00:15 +00:00
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void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
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struct skl_pipe_wm *out);
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void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
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void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
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2020-05-13 09:38:13 +00:00
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bool intel_can_enable_sagv(struct drm_i915_private *dev_priv,
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const struct intel_bw_state *bw_state);
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2019-04-05 11:00:15 +00:00
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int intel_enable_sagv(struct drm_i915_private *dev_priv);
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int intel_disable_sagv(struct drm_i915_private *dev_priv);
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2020-04-15 14:39:04 +00:00
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void intel_sagv_pre_plane_update(struct intel_atomic_state *state);
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void intel_sagv_post_plane_update(struct intel_atomic_state *state);
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2019-04-05 11:00:15 +00:00
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bool skl_wm_level_equals(const struct skl_wm_level *l1,
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const struct skl_wm_level *l2);
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bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb,
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const struct skl_ddb_entry *entries,
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int num_entries, int ignore_idx);
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void skl_write_plane_wm(struct intel_plane *plane,
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const struct intel_crtc_state *crtc_state);
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void skl_write_cursor_wm(struct intel_plane *plane,
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const struct intel_crtc_state *crtc_state);
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2019-11-27 19:05:51 +00:00
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bool ilk_disable_lp_wm(struct drm_i915_private *dev_priv);
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2019-04-05 11:00:15 +00:00
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void intel_init_ipc(struct drm_i915_private *dev_priv);
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void intel_enable_ipc(struct drm_i915_private *dev_priv);
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2019-06-06 12:22:00 +00:00
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bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable);
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2019-04-29 12:29:37 +00:00
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2020-02-25 17:11:13 +00:00
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struct intel_dbuf_state {
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struct intel_global_state base;
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u8 enabled_slices;
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u8 active_pipes;
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};
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int intel_dbuf_init(struct drm_i915_private *dev_priv);
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struct intel_dbuf_state *
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intel_atomic_get_dbuf_state(struct intel_atomic_state *state);
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#define to_intel_dbuf_state(x) container_of((x), struct intel_dbuf_state, base)
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#define intel_atomic_get_old_dbuf_state(state) \
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to_intel_dbuf_state(intel_atomic_get_old_global_obj_state(state, &to_i915(state->base.dev)->dbuf.obj))
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#define intel_atomic_get_new_dbuf_state(state) \
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to_intel_dbuf_state(intel_atomic_get_new_global_obj_state(state, &to_i915(state->base.dev)->dbuf.obj))
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int intel_dbuf_init(struct drm_i915_private *dev_priv);
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2020-02-25 17:11:15 +00:00
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void intel_dbuf_pre_plane_update(struct intel_atomic_state *state);
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void intel_dbuf_post_plane_update(struct intel_atomic_state *state);
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2020-02-25 17:11:13 +00:00
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2019-04-05 11:00:15 +00:00
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#endif /* __INTEL_PM_H__ */
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