2008-02-07 08:14:55 +00:00
|
|
|
/*
|
2014-12-28 06:44:45 +00:00
|
|
|
* Freescale MPC85xx Memory Controller kernel module
|
2008-02-07 08:14:55 +00:00
|
|
|
*
|
2013-11-25 10:28:41 +00:00
|
|
|
* Parts Copyrighted (c) 2013 by Freescale Semiconductor, Inc.
|
|
|
|
*
|
2008-02-07 08:14:55 +00:00
|
|
|
* Author: Dave Jiang <djiang@mvista.com>
|
|
|
|
*
|
|
|
|
* 2006-2007 (c) MontaVista Software, Inc. This file is licensed under
|
|
|
|
* the terms of the GNU General Public License version 2. This program
|
|
|
|
* is licensed "as is" without any warranty of any kind, whether express
|
|
|
|
* or implied.
|
|
|
|
*
|
|
|
|
*/
|
|
|
|
#include <linux/module.h>
|
|
|
|
#include <linux/init.h>
|
|
|
|
#include <linux/interrupt.h>
|
|
|
|
#include <linux/ctype.h>
|
|
|
|
#include <linux/io.h>
|
|
|
|
#include <linux/mod_devicetable.h>
|
|
|
|
#include <linux/edac.h>
|
2008-10-16 05:04:28 +00:00
|
|
|
#include <linux/smp.h>
|
include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 08:04:11 +00:00
|
|
|
#include <linux/gfp.h>
|
2015-12-10 19:07:12 +00:00
|
|
|
#include <linux/fsl/edac.h>
|
2008-02-07 08:14:55 +00:00
|
|
|
|
|
|
|
#include <linux/of_platform.h>
|
|
|
|
#include <linux/of_device.h>
|
|
|
|
#include "edac_module.h"
|
|
|
|
#include "mpc85xx_edac.h"
|
2016-08-11 20:15:18 +00:00
|
|
|
#include "fsl_ddr_edac.h"
|
2008-02-07 08:14:55 +00:00
|
|
|
|
|
|
|
static int edac_dev_idx;
|
2009-10-26 23:50:10 +00:00
|
|
|
#ifdef CONFIG_PCI
|
2008-02-07 08:14:55 +00:00
|
|
|
static int edac_pci_idx;
|
2009-10-26 23:50:10 +00:00
|
|
|
#endif
|
2008-02-07 08:14:55 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* PCI Err defines
|
|
|
|
*/
|
|
|
|
#ifdef CONFIG_PCI
|
|
|
|
static u32 orig_pci_err_cap_dr;
|
|
|
|
static u32 orig_pci_err_en;
|
|
|
|
#endif
|
|
|
|
|
|
|
|
static u32 orig_l2_err_disable;
|
|
|
|
|
|
|
|
/**************************** PCI Err device ***************************/
|
|
|
|
#ifdef CONFIG_PCI
|
|
|
|
|
|
|
|
static void mpc85xx_pci_check(struct edac_pci_ctl_info *pci)
|
|
|
|
{
|
|
|
|
struct mpc85xx_pci_pdata *pdata = pci->pvt_info;
|
|
|
|
u32 err_detect;
|
|
|
|
|
|
|
|
err_detect = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR);
|
|
|
|
|
|
|
|
/* master aborts can happen during PCI config cycles */
|
|
|
|
if (!(err_detect & ~(PCI_EDE_MULTI_ERR | PCI_EDE_MST_ABRT))) {
|
|
|
|
out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, err_detect);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2016-08-09 21:55:39 +00:00
|
|
|
pr_err("PCI error(s) detected\n");
|
|
|
|
pr_err("PCI/X ERR_DR register: %#08x\n", err_detect);
|
2008-02-07 08:14:55 +00:00
|
|
|
|
2016-08-09 21:55:39 +00:00
|
|
|
pr_err("PCI/X ERR_ATTRIB register: %#08x\n",
|
2008-02-07 08:14:55 +00:00
|
|
|
in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ATTRIB));
|
2016-08-09 21:55:39 +00:00
|
|
|
pr_err("PCI/X ERR_ADDR register: %#08x\n",
|
2008-02-07 08:14:55 +00:00
|
|
|
in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ADDR));
|
2016-08-09 21:55:39 +00:00
|
|
|
pr_err("PCI/X ERR_EXT_ADDR register: %#08x\n",
|
2008-02-07 08:14:55 +00:00
|
|
|
in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EXT_ADDR));
|
2016-08-09 21:55:39 +00:00
|
|
|
pr_err("PCI/X ERR_DL register: %#08x\n",
|
2008-02-07 08:14:55 +00:00
|
|
|
in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DL));
|
2016-08-09 21:55:39 +00:00
|
|
|
pr_err("PCI/X ERR_DH register: %#08x\n",
|
2008-02-07 08:14:55 +00:00
|
|
|
in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DH));
|
|
|
|
|
|
|
|
/* clear error bits */
|
|
|
|
out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, err_detect);
|
|
|
|
|
|
|
|
if (err_detect & PCI_EDE_PERR_MASK)
|
|
|
|
edac_pci_handle_pe(pci, pci->ctl_name);
|
|
|
|
|
|
|
|
if ((err_detect & ~PCI_EDE_MULTI_ERR) & ~PCI_EDE_PERR_MASK)
|
|
|
|
edac_pci_handle_npe(pci, pci->ctl_name);
|
|
|
|
}
|
|
|
|
|
2013-11-25 10:28:41 +00:00
|
|
|
static void mpc85xx_pcie_check(struct edac_pci_ctl_info *pci)
|
|
|
|
{
|
|
|
|
struct mpc85xx_pci_pdata *pdata = pci->pvt_info;
|
2016-08-15 19:08:49 +00:00
|
|
|
u32 err_detect, err_cap_stat;
|
2013-11-25 10:28:41 +00:00
|
|
|
|
|
|
|
err_detect = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR);
|
2016-08-15 19:08:49 +00:00
|
|
|
err_cap_stat = in_be32(pdata->pci_vbase + MPC85XX_PCI_GAS_TIMR);
|
2013-11-25 10:28:41 +00:00
|
|
|
|
|
|
|
pr_err("PCIe error(s) detected\n");
|
|
|
|
pr_err("PCIe ERR_DR register: 0x%08x\n", err_detect);
|
2016-08-15 19:08:49 +00:00
|
|
|
pr_err("PCIe ERR_CAP_STAT register: 0x%08x\n", err_cap_stat);
|
2013-11-25 10:28:41 +00:00
|
|
|
pr_err("PCIe ERR_CAP_R0 register: 0x%08x\n",
|
|
|
|
in_be32(pdata->pci_vbase + MPC85XX_PCIE_ERR_CAP_R0));
|
|
|
|
pr_err("PCIe ERR_CAP_R1 register: 0x%08x\n",
|
|
|
|
in_be32(pdata->pci_vbase + MPC85XX_PCIE_ERR_CAP_R1));
|
|
|
|
pr_err("PCIe ERR_CAP_R2 register: 0x%08x\n",
|
|
|
|
in_be32(pdata->pci_vbase + MPC85XX_PCIE_ERR_CAP_R2));
|
|
|
|
pr_err("PCIe ERR_CAP_R3 register: 0x%08x\n",
|
|
|
|
in_be32(pdata->pci_vbase + MPC85XX_PCIE_ERR_CAP_R3));
|
|
|
|
|
|
|
|
/* clear error bits */
|
|
|
|
out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, err_detect);
|
2016-08-15 19:08:49 +00:00
|
|
|
|
|
|
|
/* reset error capture */
|
|
|
|
out_be32(pdata->pci_vbase + MPC85XX_PCI_GAS_TIMR, err_cap_stat | 0x1);
|
2013-11-25 10:28:41 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static int mpc85xx_pcie_find_capability(struct device_node *np)
|
|
|
|
{
|
|
|
|
struct pci_controller *hose;
|
|
|
|
|
|
|
|
if (!np)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
hose = pci_find_hose_for_OF_device(np);
|
|
|
|
|
|
|
|
return early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP);
|
|
|
|
}
|
|
|
|
|
2008-02-07 08:14:55 +00:00
|
|
|
static irqreturn_t mpc85xx_pci_isr(int irq, void *dev_id)
|
|
|
|
{
|
|
|
|
struct edac_pci_ctl_info *pci = dev_id;
|
|
|
|
struct mpc85xx_pci_pdata *pdata = pci->pvt_info;
|
|
|
|
u32 err_detect;
|
|
|
|
|
|
|
|
err_detect = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR);
|
|
|
|
|
|
|
|
if (!err_detect)
|
|
|
|
return IRQ_NONE;
|
|
|
|
|
2013-11-25 10:28:41 +00:00
|
|
|
if (pdata->is_pcie)
|
|
|
|
mpc85xx_pcie_check(pci);
|
|
|
|
else
|
|
|
|
mpc85xx_pci_check(pci);
|
2008-02-07 08:14:55 +00:00
|
|
|
|
|
|
|
return IRQ_HANDLED;
|
|
|
|
}
|
|
|
|
|
2015-12-10 19:07:12 +00:00
|
|
|
static int mpc85xx_pci_err_probe(struct platform_device *op)
|
2008-02-07 08:14:55 +00:00
|
|
|
{
|
|
|
|
struct edac_pci_ctl_info *pci;
|
|
|
|
struct mpc85xx_pci_pdata *pdata;
|
2015-12-10 19:07:12 +00:00
|
|
|
struct mpc85xx_edac_pci_plat_data *plat_data;
|
|
|
|
struct device_node *of_node;
|
2008-07-25 08:49:14 +00:00
|
|
|
struct resource r;
|
2008-02-07 08:14:55 +00:00
|
|
|
int res = 0;
|
|
|
|
|
2008-07-25 08:49:14 +00:00
|
|
|
if (!devres_open_group(&op->dev, mpc85xx_pci_err_probe, GFP_KERNEL))
|
2008-02-07 08:14:55 +00:00
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
pci = edac_pci_alloc_ctl_info(sizeof(*pdata), "mpc85xx_pci_err");
|
|
|
|
if (!pci)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
2012-08-28 07:44:08 +00:00
|
|
|
/* make sure error reporting method is sane */
|
|
|
|
switch (edac_op_state) {
|
|
|
|
case EDAC_OPSTATE_POLL:
|
|
|
|
case EDAC_OPSTATE_INT:
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
edac_op_state = EDAC_OPSTATE_INT;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2008-02-07 08:14:55 +00:00
|
|
|
pdata = pci->pvt_info;
|
|
|
|
pdata->name = "mpc85xx_pci_err";
|
2013-11-25 10:28:41 +00:00
|
|
|
|
2015-12-10 19:07:12 +00:00
|
|
|
plat_data = op->dev.platform_data;
|
|
|
|
if (!plat_data) {
|
|
|
|
dev_err(&op->dev, "no platform data");
|
|
|
|
res = -ENXIO;
|
|
|
|
goto err;
|
|
|
|
}
|
|
|
|
of_node = plat_data->of_node;
|
|
|
|
|
|
|
|
if (mpc85xx_pcie_find_capability(of_node) > 0)
|
2013-11-25 10:28:41 +00:00
|
|
|
pdata->is_pcie = true;
|
|
|
|
|
2008-07-25 08:49:14 +00:00
|
|
|
dev_set_drvdata(&op->dev, pci);
|
|
|
|
pci->dev = &op->dev;
|
2008-02-07 08:14:55 +00:00
|
|
|
pci->mod_name = EDAC_MOD_STR;
|
|
|
|
pci->ctl_name = pdata->name;
|
2009-03-24 23:38:21 +00:00
|
|
|
pci->dev_name = dev_name(&op->dev);
|
2008-02-07 08:14:55 +00:00
|
|
|
|
2013-11-25 10:28:41 +00:00
|
|
|
if (edac_op_state == EDAC_OPSTATE_POLL) {
|
|
|
|
if (pdata->is_pcie)
|
|
|
|
pci->edac_check = mpc85xx_pcie_check;
|
|
|
|
else
|
|
|
|
pci->edac_check = mpc85xx_pci_check;
|
|
|
|
}
|
2008-02-07 08:14:55 +00:00
|
|
|
|
|
|
|
pdata->edac_idx = edac_pci_idx++;
|
|
|
|
|
2015-12-10 19:07:12 +00:00
|
|
|
res = of_address_to_resource(of_node, 0, &r);
|
2008-07-25 08:49:14 +00:00
|
|
|
if (res) {
|
2016-08-09 21:55:39 +00:00
|
|
|
pr_err("%s: Unable to get resource for PCI err regs\n", __func__);
|
2008-02-07 08:14:55 +00:00
|
|
|
goto err;
|
|
|
|
}
|
|
|
|
|
2008-07-25 08:49:14 +00:00
|
|
|
/* we only need the error registers */
|
|
|
|
r.start += 0xe00;
|
|
|
|
|
2010-03-10 23:23:13 +00:00
|
|
|
if (!devm_request_mem_region(&op->dev, r.start, resource_size(&r),
|
|
|
|
pdata->name)) {
|
2016-08-09 21:55:39 +00:00
|
|
|
pr_err("%s: Error while requesting mem region\n", __func__);
|
2008-02-07 08:14:55 +00:00
|
|
|
res = -EBUSY;
|
|
|
|
goto err;
|
|
|
|
}
|
|
|
|
|
2010-03-10 23:23:13 +00:00
|
|
|
pdata->pci_vbase = devm_ioremap(&op->dev, r.start, resource_size(&r));
|
2008-02-07 08:14:55 +00:00
|
|
|
if (!pdata->pci_vbase) {
|
2016-08-09 21:55:39 +00:00
|
|
|
pr_err("%s: Unable to setup PCI err regs\n", __func__);
|
2008-02-07 08:14:55 +00:00
|
|
|
res = -ENOMEM;
|
|
|
|
goto err;
|
|
|
|
}
|
|
|
|
|
2013-11-25 10:28:41 +00:00
|
|
|
if (pdata->is_pcie) {
|
|
|
|
orig_pci_err_cap_dr =
|
|
|
|
in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ADDR);
|
|
|
|
out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ADDR, ~0);
|
|
|
|
orig_pci_err_en =
|
|
|
|
in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN);
|
|
|
|
out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN, 0);
|
|
|
|
} else {
|
|
|
|
orig_pci_err_cap_dr =
|
|
|
|
in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_CAP_DR);
|
|
|
|
|
|
|
|
/* PCI master abort is expected during config cycles */
|
|
|
|
out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_CAP_DR, 0x40);
|
|
|
|
|
|
|
|
orig_pci_err_en =
|
|
|
|
in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN);
|
|
|
|
|
|
|
|
/* disable master abort reporting */
|
|
|
|
out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN, ~0x40);
|
|
|
|
}
|
2008-02-07 08:14:55 +00:00
|
|
|
|
|
|
|
/* clear error bits */
|
|
|
|
out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, ~0);
|
|
|
|
|
2016-08-15 19:08:49 +00:00
|
|
|
/* reset error capture */
|
|
|
|
out_be32(pdata->pci_vbase + MPC85XX_PCI_GAS_TIMR, 0x1);
|
|
|
|
|
2008-02-07 08:14:55 +00:00
|
|
|
if (edac_pci_add_device(pci, pdata->edac_idx) > 0) {
|
2012-04-29 20:08:39 +00:00
|
|
|
edac_dbg(3, "failed edac_pci_add_device()\n");
|
2008-02-07 08:14:55 +00:00
|
|
|
goto err;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (edac_op_state == EDAC_OPSTATE_INT) {
|
2015-12-10 19:07:12 +00:00
|
|
|
pdata->irq = irq_of_parse_and_map(of_node, 0);
|
2008-07-25 08:49:14 +00:00
|
|
|
res = devm_request_irq(&op->dev, pdata->irq,
|
2013-11-25 10:28:41 +00:00
|
|
|
mpc85xx_pci_isr,
|
2014-01-21 08:42:27 +00:00
|
|
|
IRQF_SHARED,
|
2008-02-07 08:14:55 +00:00
|
|
|
"[EDAC] PCI err", pci);
|
|
|
|
if (res < 0) {
|
2016-08-09 21:55:39 +00:00
|
|
|
pr_err("%s: Unable to request irq %d for MPC85xx PCI err\n",
|
|
|
|
__func__, pdata->irq);
|
2008-07-25 08:49:14 +00:00
|
|
|
irq_dispose_mapping(pdata->irq);
|
2008-02-07 08:14:55 +00:00
|
|
|
res = -ENODEV;
|
|
|
|
goto err2;
|
|
|
|
}
|
|
|
|
|
2016-08-09 21:55:39 +00:00
|
|
|
pr_info(EDAC_MOD_STR " acquired irq %d for PCI Err\n",
|
2008-02-07 08:14:55 +00:00
|
|
|
pdata->irq);
|
|
|
|
}
|
|
|
|
|
2013-11-25 10:28:41 +00:00
|
|
|
if (pdata->is_pcie) {
|
|
|
|
/*
|
|
|
|
* Enable all PCIe error interrupt & error detect except invalid
|
|
|
|
* PEX_CONFIG_ADDR/PEX_CONFIG_DATA access interrupt generation
|
|
|
|
* enable bit and invalid PEX_CONFIG_ADDR/PEX_CONFIG_DATA access
|
|
|
|
* detection enable bit. Because PCIe bus code to initialize and
|
|
|
|
* configure these PCIe devices on booting will use some invalid
|
|
|
|
* PEX_CONFIG_ADDR/PEX_CONFIG_DATA, edac driver prints the much
|
|
|
|
* notice information. So disable this detect to fix ugly print.
|
|
|
|
*/
|
|
|
|
out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN, ~0
|
|
|
|
& ~PEX_ERR_ICCAIE_EN_BIT);
|
|
|
|
out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ADDR, 0
|
|
|
|
| PEX_ERR_ICCAD_DISR_BIT);
|
|
|
|
}
|
|
|
|
|
2008-07-25 08:49:14 +00:00
|
|
|
devres_remove_group(&op->dev, mpc85xx_pci_err_probe);
|
2012-04-29 20:08:39 +00:00
|
|
|
edac_dbg(3, "success\n");
|
2016-08-09 21:55:39 +00:00
|
|
|
pr_info(EDAC_MOD_STR " PCI err registered\n");
|
2008-02-07 08:14:55 +00:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
err2:
|
2008-07-25 08:49:14 +00:00
|
|
|
edac_pci_del_device(&op->dev);
|
2008-02-07 08:14:55 +00:00
|
|
|
err:
|
|
|
|
edac_pci_free_ctl_info(pci);
|
2008-07-25 08:49:14 +00:00
|
|
|
devres_release_group(&op->dev, mpc85xx_pci_err_probe);
|
2008-02-07 08:14:55 +00:00
|
|
|
return res;
|
|
|
|
}
|
|
|
|
|
2016-11-17 02:56:20 +00:00
|
|
|
static int mpc85xx_pci_err_remove(struct platform_device *op)
|
|
|
|
{
|
|
|
|
struct edac_pci_ctl_info *pci = dev_get_drvdata(&op->dev);
|
|
|
|
struct mpc85xx_pci_pdata *pdata = pci->pvt_info;
|
|
|
|
|
|
|
|
edac_dbg(0, "\n");
|
|
|
|
|
|
|
|
out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ADDR, orig_pci_err_cap_dr);
|
|
|
|
out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN, orig_pci_err_en);
|
|
|
|
|
|
|
|
edac_pci_del_device(&op->dev);
|
|
|
|
edac_pci_free_ctl_info(pci);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2015-12-10 19:07:12 +00:00
|
|
|
static const struct platform_device_id mpc85xx_pci_err_match[] = {
|
|
|
|
{
|
|
|
|
.name = "mpc85xx-pci-edac"
|
|
|
|
},
|
|
|
|
{}
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct platform_driver mpc85xx_pci_err_driver = {
|
|
|
|
.probe = mpc85xx_pci_err_probe,
|
2016-11-17 02:56:20 +00:00
|
|
|
.remove = mpc85xx_pci_err_remove,
|
2015-12-10 19:07:12 +00:00
|
|
|
.id_table = mpc85xx_pci_err_match,
|
|
|
|
.driver = {
|
|
|
|
.name = "mpc85xx_pci_err",
|
|
|
|
.suppress_bind_attrs = true,
|
|
|
|
},
|
|
|
|
};
|
2008-02-07 08:14:55 +00:00
|
|
|
#endif /* CONFIG_PCI */
|
|
|
|
|
|
|
|
/**************************** L2 Err device ***************************/
|
|
|
|
|
|
|
|
/************************ L2 SYSFS parts ***********************************/
|
|
|
|
|
|
|
|
static ssize_t mpc85xx_l2_inject_data_hi_show(struct edac_device_ctl_info
|
|
|
|
*edac_dev, char *data)
|
|
|
|
{
|
|
|
|
struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
|
|
|
|
return sprintf(data, "0x%08x",
|
|
|
|
in_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJHI));
|
|
|
|
}
|
|
|
|
|
|
|
|
static ssize_t mpc85xx_l2_inject_data_lo_show(struct edac_device_ctl_info
|
|
|
|
*edac_dev, char *data)
|
|
|
|
{
|
|
|
|
struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
|
|
|
|
return sprintf(data, "0x%08x",
|
|
|
|
in_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJLO));
|
|
|
|
}
|
|
|
|
|
|
|
|
static ssize_t mpc85xx_l2_inject_ctrl_show(struct edac_device_ctl_info
|
|
|
|
*edac_dev, char *data)
|
|
|
|
{
|
|
|
|
struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
|
|
|
|
return sprintf(data, "0x%08x",
|
|
|
|
in_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJCTL));
|
|
|
|
}
|
|
|
|
|
|
|
|
static ssize_t mpc85xx_l2_inject_data_hi_store(struct edac_device_ctl_info
|
|
|
|
*edac_dev, const char *data,
|
|
|
|
size_t count)
|
|
|
|
{
|
|
|
|
struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
|
|
|
|
if (isdigit(*data)) {
|
|
|
|
out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJHI,
|
|
|
|
simple_strtoul(data, NULL, 0));
|
|
|
|
return count;
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static ssize_t mpc85xx_l2_inject_data_lo_store(struct edac_device_ctl_info
|
|
|
|
*edac_dev, const char *data,
|
|
|
|
size_t count)
|
|
|
|
{
|
|
|
|
struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
|
|
|
|
if (isdigit(*data)) {
|
|
|
|
out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJLO,
|
|
|
|
simple_strtoul(data, NULL, 0));
|
|
|
|
return count;
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static ssize_t mpc85xx_l2_inject_ctrl_store(struct edac_device_ctl_info
|
|
|
|
*edac_dev, const char *data,
|
|
|
|
size_t count)
|
|
|
|
{
|
|
|
|
struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
|
|
|
|
if (isdigit(*data)) {
|
|
|
|
out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJCTL,
|
|
|
|
simple_strtoul(data, NULL, 0));
|
|
|
|
return count;
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct edac_dev_sysfs_attribute mpc85xx_l2_sysfs_attributes[] = {
|
|
|
|
{
|
|
|
|
.attr = {
|
|
|
|
.name = "inject_data_hi",
|
|
|
|
.mode = (S_IRUGO | S_IWUSR)
|
|
|
|
},
|
|
|
|
.show = mpc85xx_l2_inject_data_hi_show,
|
|
|
|
.store = mpc85xx_l2_inject_data_hi_store},
|
|
|
|
{
|
|
|
|
.attr = {
|
|
|
|
.name = "inject_data_lo",
|
|
|
|
.mode = (S_IRUGO | S_IWUSR)
|
|
|
|
},
|
|
|
|
.show = mpc85xx_l2_inject_data_lo_show,
|
|
|
|
.store = mpc85xx_l2_inject_data_lo_store},
|
|
|
|
{
|
|
|
|
.attr = {
|
|
|
|
.name = "inject_ctrl",
|
|
|
|
.mode = (S_IRUGO | S_IWUSR)
|
|
|
|
},
|
|
|
|
.show = mpc85xx_l2_inject_ctrl_show,
|
|
|
|
.store = mpc85xx_l2_inject_ctrl_store},
|
|
|
|
|
|
|
|
/* End of list */
|
|
|
|
{
|
|
|
|
.attr = {.name = NULL}
|
|
|
|
}
|
|
|
|
};
|
|
|
|
|
|
|
|
static void mpc85xx_set_l2_sysfs_attributes(struct edac_device_ctl_info
|
|
|
|
*edac_dev)
|
|
|
|
{
|
|
|
|
edac_dev->sysfs_attributes = mpc85xx_l2_sysfs_attributes;
|
|
|
|
}
|
|
|
|
|
|
|
|
/***************************** L2 ops ***********************************/
|
|
|
|
|
|
|
|
static void mpc85xx_l2_check(struct edac_device_ctl_info *edac_dev)
|
|
|
|
{
|
|
|
|
struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
|
|
|
|
u32 err_detect;
|
|
|
|
|
|
|
|
err_detect = in_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET);
|
|
|
|
|
|
|
|
if (!(err_detect & L2_EDE_MASK))
|
|
|
|
return;
|
|
|
|
|
2016-08-09 21:55:39 +00:00
|
|
|
pr_err("ECC Error in CPU L2 cache\n");
|
|
|
|
pr_err("L2 Error Detect Register: 0x%08x\n", err_detect);
|
|
|
|
pr_err("L2 Error Capture Data High Register: 0x%08x\n",
|
2008-02-07 08:14:55 +00:00
|
|
|
in_be32(pdata->l2_vbase + MPC85XX_L2_CAPTDATAHI));
|
2016-08-09 21:55:39 +00:00
|
|
|
pr_err("L2 Error Capture Data Lo Register: 0x%08x\n",
|
2008-02-07 08:14:55 +00:00
|
|
|
in_be32(pdata->l2_vbase + MPC85XX_L2_CAPTDATALO));
|
2016-08-09 21:55:39 +00:00
|
|
|
pr_err("L2 Error Syndrome Register: 0x%08x\n",
|
2008-02-07 08:14:55 +00:00
|
|
|
in_be32(pdata->l2_vbase + MPC85XX_L2_CAPTECC));
|
2016-08-09 21:55:39 +00:00
|
|
|
pr_err("L2 Error Attributes Capture Register: 0x%08x\n",
|
2008-02-07 08:14:55 +00:00
|
|
|
in_be32(pdata->l2_vbase + MPC85XX_L2_ERRATTR));
|
2016-08-09 21:55:39 +00:00
|
|
|
pr_err("L2 Error Address Capture Register: 0x%08x\n",
|
2008-02-07 08:14:55 +00:00
|
|
|
in_be32(pdata->l2_vbase + MPC85XX_L2_ERRADDR));
|
|
|
|
|
|
|
|
/* clear error detect register */
|
|
|
|
out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET, err_detect);
|
|
|
|
|
|
|
|
if (err_detect & L2_EDE_CE_MASK)
|
|
|
|
edac_device_handle_ce(edac_dev, 0, 0, edac_dev->ctl_name);
|
|
|
|
|
|
|
|
if (err_detect & L2_EDE_UE_MASK)
|
|
|
|
edac_device_handle_ue(edac_dev, 0, 0, edac_dev->ctl_name);
|
|
|
|
}
|
|
|
|
|
|
|
|
static irqreturn_t mpc85xx_l2_isr(int irq, void *dev_id)
|
|
|
|
{
|
|
|
|
struct edac_device_ctl_info *edac_dev = dev_id;
|
|
|
|
struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
|
|
|
|
u32 err_detect;
|
|
|
|
|
|
|
|
err_detect = in_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET);
|
|
|
|
|
|
|
|
if (!(err_detect & L2_EDE_MASK))
|
|
|
|
return IRQ_NONE;
|
|
|
|
|
|
|
|
mpc85xx_l2_check(edac_dev);
|
|
|
|
|
|
|
|
return IRQ_HANDLED;
|
|
|
|
}
|
|
|
|
|
2012-12-21 21:23:51 +00:00
|
|
|
static int mpc85xx_l2_err_probe(struct platform_device *op)
|
2008-02-07 08:14:55 +00:00
|
|
|
{
|
|
|
|
struct edac_device_ctl_info *edac_dev;
|
|
|
|
struct mpc85xx_l2_pdata *pdata;
|
|
|
|
struct resource r;
|
|
|
|
int res;
|
|
|
|
|
|
|
|
if (!devres_open_group(&op->dev, mpc85xx_l2_err_probe, GFP_KERNEL))
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
edac_dev = edac_device_alloc_ctl_info(sizeof(*pdata),
|
|
|
|
"cpu", 1, "L", 1, 2, NULL, 0,
|
|
|
|
edac_dev_idx);
|
|
|
|
if (!edac_dev) {
|
|
|
|
devres_release_group(&op->dev, mpc85xx_l2_err_probe);
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
|
|
|
|
pdata = edac_dev->pvt_info;
|
|
|
|
pdata->name = "mpc85xx_l2_err";
|
|
|
|
edac_dev->dev = &op->dev;
|
|
|
|
dev_set_drvdata(edac_dev->dev, edac_dev);
|
|
|
|
edac_dev->ctl_name = pdata->name;
|
|
|
|
edac_dev->dev_name = pdata->name;
|
|
|
|
|
2010-06-03 01:17:42 +00:00
|
|
|
res = of_address_to_resource(op->dev.of_node, 0, &r);
|
2008-02-07 08:14:55 +00:00
|
|
|
if (res) {
|
2016-08-09 21:55:39 +00:00
|
|
|
pr_err("%s: Unable to get resource for L2 err regs\n", __func__);
|
2008-02-07 08:14:55 +00:00
|
|
|
goto err;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* we only need the error registers */
|
|
|
|
r.start += 0xe00;
|
|
|
|
|
2011-06-09 16:13:32 +00:00
|
|
|
if (!devm_request_mem_region(&op->dev, r.start, resource_size(&r),
|
|
|
|
pdata->name)) {
|
2016-08-09 21:55:39 +00:00
|
|
|
pr_err("%s: Error while requesting mem region\n", __func__);
|
2008-02-07 08:14:55 +00:00
|
|
|
res = -EBUSY;
|
|
|
|
goto err;
|
|
|
|
}
|
|
|
|
|
2011-06-09 16:13:32 +00:00
|
|
|
pdata->l2_vbase = devm_ioremap(&op->dev, r.start, resource_size(&r));
|
2008-02-07 08:14:55 +00:00
|
|
|
if (!pdata->l2_vbase) {
|
2016-08-09 21:55:39 +00:00
|
|
|
pr_err("%s: Unable to setup L2 err regs\n", __func__);
|
2008-02-07 08:14:55 +00:00
|
|
|
res = -ENOMEM;
|
|
|
|
goto err;
|
|
|
|
}
|
|
|
|
|
|
|
|
out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET, ~0);
|
|
|
|
|
|
|
|
orig_l2_err_disable = in_be32(pdata->l2_vbase + MPC85XX_L2_ERRDIS);
|
|
|
|
|
|
|
|
/* clear the err_dis */
|
|
|
|
out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDIS, 0);
|
|
|
|
|
|
|
|
edac_dev->mod_name = EDAC_MOD_STR;
|
|
|
|
|
|
|
|
if (edac_op_state == EDAC_OPSTATE_POLL)
|
|
|
|
edac_dev->edac_check = mpc85xx_l2_check;
|
|
|
|
|
|
|
|
mpc85xx_set_l2_sysfs_attributes(edac_dev);
|
|
|
|
|
|
|
|
pdata->edac_idx = edac_dev_idx++;
|
|
|
|
|
|
|
|
if (edac_device_add_device(edac_dev) > 0) {
|
2012-04-29 20:08:39 +00:00
|
|
|
edac_dbg(3, "failed edac_device_add_device()\n");
|
2008-02-07 08:14:55 +00:00
|
|
|
goto err;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (edac_op_state == EDAC_OPSTATE_INT) {
|
2010-06-03 01:17:42 +00:00
|
|
|
pdata->irq = irq_of_parse_and_map(op->dev.of_node, 0);
|
2008-02-07 08:14:55 +00:00
|
|
|
res = devm_request_irq(&op->dev, pdata->irq,
|
2014-09-30 10:55:41 +00:00
|
|
|
mpc85xx_l2_isr, IRQF_SHARED,
|
2008-02-07 08:14:55 +00:00
|
|
|
"[EDAC] L2 err", edac_dev);
|
|
|
|
if (res < 0) {
|
2016-08-09 21:55:39 +00:00
|
|
|
pr_err("%s: Unable to request irq %d for MPC85xx L2 err\n",
|
|
|
|
__func__, pdata->irq);
|
2008-02-07 08:14:55 +00:00
|
|
|
irq_dispose_mapping(pdata->irq);
|
|
|
|
res = -ENODEV;
|
|
|
|
goto err2;
|
|
|
|
}
|
|
|
|
|
2016-08-09 21:55:39 +00:00
|
|
|
pr_info(EDAC_MOD_STR " acquired irq %d for L2 Err\n", pdata->irq);
|
2008-02-07 08:14:55 +00:00
|
|
|
|
|
|
|
edac_dev->op_state = OP_RUNNING_INTERRUPT;
|
|
|
|
|
|
|
|
out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINTEN, L2_EIE_MASK);
|
|
|
|
}
|
|
|
|
|
|
|
|
devres_remove_group(&op->dev, mpc85xx_l2_err_probe);
|
|
|
|
|
2012-04-29 20:08:39 +00:00
|
|
|
edac_dbg(3, "success\n");
|
2016-08-09 21:55:39 +00:00
|
|
|
pr_info(EDAC_MOD_STR " L2 err registered\n");
|
2008-02-07 08:14:55 +00:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
err2:
|
|
|
|
edac_device_del_device(&op->dev);
|
|
|
|
err:
|
|
|
|
devres_release_group(&op->dev, mpc85xx_l2_err_probe);
|
|
|
|
edac_device_free_ctl_info(edac_dev);
|
|
|
|
return res;
|
|
|
|
}
|
|
|
|
|
2010-08-06 15:25:50 +00:00
|
|
|
static int mpc85xx_l2_err_remove(struct platform_device *op)
|
2008-02-07 08:14:55 +00:00
|
|
|
{
|
|
|
|
struct edac_device_ctl_info *edac_dev = dev_get_drvdata(&op->dev);
|
|
|
|
struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
|
|
|
|
|
2012-04-29 20:08:39 +00:00
|
|
|
edac_dbg(0, "\n");
|
2008-02-07 08:14:55 +00:00
|
|
|
|
|
|
|
if (edac_op_state == EDAC_OPSTATE_INT) {
|
|
|
|
out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINTEN, 0);
|
|
|
|
irq_dispose_mapping(pdata->irq);
|
|
|
|
}
|
|
|
|
|
|
|
|
out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDIS, orig_l2_err_disable);
|
|
|
|
edac_device_del_device(&op->dev);
|
|
|
|
edac_device_free_ctl_info(edac_dev);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2015-03-16 19:54:41 +00:00
|
|
|
static const struct of_device_id mpc85xx_l2_err_of_match[] = {
|
2009-01-06 22:42:59 +00:00
|
|
|
/* deprecate the fsl,85.. forms in the future, 2.6.30? */
|
|
|
|
{ .compatible = "fsl,8540-l2-cache-controller", },
|
|
|
|
{ .compatible = "fsl,8541-l2-cache-controller", },
|
|
|
|
{ .compatible = "fsl,8544-l2-cache-controller", },
|
|
|
|
{ .compatible = "fsl,8548-l2-cache-controller", },
|
|
|
|
{ .compatible = "fsl,8555-l2-cache-controller", },
|
|
|
|
{ .compatible = "fsl,8568-l2-cache-controller", },
|
|
|
|
{ .compatible = "fsl,mpc8536-l2-cache-controller", },
|
|
|
|
{ .compatible = "fsl,mpc8540-l2-cache-controller", },
|
|
|
|
{ .compatible = "fsl,mpc8541-l2-cache-controller", },
|
|
|
|
{ .compatible = "fsl,mpc8544-l2-cache-controller", },
|
|
|
|
{ .compatible = "fsl,mpc8548-l2-cache-controller", },
|
|
|
|
{ .compatible = "fsl,mpc8555-l2-cache-controller", },
|
|
|
|
{ .compatible = "fsl,mpc8560-l2-cache-controller", },
|
|
|
|
{ .compatible = "fsl,mpc8568-l2-cache-controller", },
|
2010-08-11 01:03:21 +00:00
|
|
|
{ .compatible = "fsl,mpc8569-l2-cache-controller", },
|
2009-01-06 22:42:59 +00:00
|
|
|
{ .compatible = "fsl,mpc8572-l2-cache-controller", },
|
2010-08-11 01:03:21 +00:00
|
|
|
{ .compatible = "fsl,p1020-l2-cache-controller", },
|
|
|
|
{ .compatible = "fsl,p1021-l2-cache-controller", },
|
2009-09-23 22:57:24 +00:00
|
|
|
{ .compatible = "fsl,p2020-l2-cache-controller", },
|
2008-02-07 08:14:55 +00:00
|
|
|
{},
|
|
|
|
};
|
2010-07-27 20:18:05 +00:00
|
|
|
MODULE_DEVICE_TABLE(of, mpc85xx_l2_err_of_match);
|
2008-02-07 08:14:55 +00:00
|
|
|
|
2011-02-23 02:59:54 +00:00
|
|
|
static struct platform_driver mpc85xx_l2_err_driver = {
|
2008-02-07 08:14:55 +00:00
|
|
|
.probe = mpc85xx_l2_err_probe,
|
|
|
|
.remove = mpc85xx_l2_err_remove,
|
|
|
|
.driver = {
|
2010-04-13 23:13:02 +00:00
|
|
|
.name = "mpc85xx_l2_err",
|
|
|
|
.of_match_table = mpc85xx_l2_err_of_match,
|
|
|
|
},
|
2008-02-07 08:14:55 +00:00
|
|
|
};
|
|
|
|
|
2015-03-16 19:54:41 +00:00
|
|
|
static const struct of_device_id mpc85xx_mc_err_of_match[] = {
|
2009-01-06 22:42:59 +00:00
|
|
|
/* deprecate the fsl,85.. forms in the future, 2.6.30? */
|
|
|
|
{ .compatible = "fsl,8540-memory-controller", },
|
|
|
|
{ .compatible = "fsl,8541-memory-controller", },
|
|
|
|
{ .compatible = "fsl,8544-memory-controller", },
|
|
|
|
{ .compatible = "fsl,8548-memory-controller", },
|
|
|
|
{ .compatible = "fsl,8555-memory-controller", },
|
|
|
|
{ .compatible = "fsl,8568-memory-controller", },
|
|
|
|
{ .compatible = "fsl,mpc8536-memory-controller", },
|
|
|
|
{ .compatible = "fsl,mpc8540-memory-controller", },
|
|
|
|
{ .compatible = "fsl,mpc8541-memory-controller", },
|
|
|
|
{ .compatible = "fsl,mpc8544-memory-controller", },
|
|
|
|
{ .compatible = "fsl,mpc8548-memory-controller", },
|
|
|
|
{ .compatible = "fsl,mpc8555-memory-controller", },
|
|
|
|
{ .compatible = "fsl,mpc8560-memory-controller", },
|
|
|
|
{ .compatible = "fsl,mpc8568-memory-controller", },
|
2010-07-20 20:24:28 +00:00
|
|
|
{ .compatible = "fsl,mpc8569-memory-controller", },
|
2009-01-06 22:42:59 +00:00
|
|
|
{ .compatible = "fsl,mpc8572-memory-controller", },
|
2009-09-23 22:57:25 +00:00
|
|
|
{ .compatible = "fsl,mpc8349-memory-controller", },
|
2010-08-11 01:03:21 +00:00
|
|
|
{ .compatible = "fsl,p1020-memory-controller", },
|
|
|
|
{ .compatible = "fsl,p1021-memory-controller", },
|
2009-09-23 22:57:24 +00:00
|
|
|
{ .compatible = "fsl,p2020-memory-controller", },
|
2011-11-15 22:52:22 +00:00
|
|
|
{ .compatible = "fsl,qoriq-memory-controller", },
|
2008-02-07 08:14:55 +00:00
|
|
|
{},
|
|
|
|
};
|
2010-07-27 20:18:05 +00:00
|
|
|
MODULE_DEVICE_TABLE(of, mpc85xx_mc_err_of_match);
|
2008-02-07 08:14:55 +00:00
|
|
|
|
2011-02-23 02:59:54 +00:00
|
|
|
static struct platform_driver mpc85xx_mc_err_driver = {
|
2016-08-09 21:55:41 +00:00
|
|
|
.probe = fsl_mc_err_probe,
|
|
|
|
.remove = fsl_mc_err_remove,
|
2008-02-07 08:14:55 +00:00
|
|
|
.driver = {
|
2010-04-13 23:13:02 +00:00
|
|
|
.name = "mpc85xx_mc_err",
|
|
|
|
.of_match_table = mpc85xx_mc_err_of_match,
|
|
|
|
},
|
2008-02-07 08:14:55 +00:00
|
|
|
};
|
|
|
|
|
2015-12-03 09:57:12 +00:00
|
|
|
static struct platform_driver * const drivers[] = {
|
|
|
|
&mpc85xx_mc_err_driver,
|
|
|
|
&mpc85xx_l2_err_driver,
|
2015-12-10 19:07:12 +00:00
|
|
|
#ifdef CONFIG_PCI
|
|
|
|
&mpc85xx_pci_err_driver,
|
|
|
|
#endif
|
2015-12-03 09:57:12 +00:00
|
|
|
};
|
|
|
|
|
2008-02-07 08:14:55 +00:00
|
|
|
static int __init mpc85xx_mc_init(void)
|
|
|
|
{
|
|
|
|
int res = 0;
|
2016-02-02 15:39:33 +00:00
|
|
|
u32 __maybe_unused pvr = 0;
|
2008-02-07 08:14:55 +00:00
|
|
|
|
2016-08-09 21:55:39 +00:00
|
|
|
pr_info("Freescale(R) MPC85xx EDAC driver, (C) 2006 Montavista Software\n");
|
2008-02-07 08:14:55 +00:00
|
|
|
|
|
|
|
/* make sure error reporting method is sane */
|
|
|
|
switch (edac_op_state) {
|
|
|
|
case EDAC_OPSTATE_POLL:
|
|
|
|
case EDAC_OPSTATE_INT:
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
edac_op_state = EDAC_OPSTATE_INT;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2015-12-03 09:57:12 +00:00
|
|
|
res = platform_register_drivers(drivers, ARRAY_SIZE(drivers));
|
2008-02-07 08:14:55 +00:00
|
|
|
if (res)
|
2016-08-09 21:55:39 +00:00
|
|
|
pr_warn(EDAC_MOD_STR "drivers fail to register\n");
|
2008-02-07 08:14:55 +00:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
module_init(mpc85xx_mc_init);
|
|
|
|
|
|
|
|
static void __exit mpc85xx_mc_exit(void)
|
|
|
|
{
|
2015-12-03 09:57:12 +00:00
|
|
|
platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
|
2008-02-07 08:14:55 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
module_exit(mpc85xx_mc_exit);
|
|
|
|
|
|
|
|
MODULE_LICENSE("GPL");
|
|
|
|
MODULE_AUTHOR("Montavista Software, Inc.");
|
|
|
|
module_param(edac_op_state, int, 0444);
|
|
|
|
MODULE_PARM_DESC(edac_op_state,
|
|
|
|
"EDAC Error Reporting state: 0=Poll, 2=Interrupt");
|