2008-10-23 05:26:29 +00:00
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#ifndef _ASM_X86_APIC_H
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#define _ASM_X86_APIC_H
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2008-01-30 12:30:15 +00:00
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#include <linux/pm.h>
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#include <linux/delay.h>
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x86: APIC: remove apic_write_around(); use alternatives
Use alternatives to select the workaround for the 11AP Pentium erratum
for the affected steppings on the fly rather than build time. Remove the
X86_GOOD_APIC configuration option and replace all the calls to
apic_write_around() with plain apic_write(), protecting accesses to the
ESR as appropriate due to the 3AP Pentium erratum. Remove
apic_read_around() and all its invocations altogether as not needed.
Remove apic_write_atomic() and all its implementing backends. The use of
ASM_OUTPUT2() is not strictly needed for input constraints, but I have
used it for readability's sake.
I had the feeling no one else was brave enough to do it, so I went ahead
and here it is. Verified by checking the generated assembly and tested
with both a 32-bit and a 64-bit configuration, also with the 11AP
"feature" forced on and verified with gdb on /proc/kcore to work as
expected (as an 11AP machines are quite hard to get hands on these days).
Some script complained about the use of "volatile", but apic_write() needs
it for the same reason and is effectively a replacement for writel(), so I
have disregarded it.
I am not sure what the policy wrt defconfig files is, they are generated
and there is risk of a conflict resulting from an unrelated change, so I
have left changes to them out. The option will get removed from them at
the next run.
Some testing with machines other than mine will be needed to avoid some
stupid mistake, but despite its volume, the change is not really that
intrusive, so I am fairly confident that because it works for me, it will
everywhere.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-07-16 18:15:30 +00:00
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#include <asm/alternative.h>
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2008-01-30 12:30:15 +00:00
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#include <asm/fixmap.h>
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#include <asm/apicdef.h>
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#include <asm/processor.h>
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#include <asm/system.h>
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2008-07-10 18:16:52 +00:00
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#include <asm/cpufeature.h>
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#include <asm/msr.h>
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2008-01-30 12:30:15 +00:00
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#define ARCH_APICTIMER_STOPS_ON_C3 1
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/*
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* Debugging macros
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*/
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#define APIC_QUIET 0
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#define APIC_VERBOSE 1
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#define APIC_DEBUG 2
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/*
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* Define the default level of output to be very little
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* This can be turned up by using apic=verbose for more
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* information and apic=debug for _lots_ of information.
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* apic_verbosity is defined in apic.c
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*/
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#define apic_printk(v, s, a...) do { \
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if ((v) <= apic_verbosity) \
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printk(s, ##a); \
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} while (0)
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extern void generic_apic_probe(void);
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#ifdef CONFIG_X86_LOCAL_APIC
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2008-07-14 17:44:51 +00:00
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extern unsigned int apic_verbosity;
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2008-01-30 12:30:15 +00:00
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extern int local_apic_timer_c2_ok;
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2008-06-20 23:11:20 +00:00
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extern int disable_apic;
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2009-01-28 16:16:25 +00:00
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#ifdef CONFIG_SMP
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extern void __inquire_remote_apic(int apicid);
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#else /* CONFIG_SMP */
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static inline void __inquire_remote_apic(int apicid)
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{
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}
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#endif /* CONFIG_SMP */
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static inline void default_inquire_remote_apic(int apicid)
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{
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if (apic_verbosity >= APIC_DEBUG)
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__inquire_remote_apic(apicid);
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}
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2008-01-30 12:30:15 +00:00
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/*
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* Basic functions accessing APICs.
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*/
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#ifdef CONFIG_PARAVIRT
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#include <asm/paravirt.h>
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2007-10-11 09:20:03 +00:00
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#else
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2008-01-30 12:30:15 +00:00
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#define setup_boot_clock setup_boot_APIC_clock
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#define setup_secondary_clock setup_secondary_APIC_clock
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2007-10-11 09:20:03 +00:00
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#endif
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2008-01-30 12:30:15 +00:00
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2008-03-20 07:41:16 +00:00
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extern int is_vsmp_box(void);
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2008-07-23 11:43:14 +00:00
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extern void xapic_wait_icr_idle(void);
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extern u32 safe_xapic_wait_icr_idle(void);
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extern void xapic_icr_write(u32, u32);
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extern int setup_profiling_timer(unsigned int);
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2008-03-20 07:41:16 +00:00
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2008-07-10 18:16:49 +00:00
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static inline void native_apic_mem_write(u32 reg, u32 v)
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2008-01-30 12:30:15 +00:00
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{
|
x86: APIC: remove apic_write_around(); use alternatives
Use alternatives to select the workaround for the 11AP Pentium erratum
for the affected steppings on the fly rather than build time. Remove the
X86_GOOD_APIC configuration option and replace all the calls to
apic_write_around() with plain apic_write(), protecting accesses to the
ESR as appropriate due to the 3AP Pentium erratum. Remove
apic_read_around() and all its invocations altogether as not needed.
Remove apic_write_atomic() and all its implementing backends. The use of
ASM_OUTPUT2() is not strictly needed for input constraints, but I have
used it for readability's sake.
I had the feeling no one else was brave enough to do it, so I went ahead
and here it is. Verified by checking the generated assembly and tested
with both a 32-bit and a 64-bit configuration, also with the 11AP
"feature" forced on and verified with gdb on /proc/kcore to work as
expected (as an 11AP machines are quite hard to get hands on these days).
Some script complained about the use of "volatile", but apic_write() needs
it for the same reason and is effectively a replacement for writel(), so I
have disregarded it.
I am not sure what the policy wrt defconfig files is, they are generated
and there is risk of a conflict resulting from an unrelated change, so I
have left changes to them out. The option will get removed from them at
the next run.
Some testing with machines other than mine will be needed to avoid some
stupid mistake, but despite its volume, the change is not really that
intrusive, so I am fairly confident that because it works for me, it will
everywhere.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-07-16 18:15:30 +00:00
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volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg);
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2008-01-30 12:30:15 +00:00
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|
x86: APIC: remove apic_write_around(); use alternatives
Use alternatives to select the workaround for the 11AP Pentium erratum
for the affected steppings on the fly rather than build time. Remove the
X86_GOOD_APIC configuration option and replace all the calls to
apic_write_around() with plain apic_write(), protecting accesses to the
ESR as appropriate due to the 3AP Pentium erratum. Remove
apic_read_around() and all its invocations altogether as not needed.
Remove apic_write_atomic() and all its implementing backends. The use of
ASM_OUTPUT2() is not strictly needed for input constraints, but I have
used it for readability's sake.
I had the feeling no one else was brave enough to do it, so I went ahead
and here it is. Verified by checking the generated assembly and tested
with both a 32-bit and a 64-bit configuration, also with the 11AP
"feature" forced on and verified with gdb on /proc/kcore to work as
expected (as an 11AP machines are quite hard to get hands on these days).
Some script complained about the use of "volatile", but apic_write() needs
it for the same reason and is effectively a replacement for writel(), so I
have disregarded it.
I am not sure what the policy wrt defconfig files is, they are generated
and there is risk of a conflict resulting from an unrelated change, so I
have left changes to them out. The option will get removed from them at
the next run.
Some testing with machines other than mine will be needed to avoid some
stupid mistake, but despite its volume, the change is not really that
intrusive, so I am fairly confident that because it works for me, it will
everywhere.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-07-16 18:15:30 +00:00
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alternative_io("movl %0, %1", "xchgl %0, %1", X86_FEATURE_11AP,
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ASM_OUTPUT2("=r" (v), "=m" (*addr)),
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ASM_OUTPUT2("0" (v), "m" (*addr)));
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2008-01-30 12:30:15 +00:00
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}
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2008-07-10 18:16:49 +00:00
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static inline u32 native_apic_mem_read(u32 reg)
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2008-01-30 12:30:15 +00:00
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{
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return *((volatile u32 *)(APIC_BASE + reg));
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}
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2008-07-10 18:16:52 +00:00
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static inline void native_apic_msr_write(u32 reg, u32 v)
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{
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if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR ||
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reg == APIC_LVR)
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return;
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wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0);
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}
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static inline u32 native_apic_msr_read(u32 reg)
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{
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u32 low, high;
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if (reg == APIC_DFR)
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return -1;
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rdmsr(APIC_BASE_MSR + (reg >> 4), low, high);
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return low;
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}
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2008-07-12 01:41:54 +00:00
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#ifndef CONFIG_X86_32
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2008-12-23 16:22:33 +00:00
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extern int x2apic;
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2008-07-10 18:16:58 +00:00
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extern void check_x2apic(void);
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extern void enable_x2apic(void);
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extern void enable_IR_x2apic(void);
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extern void x2apic_icr_write(u32 low, u32 id);
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2008-09-03 23:58:31 +00:00
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static inline int x2apic_enabled(void)
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{
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int msr, msr2;
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if (!cpu_has_x2apic)
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return 0;
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rdmsr(MSR_IA32_APICBASE, msr, msr2);
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if (msr & X2APIC_ENABLE)
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return 1;
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return 0;
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}
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#else
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#define x2apic_enabled() 0
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2008-07-12 01:41:54 +00:00
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#endif
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2008-07-10 18:16:49 +00:00
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struct apic_ops {
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u32 (*read)(u32 reg);
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void (*write)(u32 reg, u32 v);
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u64 (*icr_read)(void);
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void (*icr_write)(u32 low, u32 high);
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void (*wait_icr_idle)(void);
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u32 (*safe_wait_icr_idle)(void);
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};
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extern struct apic_ops *apic_ops;
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#define apic_read (apic_ops->read)
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#define apic_write (apic_ops->write)
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#define apic_icr_read (apic_ops->icr_read)
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#define apic_icr_write (apic_ops->icr_write)
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#define apic_wait_icr_idle (apic_ops->wait_icr_idle)
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#define safe_apic_wait_icr_idle (apic_ops->safe_wait_icr_idle)
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2008-01-30 12:30:15 +00:00
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extern int get_physical_broadcast(void);
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x64, x2apic/intr-remap: IO-APIC support for interrupt-remapping
IO-APIC support in the presence of interrupt-remapping infrastructure.
IO-APIC RTE will be programmed with interrupt-remapping table entry(IRTE)
index and the IRTE will contain information about the vector, cpu destination,
trigger mode etc, which traditionally was present in the IO-APIC RTE.
Introduce a new irq_chip for cleaner irq migration (in the process
context as opposed to the current irq migration in the context of an interrupt.
interrupt-remapping infrastructure will help us achieve this cleanly).
For edge triggered, irq migration is a simple atomic update(of vector
and cpu destination) of IRTE and flush the hardware cache.
For level triggered, we need to modify the io-apic RTE aswell with the update
vector information, along with modifying IRTE with vector and cpu destination.
So irq migration for level triggered is little bit more complex compared to
edge triggered migration. But the good news is, we use the same algorithm
for level triggered migration as we have today, only difference being,
we now initiate the irq migration from process context instead of the
interrupt context.
In future, when we do a directed EOI (combined with cpu EOI broadcast
suppression) to the IO-APIC, level triggered irq migration will also be
as simple as edge triggered migration and we can do the irq migration
with a simple atomic update to IO-APIC RTE.
TBD: some tests/changes needed in the presence of fixup_irqs() for
level triggered irq migration.
Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com>
Cc: akpm@linux-foundation.org
Cc: arjan@linux.intel.com
Cc: andi@firstfloor.org
Cc: ebiederm@xmission.com
Cc: jbarnes@virtuousgeek.org
Cc: steiner@sgi.com
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-07-10 18:16:56 +00:00
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#ifdef CONFIG_X86_64
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static inline void ack_x2APIC_irq(void)
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{
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/* Docs say use 0 for future compatibility */
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native_apic_msr_write(APIC_EOI, 0);
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}
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#endif
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2008-01-30 12:30:15 +00:00
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static inline void ack_APIC_irq(void)
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{
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/*
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2008-07-21 00:28:43 +00:00
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* ack_APIC_irq() actually gets compiled as a single instruction
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2008-01-30 12:30:15 +00:00
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* ... yummie.
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*/
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/* Docs say use 0 for future compatibility */
|
x86: APIC: remove apic_write_around(); use alternatives
Use alternatives to select the workaround for the 11AP Pentium erratum
for the affected steppings on the fly rather than build time. Remove the
X86_GOOD_APIC configuration option and replace all the calls to
apic_write_around() with plain apic_write(), protecting accesses to the
ESR as appropriate due to the 3AP Pentium erratum. Remove
apic_read_around() and all its invocations altogether as not needed.
Remove apic_write_atomic() and all its implementing backends. The use of
ASM_OUTPUT2() is not strictly needed for input constraints, but I have
used it for readability's sake.
I had the feeling no one else was brave enough to do it, so I went ahead
and here it is. Verified by checking the generated assembly and tested
with both a 32-bit and a 64-bit configuration, also with the 11AP
"feature" forced on and verified with gdb on /proc/kcore to work as
expected (as an 11AP machines are quite hard to get hands on these days).
Some script complained about the use of "volatile", but apic_write() needs
it for the same reason and is effectively a replacement for writel(), so I
have disregarded it.
I am not sure what the policy wrt defconfig files is, they are generated
and there is risk of a conflict resulting from an unrelated change, so I
have left changes to them out. The option will get removed from them at
the next run.
Some testing with machines other than mine will be needed to avoid some
stupid mistake, but despite its volume, the change is not really that
intrusive, so I am fairly confident that because it works for me, it will
everywhere.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-07-16 18:15:30 +00:00
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apic_write(APIC_EOI, 0);
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2008-01-30 12:30:15 +00:00
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}
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extern int lapic_get_maxlvt(void);
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extern void clear_local_APIC(void);
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extern void connect_bsp_APIC(void);
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extern void disconnect_bsp_APIC(int virt_wire_setup);
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extern void disable_local_APIC(void);
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extern void lapic_shutdown(void);
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extern int verify_local_APIC(void);
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extern void cache_APIC_registers(void);
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extern void sync_Arb_IDs(void);
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extern void init_bsp_APIC(void);
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extern void setup_local_APIC(void);
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2008-01-30 12:30:40 +00:00
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extern void end_local_APIC_setup(void);
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2008-01-30 12:30:15 +00:00
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extern void init_apic_mappings(void);
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extern void setup_boot_APIC_clock(void);
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extern void setup_secondary_APIC_clock(void);
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extern int APIC_init_uniprocessor(void);
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2008-01-30 12:31:24 +00:00
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extern void enable_NMI_through_LVT0(void);
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2008-01-30 12:30:15 +00:00
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/*
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* On 32bit this is mach-xxx local
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*/
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#ifdef CONFIG_X86_64
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2008-02-19 11:21:06 +00:00
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extern void early_init_lapic_mapping(void);
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2008-07-01 18:43:34 +00:00
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extern int apic_is_clustered_box(void);
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#else
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static inline int apic_is_clustered_box(void)
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{
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return 0;
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}
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2008-01-30 12:30:15 +00:00
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|
#endif
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2008-01-30 12:30:40 +00:00
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extern u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask);
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extern u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask);
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2008-01-30 12:30:15 +00:00
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#else /* !CONFIG_X86_LOCAL_APIC */
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static inline void lapic_shutdown(void) { }
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#define local_apic_timer_c2_ok 1
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2008-06-27 08:41:56 +00:00
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static inline void init_apic_mappings(void) { }
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2008-11-11 13:33:44 +00:00
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static inline void disable_local_APIC(void) { }
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2008-01-30 12:30:15 +00:00
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#endif /* !CONFIG_X86_LOCAL_APIC */
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2009-01-28 16:36:56 +00:00
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#ifdef CONFIG_X86_64
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#define SET_APIC_ID(x) (apic->set_apic_id(x))
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#else
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2009-01-28 18:32:55 +00:00
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#ifdef CONFIG_X86_LOCAL_APIC
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2009-01-28 16:55:37 +00:00
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static inline unsigned default_get_apic_id(unsigned long x)
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2009-01-28 16:36:56 +00:00
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{
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unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR));
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if (APIC_XAPIC(ver))
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return (x >> 24) & 0xFF;
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else
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return (x >> 24) & 0x0F;
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}
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2009-01-28 18:32:55 +00:00
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#endif
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2009-01-28 16:36:56 +00:00
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#endif
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2008-10-23 05:26:29 +00:00
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#endif /* _ASM_X86_APIC_H */
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