2019-06-04 08:11:33 +00:00
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// SPDX-License-Identifier: GPL-2.0-only
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2009-06-14 12:52:37 +00:00
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/* linux/drivers/mmc/host/sdhci-s3c.c
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*
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* Copyright 2008 Openmoko Inc.
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* Copyright 2008 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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* http://armlinux.simtec.co.uk/
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*
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* SDHCI (HSMMC) support for Samsung SoC
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*/
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2015-02-04 09:16:59 +00:00
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#include <linux/spinlock.h>
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2009-06-14 12:52:37 +00:00
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#include <linux/delay.h>
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#include <linux/dma-mapping.h>
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#include <linux/platform_device.h>
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2013-03-04 17:28:21 +00:00
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#include <linux/platform_data/mmc-sdhci-s3c.h>
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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 08:04:11 +00:00
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#include <linux/slab.h>
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2009-06-14 12:52:37 +00:00
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#include <linux/clk.h>
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#include <linux/io.h>
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2010-08-11 01:01:58 +00:00
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#include <linux/gpio.h>
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2011-07-29 14:35:00 +00:00
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#include <linux/module.h>
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2012-03-03 00:46:41 +00:00
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#include <linux/of.h>
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#include <linux/of_gpio.h>
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#include <linux/pm.h>
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2012-04-01 03:31:55 +00:00
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#include <linux/pm_runtime.h>
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2009-06-14 12:52:37 +00:00
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#include <linux/mmc/host.h>
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#include "sdhci.h"
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#define MAX_BUS_CLK (4)
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2017-01-24 09:27:27 +00:00
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#define S3C_SDHCI_CONTROL2 (0x80)
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#define S3C_SDHCI_CONTROL3 (0x84)
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#define S3C64XX_SDHCI_CONTROL4 (0x8C)
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2017-01-24 09:27:28 +00:00
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#define S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR BIT(31)
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#define S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK BIT(30)
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#define S3C_SDHCI_CTRL2_CDINVRXD3 BIT(29)
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#define S3C_SDHCI_CTRL2_SLCARDOUT BIT(28)
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2017-01-24 09:27:27 +00:00
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#define S3C_SDHCI_CTRL2_FLTCLKSEL_MASK (0xf << 24)
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#define S3C_SDHCI_CTRL2_FLTCLKSEL_SHIFT (24)
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#define S3C_SDHCI_CTRL2_FLTCLKSEL(_x) ((_x) << 24)
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#define S3C_SDHCI_CTRL2_LVLDAT_MASK (0xff << 16)
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#define S3C_SDHCI_CTRL2_LVLDAT_SHIFT (16)
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#define S3C_SDHCI_CTRL2_LVLDAT(_x) ((_x) << 16)
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2017-01-24 09:27:28 +00:00
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#define S3C_SDHCI_CTRL2_ENFBCLKTX BIT(15)
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#define S3C_SDHCI_CTRL2_ENFBCLKRX BIT(14)
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#define S3C_SDHCI_CTRL2_SDCDSEL BIT(13)
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#define S3C_SDHCI_CTRL2_SDSIGPC BIT(12)
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#define S3C_SDHCI_CTRL2_ENBUSYCHKTXSTART BIT(11)
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2017-01-24 09:27:27 +00:00
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#define S3C_SDHCI_CTRL2_DFCNT_MASK (0x3 << 9)
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#define S3C_SDHCI_CTRL2_DFCNT_SHIFT (9)
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#define S3C_SDHCI_CTRL2_DFCNT_NONE (0x0 << 9)
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#define S3C_SDHCI_CTRL2_DFCNT_4SDCLK (0x1 << 9)
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#define S3C_SDHCI_CTRL2_DFCNT_16SDCLK (0x2 << 9)
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#define S3C_SDHCI_CTRL2_DFCNT_64SDCLK (0x3 << 9)
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2017-01-24 09:27:28 +00:00
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#define S3C_SDHCI_CTRL2_ENCLKOUTHOLD BIT(8)
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#define S3C_SDHCI_CTRL2_RWAITMODE BIT(7)
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#define S3C_SDHCI_CTRL2_DISBUFRD BIT(6)
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2017-01-24 09:27:27 +00:00
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#define S3C_SDHCI_CTRL2_SELBASECLK_MASK (0x3 << 4)
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#define S3C_SDHCI_CTRL2_SELBASECLK_SHIFT (4)
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2017-01-24 09:27:28 +00:00
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#define S3C_SDHCI_CTRL2_PWRSYNC BIT(3)
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#define S3C_SDHCI_CTRL2_ENCLKOUTMSKCON BIT(1)
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#define S3C_SDHCI_CTRL2_HWINITFIN BIT(0)
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2017-01-24 09:27:27 +00:00
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2017-01-24 09:27:28 +00:00
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#define S3C_SDHCI_CTRL3_FCSEL3 BIT(31)
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#define S3C_SDHCI_CTRL3_FCSEL2 BIT(23)
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#define S3C_SDHCI_CTRL3_FCSEL1 BIT(15)
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#define S3C_SDHCI_CTRL3_FCSEL0 BIT(7)
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2017-01-24 09:27:27 +00:00
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#define S3C_SDHCI_CTRL3_FIA3_MASK (0x7f << 24)
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#define S3C_SDHCI_CTRL3_FIA3_SHIFT (24)
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#define S3C_SDHCI_CTRL3_FIA3(_x) ((_x) << 24)
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#define S3C_SDHCI_CTRL3_FIA2_MASK (0x7f << 16)
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#define S3C_SDHCI_CTRL3_FIA2_SHIFT (16)
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#define S3C_SDHCI_CTRL3_FIA2(_x) ((_x) << 16)
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#define S3C_SDHCI_CTRL3_FIA1_MASK (0x7f << 8)
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#define S3C_SDHCI_CTRL3_FIA1_SHIFT (8)
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#define S3C_SDHCI_CTRL3_FIA1(_x) ((_x) << 8)
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#define S3C_SDHCI_CTRL3_FIA0_MASK (0x7f << 0)
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#define S3C_SDHCI_CTRL3_FIA0_SHIFT (0)
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#define S3C_SDHCI_CTRL3_FIA0(_x) ((_x) << 0)
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#define S3C64XX_SDHCI_CONTROL4_DRIVE_MASK (0x3 << 16)
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#define S3C64XX_SDHCI_CONTROL4_DRIVE_SHIFT (16)
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#define S3C64XX_SDHCI_CONTROL4_DRIVE_2mA (0x0 << 16)
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#define S3C64XX_SDHCI_CONTROL4_DRIVE_4mA (0x1 << 16)
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#define S3C64XX_SDHCI_CONTROL4_DRIVE_7mA (0x2 << 16)
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#define S3C64XX_SDHCI_CONTROL4_DRIVE_9mA (0x3 << 16)
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#define S3C64XX_SDHCI_CONTROL4_BUSY (1)
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2009-06-14 12:52:37 +00:00
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/**
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* struct sdhci_s3c - S3C SDHCI instance
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* @host: The SDHCI host created
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* @pdev: The platform device we where created from.
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* @ioarea: The resource created when we claimed the IO area.
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* @pdata: The platform data for this controller.
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* @cur_clk: The index of the current bus clock.
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2020-07-01 12:46:51 +00:00
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* @ext_cd_irq: External card detect interrupt.
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2009-06-14 12:52:37 +00:00
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* @clk_io: The clock for the internal bus interface.
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2020-07-01 12:46:51 +00:00
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* @clk_rates: Clock frequencies.
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2009-06-14 12:52:37 +00:00
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* @clk_bus: The clocks that are available for the SD/MMC bus clock.
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2020-07-01 12:46:51 +00:00
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* @no_divider: No or non-standard internal clock divider.
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2009-06-14 12:52:37 +00:00
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*/
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struct sdhci_s3c {
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struct sdhci_host *host;
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struct platform_device *pdev;
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struct resource *ioarea;
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struct s3c_sdhci_platdata *pdata;
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2014-01-11 21:39:05 +00:00
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int cur_clk;
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2010-08-11 01:01:58 +00:00
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int ext_cd_irq;
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2009-06-14 12:52:37 +00:00
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struct clk *clk_io;
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struct clk *clk_bus[MAX_BUS_CLK];
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2014-01-11 21:39:02 +00:00
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unsigned long clk_rates[MAX_BUS_CLK];
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2014-04-25 11:58:55 +00:00
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bool no_divider;
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2009-06-14 12:52:37 +00:00
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};
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2012-02-16 13:23:58 +00:00
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/**
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* struct sdhci_s3c_driver_data - S3C SDHCI platform specific driver data
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* @sdhci_quirks: sdhci host specific quirks.
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2020-07-01 12:46:51 +00:00
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* @no_divider: no or non-standard internal clock divider.
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2012-02-16 13:23:58 +00:00
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*
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* Specifies platform specific configuration of sdhci controller.
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* Note: A structure for driver specific platform data is used for future
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* expansion of its usage.
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*/
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struct sdhci_s3c_drv_data {
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unsigned int sdhci_quirks;
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2014-04-25 11:58:55 +00:00
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bool no_divider;
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2012-02-16 13:23:58 +00:00
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};
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2009-06-14 12:52:37 +00:00
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static inline struct sdhci_s3c *to_s3c(struct sdhci_host *host)
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{
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return sdhci_priv(host);
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}
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/**
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* sdhci_s3c_get_max_clk - callback to get maximum clock frequency.
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* @host: The SDHCI host instance.
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*
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* Callback to return the maximum clock rate acheivable by the controller.
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*/
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static unsigned int sdhci_s3c_get_max_clk(struct sdhci_host *host)
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{
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struct sdhci_s3c *ourhost = to_s3c(host);
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2014-01-11 21:39:04 +00:00
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unsigned long rate, max = 0;
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int src;
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2009-06-14 12:52:37 +00:00
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2014-01-11 21:39:04 +00:00
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for (src = 0; src < MAX_BUS_CLK; src++) {
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rate = ourhost->clk_rates[src];
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2009-06-14 12:52:37 +00:00
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if (rate > max)
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max = rate;
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}
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return max;
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}
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/**
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* sdhci_s3c_consider_clock - consider one the bus clocks for current setting
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* @ourhost: Our SDHCI instance.
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* @src: The source clock index.
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* @wanted: The clock frequency wanted.
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*/
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static unsigned int sdhci_s3c_consider_clock(struct sdhci_s3c *ourhost,
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unsigned int src,
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unsigned int wanted)
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{
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unsigned long rate;
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struct clk *clksrc = ourhost->clk_bus[src];
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2014-01-11 21:39:01 +00:00
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int shift;
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2009-06-14 12:52:37 +00:00
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2014-01-11 21:39:03 +00:00
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if (IS_ERR(clksrc))
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2009-06-14 12:52:37 +00:00
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return UINT_MAX;
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2010-10-08 08:46:21 +00:00
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/*
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2012-02-16 13:23:58 +00:00
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* If controller uses a non-standard clock division, find the best clock
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* speed possible with selected clock source and skip the division.
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2010-10-08 08:46:21 +00:00
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*/
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2014-04-25 11:58:55 +00:00
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if (ourhost->no_divider) {
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2010-10-08 08:46:21 +00:00
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rate = clk_round_rate(clksrc, wanted);
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return wanted - rate;
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}
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2014-01-11 21:39:02 +00:00
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rate = ourhost->clk_rates[src];
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2009-06-14 12:52:37 +00:00
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2014-01-11 21:39:06 +00:00
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for (shift = 0; shift <= 8; ++shift) {
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2014-01-11 21:39:01 +00:00
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if ((rate >> shift) <= wanted)
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2009-06-14 12:52:37 +00:00
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break;
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}
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2014-01-11 21:39:06 +00:00
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if (shift > 8) {
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dev_dbg(&ourhost->pdev->dev,
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"clk %d: rate %ld, min rate %lu > wanted %u\n",
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src, rate, rate / 256, wanted);
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return UINT_MAX;
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}
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2009-06-14 12:52:37 +00:00
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dev_dbg(&ourhost->pdev->dev, "clk %d: rate %ld, want %d, got %ld\n",
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2014-01-11 21:39:01 +00:00
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src, rate, wanted, rate >> shift);
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2009-06-14 12:52:37 +00:00
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2014-01-11 21:39:01 +00:00
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return wanted - (rate >> shift);
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2009-06-14 12:52:37 +00:00
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}
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/**
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* sdhci_s3c_set_clock - callback on clock change
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* @host: The SDHCI host being changed
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* @clock: The clock rate being requested.
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*
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* When the card's clock is going to be changed, look at the new frequency
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* and find the best clock source to go with it.
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*/
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static void sdhci_s3c_set_clock(struct sdhci_host *host, unsigned int clock)
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{
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struct sdhci_s3c *ourhost = to_s3c(host);
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unsigned int best = UINT_MAX;
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unsigned int delta;
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int best_src = 0;
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int src;
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u32 ctrl;
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2014-04-25 11:58:50 +00:00
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host->mmc->actual_clock = 0;
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2009-06-14 12:52:37 +00:00
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/* don't bother if the clock is going off. */
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2014-04-25 11:58:55 +00:00
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if (clock == 0) {
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sdhci_set_clock(host, clock);
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2009-06-14 12:52:37 +00:00
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return;
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2014-04-25 11:58:55 +00:00
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}
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2009-06-14 12:52:37 +00:00
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|
|
for (src = 0; src < MAX_BUS_CLK; src++) {
|
|
|
|
delta = sdhci_s3c_consider_clock(ourhost, src, clock);
|
|
|
|
if (delta < best) {
|
|
|
|
best = delta;
|
|
|
|
best_src = src;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
dev_dbg(&ourhost->pdev->dev,
|
|
|
|
"selected source %d, clock %d, delta %d\n",
|
|
|
|
best_src, clock, best);
|
|
|
|
|
|
|
|
/* select the new clock source */
|
|
|
|
if (ourhost->cur_clk != best_src) {
|
|
|
|
struct clk *clk = ourhost->clk_bus[best_src];
|
|
|
|
|
2012-10-02 23:35:43 +00:00
|
|
|
clk_prepare_enable(clk);
|
2014-01-11 21:39:05 +00:00
|
|
|
if (ourhost->cur_clk >= 0)
|
|
|
|
clk_disable_unprepare(
|
|
|
|
ourhost->clk_bus[ourhost->cur_clk]);
|
2009-06-14 12:52:37 +00:00
|
|
|
|
|
|
|
ourhost->cur_clk = best_src;
|
2014-01-11 21:39:02 +00:00
|
|
|
host->max_clk = ourhost->clk_rates[best_src];
|
2009-06-14 12:52:37 +00:00
|
|
|
}
|
|
|
|
|
2014-01-11 21:39:05 +00:00
|
|
|
/* turn clock off to card before changing clock source */
|
|
|
|
writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL);
|
|
|
|
|
|
|
|
ctrl = readl(host->ioaddr + S3C_SDHCI_CONTROL2);
|
|
|
|
ctrl &= ~S3C_SDHCI_CTRL2_SELBASECLK_MASK;
|
|
|
|
ctrl |= best_src << S3C_SDHCI_CTRL2_SELBASECLK_SHIFT;
|
|
|
|
writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL2);
|
|
|
|
|
2011-09-14 07:09:17 +00:00
|
|
|
/* reprogram default hardware configuration */
|
|
|
|
writel(S3C64XX_SDHCI_CONTROL4_DRIVE_9mA,
|
|
|
|
host->ioaddr + S3C64XX_SDHCI_CONTROL4);
|
|
|
|
|
|
|
|
ctrl = readl(host->ioaddr + S3C_SDHCI_CONTROL2);
|
|
|
|
ctrl |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR |
|
|
|
|
S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK |
|
|
|
|
S3C_SDHCI_CTRL2_ENFBCLKRX |
|
|
|
|
S3C_SDHCI_CTRL2_DFCNT_NONE |
|
|
|
|
S3C_SDHCI_CTRL2_ENCLKOUTHOLD);
|
|
|
|
writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL2);
|
|
|
|
|
|
|
|
/* reconfigure the controller for new clock rate */
|
|
|
|
ctrl = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0);
|
|
|
|
if (clock < 25 * 1000000)
|
|
|
|
ctrl |= (S3C_SDHCI_CTRL3_FCSEL3 | S3C_SDHCI_CTRL3_FCSEL2);
|
|
|
|
writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL3);
|
2014-04-25 11:58:55 +00:00
|
|
|
|
|
|
|
sdhci_set_clock(host, clock);
|
2009-06-14 12:52:37 +00:00
|
|
|
}
|
|
|
|
|
2010-08-11 01:01:56 +00:00
|
|
|
/**
|
|
|
|
* sdhci_s3c_get_min_clock - callback to get minimal supported clock value
|
|
|
|
* @host: The SDHCI host being queried
|
|
|
|
*
|
|
|
|
* To init mmc host properly a minimal clock value is needed. For high system
|
|
|
|
* bus clock's values the standard formula gives values out of allowed range.
|
|
|
|
* The clock still can be set to lower values, if clock source other then
|
|
|
|
* system bus is selected.
|
|
|
|
*/
|
|
|
|
static unsigned int sdhci_s3c_get_min_clock(struct sdhci_host *host)
|
|
|
|
{
|
|
|
|
struct sdhci_s3c *ourhost = to_s3c(host);
|
2014-01-11 21:39:04 +00:00
|
|
|
unsigned long rate, min = ULONG_MAX;
|
2010-08-11 01:01:56 +00:00
|
|
|
int src;
|
|
|
|
|
|
|
|
for (src = 0; src < MAX_BUS_CLK; src++) {
|
2014-01-11 21:39:04 +00:00
|
|
|
rate = ourhost->clk_rates[src] / 256;
|
|
|
|
if (!rate)
|
2010-08-11 01:01:56 +00:00
|
|
|
continue;
|
2014-01-11 21:39:04 +00:00
|
|
|
if (rate < min)
|
|
|
|
min = rate;
|
2010-08-11 01:01:56 +00:00
|
|
|
}
|
2014-01-11 21:39:04 +00:00
|
|
|
|
2010-08-11 01:01:56 +00:00
|
|
|
return min;
|
|
|
|
}
|
|
|
|
|
2010-10-08 08:46:21 +00:00
|
|
|
/* sdhci_cmu_get_max_clk - callback to get maximum clock frequency.*/
|
|
|
|
static unsigned int sdhci_cmu_get_max_clock(struct sdhci_host *host)
|
|
|
|
{
|
|
|
|
struct sdhci_s3c *ourhost = to_s3c(host);
|
2014-01-11 21:39:04 +00:00
|
|
|
unsigned long rate, max = 0;
|
|
|
|
int src;
|
|
|
|
|
|
|
|
for (src = 0; src < MAX_BUS_CLK; src++) {
|
|
|
|
struct clk *clk;
|
|
|
|
|
|
|
|
clk = ourhost->clk_bus[src];
|
|
|
|
if (IS_ERR(clk))
|
|
|
|
continue;
|
|
|
|
|
|
|
|
rate = clk_round_rate(clk, ULONG_MAX);
|
|
|
|
if (rate > max)
|
|
|
|
max = rate;
|
|
|
|
}
|
2010-10-08 08:46:21 +00:00
|
|
|
|
2014-01-11 21:39:04 +00:00
|
|
|
return max;
|
2010-10-08 08:46:21 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/* sdhci_cmu_get_min_clock - callback to get minimal supported clock value. */
|
|
|
|
static unsigned int sdhci_cmu_get_min_clock(struct sdhci_host *host)
|
|
|
|
{
|
|
|
|
struct sdhci_s3c *ourhost = to_s3c(host);
|
2014-01-11 21:39:04 +00:00
|
|
|
unsigned long rate, min = ULONG_MAX;
|
|
|
|
int src;
|
2010-10-08 08:46:21 +00:00
|
|
|
|
2014-01-11 21:39:04 +00:00
|
|
|
for (src = 0; src < MAX_BUS_CLK; src++) {
|
|
|
|
struct clk *clk;
|
|
|
|
|
|
|
|
clk = ourhost->clk_bus[src];
|
|
|
|
if (IS_ERR(clk))
|
|
|
|
continue;
|
|
|
|
|
|
|
|
rate = clk_round_rate(clk, 0);
|
|
|
|
if (rate < min)
|
|
|
|
min = rate;
|
|
|
|
}
|
|
|
|
|
|
|
|
return min;
|
2010-10-08 08:46:21 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/* sdhci_cmu_set_clock - callback on clock change.*/
|
|
|
|
static void sdhci_cmu_set_clock(struct sdhci_host *host, unsigned int clock)
|
|
|
|
{
|
|
|
|
struct sdhci_s3c *ourhost = to_s3c(host);
|
2012-08-29 05:35:06 +00:00
|
|
|
struct device *dev = &ourhost->pdev->dev;
|
2012-02-16 13:23:58 +00:00
|
|
|
unsigned long timeout;
|
|
|
|
u16 clk = 0;
|
2014-11-04 12:26:42 +00:00
|
|
|
int ret;
|
2010-10-08 08:46:21 +00:00
|
|
|
|
2014-04-25 11:58:50 +00:00
|
|
|
host->mmc->actual_clock = 0;
|
|
|
|
|
2013-08-02 14:08:58 +00:00
|
|
|
/* If the clock is going off, set to 0 at clock control register */
|
|
|
|
if (clock == 0) {
|
|
|
|
sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
|
2010-10-08 08:46:21 +00:00
|
|
|
return;
|
2013-08-02 14:08:58 +00:00
|
|
|
}
|
2010-10-08 08:46:21 +00:00
|
|
|
|
|
|
|
sdhci_s3c_set_clock(host, clock);
|
|
|
|
|
2015-02-04 09:16:59 +00:00
|
|
|
/* Reset SD Clock Enable */
|
|
|
|
clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
|
|
|
|
clk &= ~SDHCI_CLOCK_CARD_EN;
|
|
|
|
sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
|
|
|
|
|
2014-11-04 12:26:42 +00:00
|
|
|
ret = clk_set_rate(ourhost->clk_bus[ourhost->cur_clk], clock);
|
|
|
|
if (ret != 0) {
|
|
|
|
dev_err(dev, "%s: failed to set clock rate %uHz\n",
|
|
|
|
mmc_hostname(host->mmc), clock);
|
|
|
|
return;
|
|
|
|
}
|
2010-10-08 08:46:21 +00:00
|
|
|
|
2012-02-16 13:23:58 +00:00
|
|
|
clk = SDHCI_CLOCK_INT_EN;
|
|
|
|
sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
|
|
|
|
|
|
|
|
/* Wait max 20 ms */
|
|
|
|
timeout = 20;
|
|
|
|
while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
|
|
|
|
& SDHCI_CLOCK_INT_STABLE)) {
|
|
|
|
if (timeout == 0) {
|
2012-08-29 05:35:06 +00:00
|
|
|
dev_err(dev, "%s: Internal clock never stabilised.\n",
|
|
|
|
mmc_hostname(host->mmc));
|
2012-02-16 13:23:58 +00:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
timeout--;
|
|
|
|
mdelay(1);
|
|
|
|
}
|
|
|
|
|
|
|
|
clk |= SDHCI_CLOCK_CARD_EN;
|
|
|
|
sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
|
2010-10-08 08:46:21 +00:00
|
|
|
}
|
|
|
|
|
2009-06-14 12:52:37 +00:00
|
|
|
static struct sdhci_ops sdhci_s3c_ops = {
|
|
|
|
.get_max_clock = sdhci_s3c_get_max_clk,
|
|
|
|
.set_clock = sdhci_s3c_set_clock,
|
2010-08-11 01:01:56 +00:00
|
|
|
.get_min_clock = sdhci_s3c_get_min_clock,
|
2017-08-14 20:00:26 +00:00
|
|
|
.set_bus_width = sdhci_set_bus_width,
|
2014-04-25 11:57:12 +00:00
|
|
|
.reset = sdhci_reset,
|
2014-04-25 11:59:26 +00:00
|
|
|
.set_uhs_signaling = sdhci_set_uhs_signaling,
|
2009-06-14 12:52:37 +00:00
|
|
|
};
|
|
|
|
|
2012-08-23 17:10:09 +00:00
|
|
|
#ifdef CONFIG_OF
|
2012-11-19 18:23:06 +00:00
|
|
|
static int sdhci_s3c_parse_dt(struct device *dev,
|
2012-08-23 17:10:09 +00:00
|
|
|
struct sdhci_host *host, struct s3c_sdhci_platdata *pdata)
|
|
|
|
{
|
|
|
|
struct device_node *node = dev->of_node;
|
|
|
|
u32 max_width;
|
|
|
|
|
|
|
|
/* if the bus-width property is not specified, assume width as 1 */
|
|
|
|
if (of_property_read_u32(node, "bus-width", &max_width))
|
|
|
|
max_width = 1;
|
|
|
|
pdata->max_width = max_width;
|
|
|
|
|
|
|
|
/* get the card detection method */
|
2012-11-20 04:11:53 +00:00
|
|
|
if (of_get_property(node, "broken-cd", NULL)) {
|
2012-08-23 17:10:09 +00:00
|
|
|
pdata->cd_type = S3C_SDHCI_CD_NONE;
|
2013-03-06 11:36:16 +00:00
|
|
|
return 0;
|
2012-08-23 17:10:09 +00:00
|
|
|
}
|
|
|
|
|
2012-11-20 04:11:53 +00:00
|
|
|
if (of_get_property(node, "non-removable", NULL)) {
|
2012-08-23 17:10:09 +00:00
|
|
|
pdata->cd_type = S3C_SDHCI_CD_PERMANENT;
|
2013-03-06 11:36:16 +00:00
|
|
|
return 0;
|
2012-08-23 17:10:09 +00:00
|
|
|
}
|
|
|
|
|
2014-05-26 04:58:28 +00:00
|
|
|
if (of_get_named_gpio(node, "cd-gpios", 0))
|
2012-11-16 14:28:17 +00:00
|
|
|
return 0;
|
2012-08-23 17:10:09 +00:00
|
|
|
|
2013-03-06 11:36:16 +00:00
|
|
|
/* assuming internal card detect that will be configured by pinctrl */
|
|
|
|
pdata->cd_type = S3C_SDHCI_CD_INTERNAL;
|
2012-08-23 17:10:09 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
#else
|
2012-11-19 18:23:06 +00:00
|
|
|
static int sdhci_s3c_parse_dt(struct device *dev,
|
2012-08-23 17:10:09 +00:00
|
|
|
struct sdhci_host *host, struct s3c_sdhci_platdata *pdata)
|
|
|
|
{
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
static const struct of_device_id sdhci_s3c_dt_match[];
|
|
|
|
|
2012-02-16 13:23:58 +00:00
|
|
|
static inline struct sdhci_s3c_drv_data *sdhci_s3c_get_driver_data(
|
|
|
|
struct platform_device *pdev)
|
|
|
|
{
|
2012-08-23 17:10:09 +00:00
|
|
|
#ifdef CONFIG_OF
|
|
|
|
if (pdev->dev.of_node) {
|
|
|
|
const struct of_device_id *match;
|
|
|
|
match = of_match_node(sdhci_s3c_dt_match, pdev->dev.of_node);
|
|
|
|
return (struct sdhci_s3c_drv_data *)match->data;
|
|
|
|
}
|
|
|
|
#endif
|
2012-02-16 13:23:58 +00:00
|
|
|
return (struct sdhci_s3c_drv_data *)
|
|
|
|
platform_get_device_id(pdev)->driver_data;
|
|
|
|
}
|
|
|
|
|
2012-11-19 18:23:06 +00:00
|
|
|
static int sdhci_s3c_probe(struct platform_device *pdev)
|
2009-06-14 12:52:37 +00:00
|
|
|
{
|
2012-02-16 13:23:59 +00:00
|
|
|
struct s3c_sdhci_platdata *pdata;
|
2012-02-16 13:23:58 +00:00
|
|
|
struct sdhci_s3c_drv_data *drv_data;
|
2009-06-14 12:52:37 +00:00
|
|
|
struct device *dev = &pdev->dev;
|
|
|
|
struct sdhci_host *host;
|
|
|
|
struct sdhci_s3c *sc;
|
|
|
|
int ret, irq, ptr, clks;
|
|
|
|
|
2012-08-23 17:10:09 +00:00
|
|
|
if (!pdev->dev.platform_data && !pdev->dev.of_node) {
|
2009-06-14 12:52:37 +00:00
|
|
|
dev_err(dev, "no device data specified\n");
|
|
|
|
return -ENOENT;
|
|
|
|
}
|
|
|
|
|
|
|
|
irq = platform_get_irq(pdev, 0);
|
2019-07-30 18:15:29 +00:00
|
|
|
if (irq < 0)
|
2009-06-14 12:52:37 +00:00
|
|
|
return irq;
|
|
|
|
|
|
|
|
host = sdhci_alloc_host(dev, sizeof(struct sdhci_s3c));
|
|
|
|
if (IS_ERR(host)) {
|
|
|
|
dev_err(dev, "sdhci_alloc_host() failed\n");
|
|
|
|
return PTR_ERR(host);
|
|
|
|
}
|
2012-08-23 17:10:09 +00:00
|
|
|
sc = sdhci_priv(host);
|
2009-06-14 12:52:37 +00:00
|
|
|
|
2012-02-16 13:23:59 +00:00
|
|
|
pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
|
|
|
|
if (!pdata) {
|
|
|
|
ret = -ENOMEM;
|
2012-11-25 20:40:44 +00:00
|
|
|
goto err_pdata_io_clk;
|
2012-08-23 17:10:09 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
if (pdev->dev.of_node) {
|
|
|
|
ret = sdhci_s3c_parse_dt(&pdev->dev, host, pdata);
|
|
|
|
if (ret)
|
2012-11-25 20:40:44 +00:00
|
|
|
goto err_pdata_io_clk;
|
2012-08-23 17:10:09 +00:00
|
|
|
} else {
|
|
|
|
memcpy(pdata, pdev->dev.platform_data, sizeof(*pdata));
|
2012-02-16 13:23:59 +00:00
|
|
|
}
|
|
|
|
|
2012-02-16 13:23:58 +00:00
|
|
|
drv_data = sdhci_s3c_get_driver_data(pdev);
|
2009-06-14 12:52:37 +00:00
|
|
|
|
|
|
|
sc->host = host;
|
|
|
|
sc->pdev = pdev;
|
|
|
|
sc->pdata = pdata;
|
2014-01-11 21:39:05 +00:00
|
|
|
sc->cur_clk = -1;
|
2009-06-14 12:52:37 +00:00
|
|
|
|
|
|
|
platform_set_drvdata(pdev, host);
|
|
|
|
|
2013-02-12 03:24:39 +00:00
|
|
|
sc->clk_io = devm_clk_get(dev, "hsmmc");
|
2009-06-14 12:52:37 +00:00
|
|
|
if (IS_ERR(sc->clk_io)) {
|
|
|
|
dev_err(dev, "failed to get io clock\n");
|
|
|
|
ret = PTR_ERR(sc->clk_io);
|
2012-11-25 20:40:44 +00:00
|
|
|
goto err_pdata_io_clk;
|
2009-06-14 12:52:37 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/* enable the local io clock and keep it running for the moment. */
|
2012-10-02 23:35:43 +00:00
|
|
|
clk_prepare_enable(sc->clk_io);
|
2009-06-14 12:52:37 +00:00
|
|
|
|
|
|
|
for (clks = 0, ptr = 0; ptr < MAX_BUS_CLK; ptr++) {
|
2011-11-03 01:52:58 +00:00
|
|
|
char name[14];
|
2009-06-14 12:52:37 +00:00
|
|
|
|
2011-11-03 01:52:58 +00:00
|
|
|
snprintf(name, 14, "mmc_busclk.%d", ptr);
|
2014-01-11 21:39:03 +00:00
|
|
|
sc->clk_bus[ptr] = devm_clk_get(dev, name);
|
|
|
|
if (IS_ERR(sc->clk_bus[ptr]))
|
2009-06-14 12:52:37 +00:00
|
|
|
continue;
|
|
|
|
|
|
|
|
clks++;
|
2014-01-11 21:39:02 +00:00
|
|
|
sc->clk_rates[ptr] = clk_get_rate(sc->clk_bus[ptr]);
|
|
|
|
|
2009-06-14 12:52:37 +00:00
|
|
|
dev_info(dev, "clock source %d: %s (%ld Hz)\n",
|
2014-01-11 21:39:02 +00:00
|
|
|
ptr, name, sc->clk_rates[ptr]);
|
2009-06-14 12:52:37 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
if (clks == 0) {
|
|
|
|
dev_err(dev, "failed to find any bus clocks\n");
|
|
|
|
ret = -ENOENT;
|
|
|
|
goto err_no_busclks;
|
|
|
|
}
|
|
|
|
|
2019-12-15 17:51:11 +00:00
|
|
|
host->ioaddr = devm_platform_ioremap_resource(pdev, 0);
|
2013-01-21 10:09:11 +00:00
|
|
|
if (IS_ERR(host->ioaddr)) {
|
|
|
|
ret = PTR_ERR(host->ioaddr);
|
2009-06-14 12:52:37 +00:00
|
|
|
goto err_req_regs;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Ensure we have minimal gpio selected CMD/CLK/Detect */
|
|
|
|
if (pdata->cfg_gpio)
|
|
|
|
pdata->cfg_gpio(pdev, pdata->max_width);
|
|
|
|
|
|
|
|
host->hw_name = "samsung-hsmmc";
|
|
|
|
host->ops = &sdhci_s3c_ops;
|
|
|
|
host->quirks = 0;
|
2013-08-02 14:09:00 +00:00
|
|
|
host->quirks2 = 0;
|
2009-06-14 12:52:37 +00:00
|
|
|
host->irq = irq;
|
|
|
|
|
|
|
|
/* Setup quirks for the controller */
|
2010-05-26 21:42:05 +00:00
|
|
|
host->quirks |= SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC;
|
2010-08-11 01:01:57 +00:00
|
|
|
host->quirks |= SDHCI_QUIRK_NO_HISPD_BIT;
|
2014-04-25 11:58:55 +00:00
|
|
|
if (drv_data) {
|
2012-02-16 13:23:58 +00:00
|
|
|
host->quirks |= drv_data->sdhci_quirks;
|
2014-04-25 11:58:55 +00:00
|
|
|
sc->no_divider = drv_data->no_divider;
|
|
|
|
}
|
2009-06-14 12:52:37 +00:00
|
|
|
|
|
|
|
#ifndef CONFIG_MMC_SDHCI_S3C_DMA
|
|
|
|
|
|
|
|
/* we currently see overruns on errors, so disable the SDMA
|
|
|
|
* support as well. */
|
|
|
|
host->quirks |= SDHCI_QUIRK_BROKEN_DMA;
|
|
|
|
|
|
|
|
#endif /* CONFIG_MMC_SDHCI_S3C_DMA */
|
|
|
|
|
|
|
|
/* It seems we do not get an DATA transfer complete on non-busy
|
|
|
|
* transfers, not sure if this is a problem with this specific
|
|
|
|
* SDHCI block, or a missing configuration that needs to be set. */
|
|
|
|
host->quirks |= SDHCI_QUIRK_NO_BUSY_IRQ;
|
|
|
|
|
2010-10-30 03:58:56 +00:00
|
|
|
/* This host supports the Auto CMD12 */
|
|
|
|
host->quirks |= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12;
|
|
|
|
|
2011-07-12 08:30:47 +00:00
|
|
|
/* Samsung SoCs need BROKEN_ADMA_ZEROLEN_DESC */
|
|
|
|
host->quirks |= SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC;
|
|
|
|
|
2010-08-11 01:01:58 +00:00
|
|
|
if (pdata->cd_type == S3C_SDHCI_CD_NONE ||
|
|
|
|
pdata->cd_type == S3C_SDHCI_CD_PERMANENT)
|
|
|
|
host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION;
|
|
|
|
|
|
|
|
if (pdata->cd_type == S3C_SDHCI_CD_PERMANENT)
|
|
|
|
host->mmc->caps = MMC_CAP_NONREMOVABLE;
|
|
|
|
|
2012-04-01 03:29:45 +00:00
|
|
|
switch (pdata->max_width) {
|
|
|
|
case 8:
|
|
|
|
host->mmc->caps |= MMC_CAP_8_BIT_DATA;
|
2019-07-29 00:02:59 +00:00
|
|
|
/* Fall through */
|
2012-04-01 03:29:45 +00:00
|
|
|
case 4:
|
|
|
|
host->mmc->caps |= MMC_CAP_4_BIT_DATA;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2011-11-07 17:05:22 +00:00
|
|
|
if (pdata->pm_caps)
|
|
|
|
host->mmc->pm_caps |= pdata->pm_caps;
|
|
|
|
|
2009-06-14 12:52:37 +00:00
|
|
|
host->quirks |= (SDHCI_QUIRK_32BIT_DMA_ADDR |
|
|
|
|
SDHCI_QUIRK_32BIT_DMA_SIZE);
|
|
|
|
|
2010-08-11 01:01:55 +00:00
|
|
|
/* HSMMC on Samsung SoCs uses SDCLK as timeout clock */
|
|
|
|
host->quirks |= SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK;
|
|
|
|
|
2010-10-08 08:46:21 +00:00
|
|
|
/*
|
|
|
|
* If controller does not have internal clock divider,
|
|
|
|
* we can use overriding functions instead of default.
|
|
|
|
*/
|
2014-04-25 11:58:55 +00:00
|
|
|
if (sc->no_divider) {
|
2010-10-08 08:46:21 +00:00
|
|
|
sdhci_s3c_ops.set_clock = sdhci_cmu_set_clock;
|
|
|
|
sdhci_s3c_ops.get_min_clock = sdhci_cmu_get_min_clock;
|
|
|
|
sdhci_s3c_ops.get_max_clock = sdhci_cmu_get_max_clock;
|
|
|
|
}
|
|
|
|
|
2010-10-08 08:46:20 +00:00
|
|
|
/* It supports additional host capabilities if needed */
|
|
|
|
if (pdata->host_caps)
|
|
|
|
host->mmc->caps |= pdata->host_caps;
|
|
|
|
|
2012-02-07 06:59:01 +00:00
|
|
|
if (pdata->host_caps2)
|
|
|
|
host->mmc->caps2 |= pdata->host_caps2;
|
|
|
|
|
2012-04-01 03:31:55 +00:00
|
|
|
pm_runtime_enable(&pdev->dev);
|
|
|
|
pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
|
|
|
|
pm_runtime_use_autosuspend(&pdev->dev);
|
|
|
|
pm_suspend_ignore_children(&pdev->dev, 1);
|
|
|
|
|
2014-12-18 09:41:42 +00:00
|
|
|
ret = mmc_of_parse(host->mmc);
|
|
|
|
if (ret)
|
|
|
|
goto err_req_regs;
|
2014-05-26 04:58:28 +00:00
|
|
|
|
2009-06-14 12:52:37 +00:00
|
|
|
ret = sdhci_add_host(host);
|
2018-05-25 07:15:09 +00:00
|
|
|
if (ret)
|
2012-03-09 04:24:53 +00:00
|
|
|
goto err_req_regs;
|
2009-06-14 12:52:37 +00:00
|
|
|
|
2014-12-05 02:05:33 +00:00
|
|
|
#ifdef CONFIG_PM
|
2012-10-30 05:28:36 +00:00
|
|
|
if (pdata->cd_type != S3C_SDHCI_CD_INTERNAL)
|
|
|
|
clk_disable_unprepare(sc->clk_io);
|
2012-09-21 05:42:08 +00:00
|
|
|
#endif
|
2009-06-14 12:52:37 +00:00
|
|
|
return 0;
|
|
|
|
|
|
|
|
err_req_regs:
|
2014-08-07 16:07:07 +00:00
|
|
|
pm_runtime_disable(&pdev->dev);
|
|
|
|
|
2009-06-14 12:52:37 +00:00
|
|
|
err_no_busclks:
|
2012-10-02 23:35:43 +00:00
|
|
|
clk_disable_unprepare(sc->clk_io);
|
2009-06-14 12:52:37 +00:00
|
|
|
|
2012-11-25 20:40:44 +00:00
|
|
|
err_pdata_io_clk:
|
2009-06-14 12:52:37 +00:00
|
|
|
sdhci_free_host(host);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2012-11-19 18:26:03 +00:00
|
|
|
static int sdhci_s3c_remove(struct platform_device *pdev)
|
2009-06-14 12:52:37 +00:00
|
|
|
{
|
2010-07-20 20:24:33 +00:00
|
|
|
struct sdhci_host *host = platform_get_drvdata(pdev);
|
|
|
|
struct sdhci_s3c *sc = sdhci_priv(host);
|
2010-08-11 01:01:58 +00:00
|
|
|
|
|
|
|
if (sc->ext_cd_irq)
|
|
|
|
free_irq(sc->ext_cd_irq, sc);
|
|
|
|
|
2014-12-05 02:05:33 +00:00
|
|
|
#ifdef CONFIG_PM
|
2014-05-26 04:58:28 +00:00
|
|
|
if (sc->pdata->cd_type != S3C_SDHCI_CD_INTERNAL)
|
2012-10-30 05:28:36 +00:00
|
|
|
clk_prepare_enable(sc->clk_io);
|
2012-09-21 05:42:08 +00:00
|
|
|
#endif
|
2010-07-20 20:24:33 +00:00
|
|
|
sdhci_remove_host(host, 1);
|
|
|
|
|
2012-09-14 09:08:50 +00:00
|
|
|
pm_runtime_dont_use_autosuspend(&pdev->dev);
|
2012-04-01 03:31:55 +00:00
|
|
|
pm_runtime_disable(&pdev->dev);
|
|
|
|
|
2012-10-02 23:35:43 +00:00
|
|
|
clk_disable_unprepare(sc->clk_io);
|
2010-07-20 20:24:33 +00:00
|
|
|
|
|
|
|
sdhci_free_host(host);
|
|
|
|
|
2009-06-14 12:52:37 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2012-03-03 00:46:41 +00:00
|
|
|
#ifdef CONFIG_PM_SLEEP
|
2011-11-03 10:09:45 +00:00
|
|
|
static int sdhci_s3c_suspend(struct device *dev)
|
2009-06-14 12:52:37 +00:00
|
|
|
{
|
2011-11-03 10:09:45 +00:00
|
|
|
struct sdhci_host *host = dev_get_drvdata(dev);
|
2009-06-14 12:52:37 +00:00
|
|
|
|
2017-03-20 17:50:32 +00:00
|
|
|
if (host->tuning_mode != SDHCI_TUNING_MODE_3)
|
|
|
|
mmc_retune_needed(host->mmc);
|
|
|
|
|
2011-11-03 10:09:45 +00:00
|
|
|
return sdhci_suspend_host(host);
|
2009-06-14 12:52:37 +00:00
|
|
|
}
|
|
|
|
|
2011-11-03 10:09:45 +00:00
|
|
|
static int sdhci_s3c_resume(struct device *dev)
|
2009-06-14 12:52:37 +00:00
|
|
|
{
|
2011-11-03 10:09:45 +00:00
|
|
|
struct sdhci_host *host = dev_get_drvdata(dev);
|
2009-06-14 12:52:37 +00:00
|
|
|
|
2011-06-29 02:38:38 +00:00
|
|
|
return sdhci_resume_host(host);
|
2009-06-14 12:52:37 +00:00
|
|
|
}
|
2012-03-03 00:46:41 +00:00
|
|
|
#endif
|
2009-06-14 12:52:37 +00:00
|
|
|
|
2014-12-05 02:05:33 +00:00
|
|
|
#ifdef CONFIG_PM
|
2012-04-01 03:31:55 +00:00
|
|
|
static int sdhci_s3c_runtime_suspend(struct device *dev)
|
|
|
|
{
|
|
|
|
struct sdhci_host *host = dev_get_drvdata(dev);
|
2012-09-21 05:42:08 +00:00
|
|
|
struct sdhci_s3c *ourhost = to_s3c(host);
|
|
|
|
struct clk *busclk = ourhost->clk_io;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = sdhci_runtime_suspend_host(host);
|
2012-04-01 03:31:55 +00:00
|
|
|
|
2017-03-20 17:50:32 +00:00
|
|
|
if (host->tuning_mode != SDHCI_TUNING_MODE_3)
|
|
|
|
mmc_retune_needed(host->mmc);
|
|
|
|
|
2014-01-11 21:39:05 +00:00
|
|
|
if (ourhost->cur_clk >= 0)
|
|
|
|
clk_disable_unprepare(ourhost->clk_bus[ourhost->cur_clk]);
|
2012-10-02 23:35:43 +00:00
|
|
|
clk_disable_unprepare(busclk);
|
2012-09-21 05:42:08 +00:00
|
|
|
return ret;
|
2012-04-01 03:31:55 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static int sdhci_s3c_runtime_resume(struct device *dev)
|
|
|
|
{
|
|
|
|
struct sdhci_host *host = dev_get_drvdata(dev);
|
2012-09-21 05:42:08 +00:00
|
|
|
struct sdhci_s3c *ourhost = to_s3c(host);
|
|
|
|
struct clk *busclk = ourhost->clk_io;
|
|
|
|
int ret;
|
2012-04-01 03:31:55 +00:00
|
|
|
|
2012-10-02 23:35:43 +00:00
|
|
|
clk_prepare_enable(busclk);
|
2014-01-11 21:39:05 +00:00
|
|
|
if (ourhost->cur_clk >= 0)
|
|
|
|
clk_prepare_enable(ourhost->clk_bus[ourhost->cur_clk]);
|
2019-07-25 03:14:22 +00:00
|
|
|
ret = sdhci_runtime_resume_host(host, 0);
|
2012-09-21 05:42:08 +00:00
|
|
|
return ret;
|
2012-04-01 03:31:55 +00:00
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2011-11-03 10:09:45 +00:00
|
|
|
static const struct dev_pm_ops sdhci_s3c_pmops = {
|
2012-03-03 00:46:41 +00:00
|
|
|
SET_SYSTEM_SLEEP_PM_OPS(sdhci_s3c_suspend, sdhci_s3c_resume)
|
2012-04-01 03:31:55 +00:00
|
|
|
SET_RUNTIME_PM_OPS(sdhci_s3c_runtime_suspend, sdhci_s3c_runtime_resume,
|
|
|
|
NULL)
|
2011-11-03 10:09:45 +00:00
|
|
|
};
|
|
|
|
|
2015-05-01 15:49:22 +00:00
|
|
|
static const struct platform_device_id sdhci_s3c_driver_ids[] = {
|
2012-02-16 13:23:58 +00:00
|
|
|
{
|
|
|
|
.name = "s3c-sdhci",
|
|
|
|
.driver_data = (kernel_ulong_t)NULL,
|
|
|
|
},
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(platform, sdhci_s3c_driver_ids);
|
|
|
|
|
2012-08-23 17:10:09 +00:00
|
|
|
#ifdef CONFIG_OF
|
2017-10-04 06:38:24 +00:00
|
|
|
static struct sdhci_s3c_drv_data exynos4_sdhci_drv_data = {
|
|
|
|
.no_divider = true,
|
|
|
|
};
|
|
|
|
|
2012-08-23 17:10:09 +00:00
|
|
|
static const struct of_device_id sdhci_s3c_dt_match[] = {
|
|
|
|
{ .compatible = "samsung,s3c6410-sdhci", },
|
|
|
|
{ .compatible = "samsung,exynos4210-sdhci",
|
2017-10-04 06:38:24 +00:00
|
|
|
.data = &exynos4_sdhci_drv_data },
|
2012-08-23 17:10:09 +00:00
|
|
|
{},
|
|
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(of, sdhci_s3c_dt_match);
|
|
|
|
#endif
|
|
|
|
|
2009-06-14 12:52:37 +00:00
|
|
|
static struct platform_driver sdhci_s3c_driver = {
|
|
|
|
.probe = sdhci_s3c_probe,
|
2012-11-19 18:20:26 +00:00
|
|
|
.remove = sdhci_s3c_remove,
|
2012-02-16 13:23:58 +00:00
|
|
|
.id_table = sdhci_s3c_driver_ids,
|
2009-06-14 12:52:37 +00:00
|
|
|
.driver = {
|
|
|
|
.name = "s3c-sdhci",
|
2012-08-23 17:10:09 +00:00
|
|
|
.of_match_table = of_match_ptr(sdhci_s3c_dt_match),
|
2016-07-27 09:23:37 +00:00
|
|
|
.pm = &sdhci_s3c_pmops,
|
2009-06-14 12:52:37 +00:00
|
|
|
},
|
|
|
|
};
|
|
|
|
|
2011-11-26 04:55:43 +00:00
|
|
|
module_platform_driver(sdhci_s3c_driver);
|
2009-06-14 12:52:37 +00:00
|
|
|
|
|
|
|
MODULE_DESCRIPTION("Samsung SDHCI (HSMMC) glue");
|
|
|
|
MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
|
|
|
|
MODULE_LICENSE("GPL v2");
|
|
|
|
MODULE_ALIAS("platform:s3c-sdhci");
|