2010-02-05 11:14:49 +00:00
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/*
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2010-05-20 14:49:28 +00:00
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* SH7367 clock framework support
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2010-02-05 11:14:49 +00:00
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*
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* Copyright (C) 2010 Magnus Damm
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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2010-05-20 14:49:28 +00:00
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#include <linux/io.h>
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2010-05-12 14:21:24 +00:00
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#include <linux/sh_clk.h>
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2010-11-17 09:04:33 +00:00
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#include <linux/clkdev.h>
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2010-05-20 14:49:28 +00:00
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#include <mach/common.h>
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2010-02-05 11:14:49 +00:00
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2010-05-20 14:49:28 +00:00
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/* SH7367 registers */
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#define RTFRQCR 0xe6150000
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#define SYFRQCR 0xe6150004
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#define CMFRQCR 0xe61500E0
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#define VCLKCR1 0xe6150008
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#define VCLKCR2 0xe615000C
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#define VCLKCR3 0xe615001C
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#define SCLKACR 0xe6150010
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#define SCLKBCR 0xe6150014
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#define SUBUSBCKCR 0xe6158080
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#define SPUCKCR 0xe6150084
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#define MSUCKCR 0xe6150088
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#define MVI3CKCR 0xe6150090
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#define VOUCKCR 0xe6150094
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#define MFCK1CR 0xe6150098
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#define MFCK2CR 0xe615009C
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#define PLLC1CR 0xe6150028
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#define PLLC2CR 0xe615002C
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#define RTMSTPCR0 0xe6158030
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#define RTMSTPCR2 0xe6158038
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#define SYMSTPCR0 0xe6158040
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#define SYMSTPCR2 0xe6158048
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#define CMMSTPCR0 0xe615804c
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2010-02-05 11:14:49 +00:00
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2010-05-20 14:49:28 +00:00
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/* Fixed 32 KHz root clock from EXTALR pin */
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2010-02-05 11:14:49 +00:00
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static struct clk r_clk = {
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2010-05-20 14:49:28 +00:00
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.rate = 32768,
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2010-02-05 11:14:49 +00:00
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};
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2010-05-20 14:49:28 +00:00
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/*
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* 26MHz default rate for the EXTALB1 root input clock.
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* If needed, reset this with clk_set_rate() from the platform code.
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*/
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struct clk sh7367_extalb1_clk = {
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.rate = 26666666,
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2010-02-10 11:13:31 +00:00
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};
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2010-05-20 14:49:28 +00:00
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/*
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* 48MHz default rate for the EXTAL2 root input clock.
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* If needed, reset this with clk_set_rate() from the platform code.
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*/
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struct clk sh7367_extal2_clk = {
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.rate = 48000000,
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2010-02-16 10:48:15 +00:00
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};
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2010-05-20 14:49:28 +00:00
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/* A fixed divide-by-2 block */
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static unsigned long div2_recalc(struct clk *clk)
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{
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return clk->parent->rate / 2;
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}
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2012-02-29 13:16:29 +00:00
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static struct sh_clk_ops div2_clk_ops = {
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2010-05-20 14:49:28 +00:00
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.recalc = div2_recalc,
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};
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/* Divide extalb1 by two */
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static struct clk extalb1_div2_clk = {
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.ops = &div2_clk_ops,
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.parent = &sh7367_extalb1_clk,
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};
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/* Divide extal2 by two */
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static struct clk extal2_div2_clk = {
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.ops = &div2_clk_ops,
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.parent = &sh7367_extal2_clk,
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};
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/* PLLC1 */
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static unsigned long pllc1_recalc(struct clk *clk)
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{
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unsigned long mult = 1;
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if (__raw_readl(PLLC1CR) & (1 << 14))
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mult = (((__raw_readl(RTFRQCR) >> 24) & 0x3f) + 1) * 2;
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return clk->parent->rate * mult;
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}
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2012-02-29 13:16:29 +00:00
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static struct sh_clk_ops pllc1_clk_ops = {
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2010-05-20 14:49:28 +00:00
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.recalc = pllc1_recalc,
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};
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static struct clk pllc1_clk = {
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.ops = &pllc1_clk_ops,
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.flags = CLK_ENABLE_ON_INIT,
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.parent = &extalb1_div2_clk,
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};
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/* Divide PLLC1 by two */
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static struct clk pllc1_div2_clk = {
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.ops = &div2_clk_ops,
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.parent = &pllc1_clk,
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};
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/* PLLC2 */
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static unsigned long pllc2_recalc(struct clk *clk)
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{
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unsigned long mult = 1;
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if (__raw_readl(PLLC2CR) & (1 << 31))
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mult = (((__raw_readl(PLLC2CR) >> 24) & 0x3f) + 1) * 2;
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return clk->parent->rate * mult;
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}
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2012-02-29 13:16:29 +00:00
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static struct sh_clk_ops pllc2_clk_ops = {
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2010-05-20 14:49:28 +00:00
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.recalc = pllc2_recalc,
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};
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static struct clk pllc2_clk = {
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.ops = &pllc2_clk_ops,
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.flags = CLK_ENABLE_ON_INIT,
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.parent = &extalb1_div2_clk,
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};
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static struct clk *main_clks[] = {
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&r_clk,
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&sh7367_extalb1_clk,
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&sh7367_extal2_clk,
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&extalb1_div2_clk,
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&extal2_div2_clk,
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&pllc1_clk,
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&pllc1_div2_clk,
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&pllc2_clk,
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};
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static void div4_kick(struct clk *clk)
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{
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unsigned long value;
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/* set KICK bit in SYFRQCR to update hardware setting */
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value = __raw_readl(SYFRQCR);
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value |= (1 << 31);
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__raw_writel(value, SYFRQCR);
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}
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static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18,
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24, 32, 36, 48, 0, 72, 0, 0 };
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static struct clk_div_mult_table div4_div_mult_table = {
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.divisors = divisors,
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.nr_divisors = ARRAY_SIZE(divisors),
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};
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static struct clk_div4_table div4_table = {
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.div_mult_table = &div4_div_mult_table,
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.kick = div4_kick,
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};
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enum { DIV4_I, DIV4_G, DIV4_S, DIV4_B,
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DIV4_ZX, DIV4_ZT, DIV4_Z, DIV4_ZD, DIV4_HP,
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DIV4_ZS, DIV4_ZB, DIV4_ZB3, DIV4_CP, DIV4_NR };
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#define DIV4(_reg, _bit, _mask, _flags) \
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SH_CLK_DIV4(&pllc1_clk, _reg, _bit, _mask, _flags)
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static struct clk div4_clks[DIV4_NR] = {
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[DIV4_I] = DIV4(RTFRQCR, 20, 0x6fff, CLK_ENABLE_ON_INIT),
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[DIV4_G] = DIV4(RTFRQCR, 16, 0x6fff, CLK_ENABLE_ON_INIT),
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[DIV4_S] = DIV4(RTFRQCR, 12, 0x6fff, CLK_ENABLE_ON_INIT),
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[DIV4_B] = DIV4(RTFRQCR, 8, 0x6fff, CLK_ENABLE_ON_INIT),
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[DIV4_ZX] = DIV4(SYFRQCR, 20, 0x6fff, 0),
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[DIV4_ZT] = DIV4(SYFRQCR, 16, 0x6fff, 0),
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[DIV4_Z] = DIV4(SYFRQCR, 12, 0x6fff, 0),
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[DIV4_ZD] = DIV4(SYFRQCR, 8, 0x6fff, 0),
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[DIV4_HP] = DIV4(SYFRQCR, 4, 0x6fff, 0),
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[DIV4_ZS] = DIV4(CMFRQCR, 12, 0x6fff, 0),
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[DIV4_ZB] = DIV4(CMFRQCR, 8, 0x6fff, 0),
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[DIV4_ZB3] = DIV4(CMFRQCR, 4, 0x6fff, 0),
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[DIV4_CP] = DIV4(CMFRQCR, 0, 0x6fff, 0),
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};
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enum { DIV6_SUB, DIV6_SIUA, DIV6_SIUB, DIV6_MSU, DIV6_SPU,
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DIV6_MVI3, DIV6_MF1, DIV6_MF2,
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DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_VOU,
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DIV6_NR };
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static struct clk div6_clks[DIV6_NR] = {
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[DIV6_SUB] = SH_CLK_DIV6(&sh7367_extal2_clk, SUBUSBCKCR, 0),
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[DIV6_SIUA] = SH_CLK_DIV6(&pllc1_div2_clk, SCLKACR, 0),
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[DIV6_SIUB] = SH_CLK_DIV6(&pllc1_div2_clk, SCLKBCR, 0),
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[DIV6_MSU] = SH_CLK_DIV6(&pllc1_div2_clk, MSUCKCR, 0),
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[DIV6_SPU] = SH_CLK_DIV6(&pllc1_div2_clk, SPUCKCR, 0),
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[DIV6_MVI3] = SH_CLK_DIV6(&pllc1_div2_clk, MVI3CKCR, 0),
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[DIV6_MF1] = SH_CLK_DIV6(&pllc1_div2_clk, MFCK1CR, 0),
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[DIV6_MF2] = SH_CLK_DIV6(&pllc1_div2_clk, MFCK2CR, 0),
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[DIV6_VCK1] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR1, 0),
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[DIV6_VCK2] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR2, 0),
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[DIV6_VCK3] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR3, 0),
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[DIV6_VOU] = SH_CLK_DIV6(&pllc1_div2_clk, VOUCKCR, 0),
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};
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enum { RTMSTP001,
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RTMSTP231, RTMSTP230, RTMSTP229, RTMSTP228, RTMSTP226,
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RTMSTP216, RTMSTP206, RTMSTP205, RTMSTP201,
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SYMSTP023, SYMSTP007, SYMSTP006, SYMSTP004,
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SYMSTP003, SYMSTP002, SYMSTP001, SYMSTP000,
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SYMSTP231, SYMSTP229, SYMSTP225, SYMSTP223, SYMSTP222,
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SYMSTP215, SYMSTP214, SYMSTP213, SYMSTP211,
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CMMSTP003,
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MSTP_NR };
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#define MSTP(_parent, _reg, _bit, _flags) \
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SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
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static struct clk mstp_clks[MSTP_NR] = {
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[RTMSTP001] = MSTP(&div6_clks[DIV6_SUB], RTMSTPCR0, 1, 0), /* IIC2 */
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[RTMSTP231] = MSTP(&div4_clks[DIV4_B], RTMSTPCR2, 31, 0), /* VEU3 */
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[RTMSTP230] = MSTP(&div4_clks[DIV4_B], RTMSTPCR2, 30, 0), /* VEU2 */
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[RTMSTP229] = MSTP(&div4_clks[DIV4_B], RTMSTPCR2, 29, 0), /* VEU1 */
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[RTMSTP228] = MSTP(&div4_clks[DIV4_B], RTMSTPCR2, 28, 0), /* VEU0 */
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[RTMSTP226] = MSTP(&div4_clks[DIV4_B], RTMSTPCR2, 26, 0), /* VEU2H */
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[RTMSTP216] = MSTP(&div6_clks[DIV6_SUB], RTMSTPCR2, 16, 0), /* IIC0 */
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[RTMSTP206] = MSTP(&div4_clks[DIV4_B], RTMSTPCR2, 6, 0), /* JPU */
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[RTMSTP205] = MSTP(&div6_clks[DIV6_VOU], RTMSTPCR2, 5, 0), /* VOU */
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[RTMSTP201] = MSTP(&div4_clks[DIV4_B], RTMSTPCR2, 1, 0), /* VPU */
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[SYMSTP023] = MSTP(&div6_clks[DIV6_SPU], SYMSTPCR0, 23, 0), /* SPU1 */
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[SYMSTP007] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR0, 7, 0), /* SCIFA5 */
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[SYMSTP006] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR0, 6, 0), /* SCIFB */
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[SYMSTP004] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR0, 4, 0), /* SCIFA0 */
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[SYMSTP003] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR0, 3, 0), /* SCIFA1 */
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[SYMSTP002] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR0, 2, 0), /* SCIFA2 */
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[SYMSTP001] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR0, 1, 0), /* SCIFA3 */
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[SYMSTP000] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR0, 0, 0), /* SCIFA4 */
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[SYMSTP231] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR2, 31, 0), /* SIU */
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[SYMSTP229] = MSTP(&r_clk, SYMSTPCR2, 29, 0), /* CMT10 */
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[SYMSTP225] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR2, 25, 0), /* IRDA */
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[SYMSTP223] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR2, 23, 0), /* IIC1 */
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[SYMSTP222] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR2, 22, 0), /* USBHS */
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[SYMSTP215] = MSTP(&div4_clks[DIV4_HP], SYMSTPCR2, 15, 0), /* FLCTL */
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[SYMSTP214] = MSTP(&div4_clks[DIV4_HP], SYMSTPCR2, 14, 0), /* SDHI0 */
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[SYMSTP213] = MSTP(&div4_clks[DIV4_HP], SYMSTPCR2, 13, 0), /* SDHI1 */
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[SYMSTP211] = MSTP(&div4_clks[DIV4_HP], SYMSTPCR2, 11, 0), /* SDHI2 */
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[CMMSTP003] = MSTP(&r_clk, CMMSTPCR0, 3, 0), /* KEYSC */
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};
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2010-02-05 11:14:49 +00:00
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static struct clk_lookup lookups[] = {
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2010-05-20 14:49:28 +00:00
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/* main clocks */
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CLKDEV_CON_ID("r_clk", &r_clk),
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CLKDEV_CON_ID("extalb1", &sh7367_extalb1_clk),
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CLKDEV_CON_ID("extal2", &sh7367_extal2_clk),
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CLKDEV_CON_ID("extalb1_div2_clk", &extalb1_div2_clk),
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CLKDEV_CON_ID("extal2_div2_clk", &extal2_div2_clk),
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CLKDEV_CON_ID("pllc1_clk", &pllc1_clk),
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CLKDEV_CON_ID("pllc1_div2_clk", &pllc1_div2_clk),
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CLKDEV_CON_ID("pllc2_clk", &pllc2_clk),
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|
/* DIV4 clocks */
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CLKDEV_CON_ID("i_clk", &div4_clks[DIV4_I]),
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CLKDEV_CON_ID("g_clk", &div4_clks[DIV4_G]),
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CLKDEV_CON_ID("b_clk", &div4_clks[DIV4_B]),
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CLKDEV_CON_ID("zx_clk", &div4_clks[DIV4_ZX]),
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CLKDEV_CON_ID("zt_clk", &div4_clks[DIV4_ZT]),
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CLKDEV_CON_ID("z_clk", &div4_clks[DIV4_Z]),
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CLKDEV_CON_ID("zd_clk", &div4_clks[DIV4_ZD]),
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CLKDEV_CON_ID("hp_clk", &div4_clks[DIV4_HP]),
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CLKDEV_CON_ID("zs_clk", &div4_clks[DIV4_ZS]),
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CLKDEV_CON_ID("zb_clk", &div4_clks[DIV4_ZB]),
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CLKDEV_CON_ID("zb3_clk", &div4_clks[DIV4_ZB3]),
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CLKDEV_CON_ID("cp_clk", &div4_clks[DIV4_CP]),
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|
|
|
/* DIV6 clocks */
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CLKDEV_CON_ID("sub_clk", &div6_clks[DIV6_SUB]),
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|
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CLKDEV_CON_ID("siua_clk", &div6_clks[DIV6_SIUA]),
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|
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CLKDEV_CON_ID("siub_clk", &div6_clks[DIV6_SIUB]),
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|
|
CLKDEV_CON_ID("msu_clk", &div6_clks[DIV6_MSU]),
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|
|
|
|
CLKDEV_CON_ID("spu_clk", &div6_clks[DIV6_SPU]),
|
|
|
|
|
CLKDEV_CON_ID("mvi3_clk", &div6_clks[DIV6_MVI3]),
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|
|
|
|
CLKDEV_CON_ID("mf1_clk", &div6_clks[DIV6_MF1]),
|
|
|
|
|
CLKDEV_CON_ID("mf2_clk", &div6_clks[DIV6_MF2]),
|
|
|
|
|
CLKDEV_CON_ID("vck1_clk", &div6_clks[DIV6_VCK1]),
|
|
|
|
|
CLKDEV_CON_ID("vck2_clk", &div6_clks[DIV6_VCK2]),
|
|
|
|
|
CLKDEV_CON_ID("vck3_clk", &div6_clks[DIV6_VCK3]),
|
|
|
|
|
CLKDEV_CON_ID("vou_clk", &div6_clks[DIV6_VOU]),
|
|
|
|
|
|
|
|
|
|
/* MSTP32 clocks */
|
|
|
|
|
CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[RTMSTP001]), /* IIC2 */
|
|
|
|
|
CLKDEV_DEV_ID("uio_pdrv_genirq.4", &mstp_clks[RTMSTP231]), /* VEU3 */
|
|
|
|
|
CLKDEV_DEV_ID("uio_pdrv_genirq.3", &mstp_clks[RTMSTP230]), /* VEU2 */
|
|
|
|
|
CLKDEV_DEV_ID("uio_pdrv_genirq.2", &mstp_clks[RTMSTP229]), /* VEU1 */
|
|
|
|
|
CLKDEV_DEV_ID("uio_pdrv_genirq.1", &mstp_clks[RTMSTP228]), /* VEU0 */
|
|
|
|
|
CLKDEV_DEV_ID("uio_pdrv_genirq.5", &mstp_clks[RTMSTP226]), /* VEU2H */
|
|
|
|
|
CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[RTMSTP216]), /* IIC0 */
|
|
|
|
|
CLKDEV_DEV_ID("uio_pdrv_genirq.6", &mstp_clks[RTMSTP206]), /* JPU */
|
|
|
|
|
CLKDEV_DEV_ID("sh-vou", &mstp_clks[RTMSTP205]), /* VOU */
|
|
|
|
|
CLKDEV_DEV_ID("uio_pdrv_genirq.0", &mstp_clks[RTMSTP201]), /* VPU */
|
|
|
|
|
CLKDEV_DEV_ID("uio_pdrv_genirq.7", &mstp_clks[SYMSTP023]), /* SPU1 */
|
|
|
|
|
CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[SYMSTP007]), /* SCIFA5 */
|
|
|
|
|
CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[SYMSTP006]), /* SCIFB */
|
|
|
|
|
CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[SYMSTP004]), /* SCIFA0 */
|
|
|
|
|
CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[SYMSTP003]), /* SCIFA1 */
|
|
|
|
|
CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[SYMSTP002]), /* SCIFA2 */
|
|
|
|
|
CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[SYMSTP001]), /* SCIFA3 */
|
|
|
|
|
CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[SYMSTP000]), /* SCIFA4 */
|
|
|
|
|
CLKDEV_DEV_ID("sh_siu", &mstp_clks[SYMSTP231]), /* SIU */
|
2010-10-13 07:29:31 +00:00
|
|
|
CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[SYMSTP229]), /* CMT10 */
|
2010-05-20 14:49:28 +00:00
|
|
|
CLKDEV_DEV_ID("sh_irda", &mstp_clks[SYMSTP225]), /* IRDA */
|
|
|
|
|
CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[SYMSTP223]), /* IIC1 */
|
|
|
|
|
CLKDEV_DEV_ID("r8a66597_hcd.0", &mstp_clks[SYMSTP222]), /* USBHS */
|
|
|
|
|
CLKDEV_DEV_ID("r8a66597_udc.0", &mstp_clks[SYMSTP222]), /* USBHS */
|
|
|
|
|
CLKDEV_DEV_ID("sh_flctl", &mstp_clks[SYMSTP215]), /* FLCTL */
|
|
|
|
|
CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[SYMSTP214]), /* SDHI0 */
|
|
|
|
|
CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[SYMSTP213]), /* SDHI1 */
|
|
|
|
|
CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[SYMSTP211]), /* SDHI2 */
|
|
|
|
|
CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[CMMSTP003]), /* KEYSC */
|
2010-02-05 11:14:49 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
void __init sh7367_clock_init(void)
|
|
|
|
|
{
|
2010-05-20 14:49:28 +00:00
|
|
|
int k, ret = 0;
|
|
|
|
|
|
|
|
|
|
for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
|
|
|
|
|
ret = clk_register(main_clks[k]);
|
|
|
|
|
|
|
|
|
|
if (!ret)
|
|
|
|
|
ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
|
|
|
|
|
|
|
|
|
|
if (!ret)
|
|
|
|
|
ret = sh_clk_div6_register(div6_clks, DIV6_NR);
|
|
|
|
|
|
|
|
|
|
if (!ret)
|
|
|
|
|
ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
|
|
|
|
|
|
|
|
|
|
clkdev_add_table(lookups, ARRAY_SIZE(lookups));
|
2010-02-05 11:14:49 +00:00
|
|
|
|
2010-05-20 14:49:28 +00:00
|
|
|
if (!ret)
|
|
|
|
|
clk_init();
|
|
|
|
|
else
|
|
|
|
|
panic("failed to setup sh7367 clocks\n");
|
2010-02-05 11:14:49 +00:00
|
|
|
}
|
