2005-09-05 22:19:29 +00:00
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/*
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2007-02-20 22:36:14 +00:00
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* Network device driver for Cell Processor-Based Blade and Celleb platform
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2005-09-05 22:19:29 +00:00
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*
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* (C) Copyright IBM Corp. 2005
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2007-02-20 22:36:14 +00:00
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* (C) Copyright 2006 TOSHIBA CORPORATION
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2005-09-05 22:19:29 +00:00
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*
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* Authors : Utz Bacher <utz.bacher@de.ibm.com>
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* Jens Osterkamp <Jens.Osterkamp@de.ibm.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#ifndef _SPIDER_NET_H
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#define _SPIDER_NET_H
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spidernet: Cure RX ram full bug
This patch fixes a rare deadlock that can occur when the kernel
is not able to empty out the RX ring quickly enough. Below follows
a detailed description of the bug and the fix.
As long as the OS can empty out the RX buffers at a rate faster than
the hardware can fill them, there is no problem. If, for some reason,
the OS fails to empty the RX ring fast enough, the hardware GDACTDPA
pointer will catch up to the head, notice the not-empty condition,
ad stop. However, RX packets may still continue arriving on the wire.
The spidernet chip can save some limited number of these in local RAM.
When this local ram fills up, the spider chip will issue an interrupt
indicating this (GHIINT0STS will show ERRINT, and the GRMFLLINT bit
will be set in GHIINT1STS). When te RX ram full condition occurs,
a certain bug/feature is triggered that has to be specially handled.
This section describes the special handling for this condition.
When the OS finally has a chance to run, it will empty out the RX ring.
In particular, it will clear the descriptor on which the hardware had
stopped. However, once the hardware has decided that a certain
descriptor is invalid, it will not restart at that descriptor; instead
it will restart at the next descr. This potentially will lead to a
deadlock condition, as the tail pointer will be pointing at this descr,
which, from the OS point of view, is empty; the OS will be waiting for
this descr to be filled. However, the hardware has skipped this descr,
and is filling the next descrs. Since the OS doesn't see this, there
is a potential deadlock, with the OS waiting for one descr to fill,
while the hardware is waiting for a differen set of descrs to become
empty.
A call to show_rx_chain() at this point indicates the nature of the
problem. A typical print when the network is hung shows the following:
net eth1: Spider RX RAM full, incoming packets might be discarded!
net eth1: Total number of descrs=256
net eth1: Chain tail located at descr=255
net eth1: Chain head is at 255
net eth1: HW curr desc (GDACTDPA) is at 0
net eth1: Have 1 descrs with stat=xa0800000
net eth1: HW next desc (GDACNEXTDA) is at 1
net eth1: Have 127 descrs with stat=x40800101
net eth1: Have 1 descrs with stat=x40800001
net eth1: Have 126 descrs with stat=x40800101
net eth1: Last 1 descrs with stat=xa0800000
Both the tail and head pointers are pointing at descr 255, which is
marked xa... which is "empty". Thus, from the OS point of view, there
is nothing to be done. In particular, there is the implicit assumption
that everything in front of the "empty" descr must surely also be empty,
as explained in the last section. The OS is waiting for descr 255 to
become non-empty, which, in this case, will never happen.
The HW pointer is at descr 0. This descr is marked 0x4.. or "full".
Since its already full, the hardware can do nothing more, and thus has
halted processing. Notice that descrs 0 through 254 are all marked
"full", while descr 254 and 255 are empty. (The "Last 1 descrs" is
descr 254, since tail was at 255.) Thus, the system is deadlocked,
and there can be no forward progress; the OS thinks there's nothing
to do, and the hardware has nowhere to put incoming data.
This bug/feature is worked around with the spider_net_resync_head_ptr()
routine. When the driver receives RX interrupts, but an examination
of the RX chain seems to show it is empty, then it is probable that
the hardware has skipped a descr or two (sometimes dozens under heavy
network conditions). The spider_net_resync_head_ptr() subroutine will
search the ring for the next full descr, and the driver will resume
operations there. Since this will leave "holes" in the ring, there
is also a spider_net_resync_tail_ptr() that will skip over such holes.
Signed-off-by: Linas Vepstas <linas@austin.ibm.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-06-11 18:21:13 +00:00
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#define VERSION "2.0 B"
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2006-10-10 20:56:04 +00:00
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2005-09-05 22:19:29 +00:00
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#include "sungem_phy.h"
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extern int spider_net_stop(struct net_device *netdev);
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extern int spider_net_open(struct net_device *netdev);
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2006-09-13 18:30:00 +00:00
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extern const struct ethtool_ops spider_net_ethtool_ops;
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2005-09-05 22:19:29 +00:00
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extern char spider_net_driver_name[];
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2006-01-12 22:16:44 +00:00
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#define SPIDER_NET_MAX_FRAME 2312
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#define SPIDER_NET_MAX_MTU 2294
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2005-09-05 22:19:29 +00:00
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#define SPIDER_NET_MIN_MTU 64
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#define SPIDER_NET_RXBUF_ALIGN 128
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2006-01-12 22:16:44 +00:00
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#define SPIDER_NET_RX_DESCRIPTORS_DEFAULT 256
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2005-09-05 22:19:29 +00:00
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#define SPIDER_NET_RX_DESCRIPTORS_MIN 16
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2006-01-12 22:16:44 +00:00
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#define SPIDER_NET_RX_DESCRIPTORS_MAX 512
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2005-09-05 22:19:29 +00:00
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2006-01-12 22:16:44 +00:00
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#define SPIDER_NET_TX_DESCRIPTORS_DEFAULT 256
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2005-09-05 22:19:29 +00:00
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#define SPIDER_NET_TX_DESCRIPTORS_MIN 16
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2006-01-12 22:16:44 +00:00
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#define SPIDER_NET_TX_DESCRIPTORS_MAX 512
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[PATCH] powerpc/cell spidernet low watermark patch.
Implement basic low-watermark support for the transmit queue.
Hardware low-watermarks allow a properly configured kernel
to continously stream data to a device and not have to handle
any interrupts at all in doing so. Correct zero-interrupt
operation can be actually observed for this driver, when the
socket buffer is made large enough.
The basic idea of a low-watermark interrupt is as follows.
The device driver queues up a bunch of packets for the hardware
to transmit, and then kicks the hardware to get it started.
As the hardware drains the queue of pending, untransmitted
packets, the device driver will want to know when the queue
is almost empty, so that it can queue some more packets.
If the queue drains down to the low waterark, then an interrupt
will be generated. However, if the kernel/driver continues
to add enough packets to keep the queue partially filled,
no interrupt will actually be generated, and the hardware
can continue streaming packets indefinitely in this mode.
The impelmentation is done by setting the DESCR_TXDESFLG flag
in one of the packets. When the hardware sees this flag, it will
interrupt the device driver. Because this flag is on a fixed
packet, rather than at fixed location in the queue, the
code below needs to move the flag as more packets are
queued up. This implementation attempts to keep the flag
at about 1/4 from "empty".
Signed-off-by: Linas Vepstas <linas@austin.ibm.com>
Signed-off-by: James K Lewis <jklewis@us.ibm.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2006-10-10 21:11:33 +00:00
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#define SPIDER_NET_TX_TIMER (HZ/5)
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2007-02-20 22:33:41 +00:00
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#define SPIDER_NET_ANEG_TIMER (HZ)
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#define SPIDER_NET_ANEG_TIMEOUT 2
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2005-09-05 22:19:29 +00:00
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#define SPIDER_NET_RX_CSUM_DEFAULT 1
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2006-01-12 22:16:44 +00:00
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#define SPIDER_NET_WATCHDOG_TIMEOUT 50*HZ
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#define SPIDER_NET_NAPI_WEIGHT 64
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2005-09-05 22:19:29 +00:00
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2006-01-12 22:16:44 +00:00
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#define SPIDER_NET_FIRMWARE_SEQS 6
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#define SPIDER_NET_FIRMWARE_SEQWORDS 1024
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#define SPIDER_NET_FIRMWARE_LEN (SPIDER_NET_FIRMWARE_SEQS * \
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SPIDER_NET_FIRMWARE_SEQWORDS * \
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sizeof(u32))
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2005-09-05 22:19:29 +00:00
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#define SPIDER_NET_FIRMWARE_NAME "spider_fw.bin"
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/** spider_net SMMIO registers */
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#define SPIDER_NET_GHIINT0STS 0x00000000
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#define SPIDER_NET_GHIINT1STS 0x00000004
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#define SPIDER_NET_GHIINT2STS 0x00000008
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#define SPIDER_NET_GHIINT0MSK 0x00000010
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#define SPIDER_NET_GHIINT1MSK 0x00000014
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#define SPIDER_NET_GHIINT2MSK 0x00000018
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#define SPIDER_NET_GRESUMINTNUM 0x00000020
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#define SPIDER_NET_GREINTNUM 0x00000024
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#define SPIDER_NET_GFFRMNUM 0x00000028
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#define SPIDER_NET_GFAFRMNUM 0x0000002c
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#define SPIDER_NET_GFBFRMNUM 0x00000030
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#define SPIDER_NET_GFCFRMNUM 0x00000034
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#define SPIDER_NET_GFDFRMNUM 0x00000038
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/* clear them (don't use it) */
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#define SPIDER_NET_GFREECNNUM 0x0000003c
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#define SPIDER_NET_GONETIMENUM 0x00000040
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#define SPIDER_NET_GTOUTFRMNUM 0x00000044
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#define SPIDER_NET_GTXMDSET 0x00000050
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#define SPIDER_NET_GPCCTRL 0x00000054
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#define SPIDER_NET_GRXMDSET 0x00000058
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#define SPIDER_NET_GIPSECINIT 0x0000005c
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#define SPIDER_NET_GFTRESTRT 0x00000060
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#define SPIDER_NET_GRXDMAEN 0x00000064
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#define SPIDER_NET_GMRWOLCTRL 0x00000068
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#define SPIDER_NET_GPCWOPCMD 0x0000006c
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#define SPIDER_NET_GPCROPCMD 0x00000070
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#define SPIDER_NET_GTTFRMCNT 0x00000078
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#define SPIDER_NET_GTESTMD 0x0000007c
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#define SPIDER_NET_GSINIT 0x00000080
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#define SPIDER_NET_GSnPRGADR 0x00000084
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#define SPIDER_NET_GSnPRGDAT 0x00000088
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#define SPIDER_NET_GMACOPEMD 0x00000100
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#define SPIDER_NET_GMACLENLMT 0x00000108
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2007-02-20 22:33:41 +00:00
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#define SPIDER_NET_GMACST 0x00000110
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2005-09-05 22:19:29 +00:00
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#define SPIDER_NET_GMACINTEN 0x00000118
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#define SPIDER_NET_GMACPHYCTRL 0x00000120
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#define SPIDER_NET_GMACAPAUSE 0x00000154
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#define SPIDER_NET_GMACTXPAUSE 0x00000164
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#define SPIDER_NET_GMACMODE 0x000001b0
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#define SPIDER_NET_GMACBSTLMT 0x000001b4
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#define SPIDER_NET_GMACUNIMACU 0x000001c0
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#define SPIDER_NET_GMACUNIMACL 0x000001c8
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#define SPIDER_NET_GMRMHFILnR 0x00000400
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#define SPIDER_NET_MULTICAST_HASHES 256
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#define SPIDER_NET_GMRUAFILnR 0x00000500
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#define SPIDER_NET_GMRUA0FIL15R 0x00000578
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2006-05-04 09:59:56 +00:00
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#define SPIDER_NET_GTTQMSK 0x00000934
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2005-09-05 22:19:29 +00:00
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/* RX DMA controller registers, all 0x00000a.. are for DMA controller A,
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* 0x00000b.. for DMA controller B, etc. */
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#define SPIDER_NET_GDADCHA 0x00000a00
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#define SPIDER_NET_GDADMACCNTR 0x00000a04
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#define SPIDER_NET_GDACTDPA 0x00000a08
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#define SPIDER_NET_GDACTDCNT 0x00000a0c
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#define SPIDER_NET_GDACDBADDR 0x00000a20
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#define SPIDER_NET_GDACDBSIZE 0x00000a24
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#define SPIDER_NET_GDACNEXTDA 0x00000a28
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#define SPIDER_NET_GDACCOMST 0x00000a2c
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#define SPIDER_NET_GDAWBCOMST 0x00000a30
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#define SPIDER_NET_GDAWBRSIZE 0x00000a34
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#define SPIDER_NET_GDAWBVSIZE 0x00000a38
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#define SPIDER_NET_GDAWBTRST 0x00000a3c
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#define SPIDER_NET_GDAWBTRERR 0x00000a40
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/* TX DMA controller registers */
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#define SPIDER_NET_GDTDCHA 0x00000e00
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#define SPIDER_NET_GDTDMACCNTR 0x00000e04
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#define SPIDER_NET_GDTCDPA 0x00000e08
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#define SPIDER_NET_GDTDMASEL 0x00000e14
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#define SPIDER_NET_ECMODE 0x00000f00
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/* clock and reset control register */
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#define SPIDER_NET_CKRCTRL 0x00000ff0
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/** SCONFIG registers */
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#define SPIDER_NET_SCONFIG_IOACTE 0x00002810
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2006-01-12 22:16:44 +00:00
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/** interrupt mask registers */
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#define SPIDER_NET_INT0_MASK_VALUE 0x3f7fe2c7
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#define SPIDER_NET_INT1_MASK_VALUE 0xffff7ff7
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2005-09-05 22:19:29 +00:00
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/* no MAC aborts -> auto retransmission */
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2006-01-12 22:16:44 +00:00
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#define SPIDER_NET_INT2_MASK_VALUE 0xffef7ff1
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2005-09-05 22:19:29 +00:00
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/* we rely on flagged descriptor interrupts */
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#define SPIDER_NET_FRAMENUM_VALUE 0x00000000
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/* set this first, then the FRAMENUM_VALUE */
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#define SPIDER_NET_GFXFRAMES_VALUE 0x00000000
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#define SPIDER_NET_STOP_SEQ_VALUE 0x00000000
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#define SPIDER_NET_RUN_SEQ_VALUE 0x0000007e
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#define SPIDER_NET_PHY_CTRL_VALUE 0x00040040
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/* #define SPIDER_NET_PHY_CTRL_VALUE 0x01070080*/
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#define SPIDER_NET_RXMODE_VALUE 0x00000011
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/* auto retransmission in case of MAC aborts */
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#define SPIDER_NET_TXMODE_VALUE 0x00010000
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#define SPIDER_NET_RESTART_VALUE 0x00000000
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#define SPIDER_NET_WOL_VALUE 0x00001111
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#if 0
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#define SPIDER_NET_WOL_VALUE 0x00000000
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#endif
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2006-01-12 22:16:44 +00:00
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#define SPIDER_NET_IPSECINIT_VALUE 0x6f716f71
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2005-09-05 22:19:29 +00:00
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/* pause frames: automatic, no upper retransmission count */
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/* outside loopback mode: ETOMOD signal dont matter, not connected */
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2007-02-20 22:36:14 +00:00
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/* ETOMOD signal is brought to PHY reset. bit 2 must be 1 in Celleb */
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#define SPIDER_NET_OPMODE_VALUE 0x00000067
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2005-09-05 22:19:29 +00:00
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/*#define SPIDER_NET_OPMODE_VALUE 0x001b0062*/
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#define SPIDER_NET_LENLMT_VALUE 0x00000908
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#define SPIDER_NET_MACAPAUSE_VALUE 0x00000800 /* about 1 ms */
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#define SPIDER_NET_TXPAUSE_VALUE 0x00000000
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#define SPIDER_NET_MACMODE_VALUE 0x00000001
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#define SPIDER_NET_BURSTLMT_VALUE 0x00000200 /* about 16 us */
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2006-10-10 21:02:54 +00:00
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/* DMAC control register GDMACCNTR
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*
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* 1(0) enable r/tx dma
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2005-09-05 22:19:29 +00:00
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* 0000000 fixed to 0
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*
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* 000000 fixed to 0
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* 0(1) en/disable descr writeback on force end
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* 0(1) force end
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*
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* 000000 fixed to 0
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* 00 burst alignment: 128 bytes
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2006-10-10 21:02:54 +00:00
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* 11 burst alignment: 1024 bytes
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2005-09-05 22:19:29 +00:00
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*
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* 00000 fixed to 0
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* 0 descr writeback size 32 bytes
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* 0(1) descr chain end interrupt enable
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* 0(1) descr status writeback enable */
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|
|
|
|
|
|
|
|
|
/* to set RX_DMA_EN */
|
|
|
|
|
#define SPIDER_NET_DMA_RX_VALUE 0x80000000
|
|
|
|
|
#define SPIDER_NET_DMA_RX_FEND_VALUE 0x00030003
|
|
|
|
|
/* to set TX_DMA_EN */
|
2006-10-10 21:02:54 +00:00
|
|
|
#define SPIDER_NET_TX_DMA_EN 0x80000000
|
|
|
|
|
#define SPIDER_NET_GDTBSTA 0x00000300
|
|
|
|
|
#define SPIDER_NET_GDTDCEIDIS 0x00000002
|
|
|
|
|
#define SPIDER_NET_DMA_TX_VALUE SPIDER_NET_TX_DMA_EN | \
|
2007-06-11 18:29:03 +00:00
|
|
|
SPIDER_NET_GDTDCEIDIS | \
|
2006-11-17 22:39:40 +00:00
|
|
|
SPIDER_NET_GDTBSTA
|
2006-10-10 21:02:54 +00:00
|
|
|
|
2005-09-05 22:19:29 +00:00
|
|
|
#define SPIDER_NET_DMA_TX_FEND_VALUE 0x00030003
|
|
|
|
|
|
|
|
|
|
/* SPIDER_NET_UA_DESCR_VALUE is OR'ed with the unicast address */
|
|
|
|
|
#define SPIDER_NET_UA_DESCR_VALUE 0x00080000
|
|
|
|
|
#define SPIDER_NET_PROMISC_VALUE 0x00080000
|
|
|
|
|
#define SPIDER_NET_NONPROMISC_VALUE 0x00000000
|
|
|
|
|
|
|
|
|
|
#define SPIDER_NET_DMASEL_VALUE 0x00000001
|
|
|
|
|
|
|
|
|
|
#define SPIDER_NET_ECMODE_VALUE 0x00000000
|
|
|
|
|
|
|
|
|
|
#define SPIDER_NET_CKRCTRL_RUN_VALUE 0x1fff010f
|
|
|
|
|
#define SPIDER_NET_CKRCTRL_STOP_VALUE 0x0000010f
|
|
|
|
|
|
|
|
|
|
#define SPIDER_NET_SBIMSTATE_VALUE 0x00000000
|
|
|
|
|
#define SPIDER_NET_SBTMSTATE_VALUE 0x00000000
|
|
|
|
|
|
|
|
|
|
/* SPIDER_NET_GHIINT0STS bits, in reverse order so that they can be used
|
|
|
|
|
* with 1 << SPIDER_NET_... */
|
|
|
|
|
enum spider_net_int0_status {
|
|
|
|
|
SPIDER_NET_GPHYINT = 0,
|
|
|
|
|
SPIDER_NET_GMAC2INT,
|
|
|
|
|
SPIDER_NET_GMAC1INT,
|
|
|
|
|
SPIDER_NET_GIPSINT,
|
|
|
|
|
SPIDER_NET_GFIFOINT,
|
|
|
|
|
SPIDER_NET_GDMACINT,
|
|
|
|
|
SPIDER_NET_GSYSINT,
|
|
|
|
|
SPIDER_NET_GPWOPCMPINT,
|
|
|
|
|
SPIDER_NET_GPROPCMPINT,
|
|
|
|
|
SPIDER_NET_GPWFFINT,
|
|
|
|
|
SPIDER_NET_GRMDADRINT,
|
|
|
|
|
SPIDER_NET_GRMARPINT,
|
|
|
|
|
SPIDER_NET_GRMMPINT,
|
|
|
|
|
SPIDER_NET_GDTDEN0INT,
|
|
|
|
|
SPIDER_NET_GDDDEN0INT,
|
|
|
|
|
SPIDER_NET_GDCDEN0INT,
|
|
|
|
|
SPIDER_NET_GDBDEN0INT,
|
|
|
|
|
SPIDER_NET_GDADEN0INT,
|
|
|
|
|
SPIDER_NET_GDTFDCINT,
|
|
|
|
|
SPIDER_NET_GDDFDCINT,
|
|
|
|
|
SPIDER_NET_GDCFDCINT,
|
|
|
|
|
SPIDER_NET_GDBFDCINT,
|
|
|
|
|
SPIDER_NET_GDAFDCINT,
|
|
|
|
|
SPIDER_NET_GTTEDINT,
|
|
|
|
|
SPIDER_NET_GDTDCEINT,
|
|
|
|
|
SPIDER_NET_GRFDNMINT,
|
|
|
|
|
SPIDER_NET_GRFCNMINT,
|
|
|
|
|
SPIDER_NET_GRFBNMINT,
|
|
|
|
|
SPIDER_NET_GRFANMINT,
|
|
|
|
|
SPIDER_NET_GRFNMINT,
|
|
|
|
|
SPIDER_NET_G1TMCNTINT,
|
|
|
|
|
SPIDER_NET_GFREECNTINT
|
|
|
|
|
};
|
|
|
|
|
/* GHIINT1STS bits */
|
|
|
|
|
enum spider_net_int1_status {
|
|
|
|
|
SPIDER_NET_GTMFLLINT = 0,
|
|
|
|
|
SPIDER_NET_GRMFLLINT,
|
|
|
|
|
SPIDER_NET_GTMSHTINT,
|
|
|
|
|
SPIDER_NET_GDTINVDINT,
|
|
|
|
|
SPIDER_NET_GRFDFLLINT,
|
|
|
|
|
SPIDER_NET_GDDDCEINT,
|
|
|
|
|
SPIDER_NET_GDDINVDINT,
|
|
|
|
|
SPIDER_NET_GRFCFLLINT,
|
|
|
|
|
SPIDER_NET_GDCDCEINT,
|
|
|
|
|
SPIDER_NET_GDCINVDINT,
|
|
|
|
|
SPIDER_NET_GRFBFLLINT,
|
|
|
|
|
SPIDER_NET_GDBDCEINT,
|
|
|
|
|
SPIDER_NET_GDBINVDINT,
|
|
|
|
|
SPIDER_NET_GRFAFLLINT,
|
|
|
|
|
SPIDER_NET_GDADCEINT,
|
|
|
|
|
SPIDER_NET_GDAINVDINT,
|
|
|
|
|
SPIDER_NET_GDTRSERINT,
|
|
|
|
|
SPIDER_NET_GDDRSERINT,
|
|
|
|
|
SPIDER_NET_GDCRSERINT,
|
|
|
|
|
SPIDER_NET_GDBRSERINT,
|
|
|
|
|
SPIDER_NET_GDARSERINT,
|
|
|
|
|
SPIDER_NET_GDSERINT,
|
|
|
|
|
SPIDER_NET_GDTPTERINT,
|
|
|
|
|
SPIDER_NET_GDDPTERINT,
|
|
|
|
|
SPIDER_NET_GDCPTERINT,
|
|
|
|
|
SPIDER_NET_GDBPTERINT,
|
|
|
|
|
SPIDER_NET_GDAPTERINT
|
|
|
|
|
};
|
|
|
|
|
/* GHIINT2STS bits */
|
|
|
|
|
enum spider_net_int2_status {
|
|
|
|
|
SPIDER_NET_GPROPERINT = 0,
|
|
|
|
|
SPIDER_NET_GMCTCRSNGINT,
|
|
|
|
|
SPIDER_NET_GMCTLCOLINT,
|
|
|
|
|
SPIDER_NET_GMCTTMOTINT,
|
|
|
|
|
SPIDER_NET_GMCRCAERINT,
|
|
|
|
|
SPIDER_NET_GMCRCALERINT,
|
|
|
|
|
SPIDER_NET_GMCRALNERINT,
|
|
|
|
|
SPIDER_NET_GMCROVRINT,
|
|
|
|
|
SPIDER_NET_GMCRRNTINT,
|
|
|
|
|
SPIDER_NET_GMCRRXERINT,
|
|
|
|
|
SPIDER_NET_GTITCSERINT,
|
|
|
|
|
SPIDER_NET_GTIFMTERINT,
|
|
|
|
|
SPIDER_NET_GTIPKTRVKINT,
|
|
|
|
|
SPIDER_NET_GTISPINGINT,
|
|
|
|
|
SPIDER_NET_GTISADNGINT,
|
|
|
|
|
SPIDER_NET_GTISPDNGINT,
|
|
|
|
|
SPIDER_NET_GRIFMTERINT,
|
|
|
|
|
SPIDER_NET_GRIPKTRVKINT,
|
|
|
|
|
SPIDER_NET_GRISPINGINT,
|
|
|
|
|
SPIDER_NET_GRISADNGINT,
|
|
|
|
|
SPIDER_NET_GRISPDNGINT
|
|
|
|
|
};
|
|
|
|
|
|
2007-06-11 18:29:03 +00:00
|
|
|
#define SPIDER_NET_TXINT (1 << SPIDER_NET_GDTFDCINT)
|
2005-09-05 22:19:29 +00:00
|
|
|
|
2006-10-10 21:05:00 +00:00
|
|
|
/* We rely on flagged descriptor interrupts */
|
|
|
|
|
#define SPIDER_NET_RXINT ( (1 << SPIDER_NET_GDAFDCINT) )
|
2005-09-05 22:19:29 +00:00
|
|
|
|
2007-02-20 22:33:41 +00:00
|
|
|
#define SPIDER_NET_LINKINT ( 1 << SPIDER_NET_GMAC2INT )
|
|
|
|
|
|
2006-01-12 22:16:44 +00:00
|
|
|
#define SPIDER_NET_ERRINT ( 0xffffffff & \
|
|
|
|
|
(~SPIDER_NET_TXINT) & \
|
2007-02-20 22:33:41 +00:00
|
|
|
(~SPIDER_NET_RXINT) & \
|
|
|
|
|
(~SPIDER_NET_LINKINT) )
|
2006-01-12 22:16:44 +00:00
|
|
|
|
2006-07-13 09:54:08 +00:00
|
|
|
#define SPIDER_NET_GPREXEC 0x80000000
|
|
|
|
|
#define SPIDER_NET_GPRDAT_MASK 0x0000ffff
|
2005-09-05 22:19:29 +00:00
|
|
|
|
2006-07-13 09:54:08 +00:00
|
|
|
#define SPIDER_NET_DMAC_NOINTR_COMPLETE 0x00800000
|
2007-06-11 19:09:16 +00:00
|
|
|
#define SPIDER_NET_DMAC_TXFRMTL 0x00040000
|
2006-07-13 09:54:08 +00:00
|
|
|
#define SPIDER_NET_DMAC_TCP 0x00020000
|
|
|
|
|
#define SPIDER_NET_DMAC_UDP 0x00030000
|
|
|
|
|
#define SPIDER_NET_TXDCEST 0x08000000
|
|
|
|
|
|
2007-06-14 23:12:23 +00:00
|
|
|
#define SPIDER_NET_DESCR_RXFDIS 0x00000001
|
|
|
|
|
#define SPIDER_NET_DESCR_RXDCEIS 0x00000002
|
|
|
|
|
#define SPIDER_NET_DESCR_RXDEN0IS 0x00000004
|
|
|
|
|
#define SPIDER_NET_DESCR_RXINVDIS 0x00000008
|
|
|
|
|
#define SPIDER_NET_DESCR_RXRERRIS 0x00000010
|
|
|
|
|
#define SPIDER_NET_DESCR_RXFDCIMS 0x00000100
|
|
|
|
|
#define SPIDER_NET_DESCR_RXDCEIMS 0x00000200
|
|
|
|
|
#define SPIDER_NET_DESCR_RXDEN0IMS 0x00000400
|
|
|
|
|
#define SPIDER_NET_DESCR_RXINVDIMS 0x00000800
|
|
|
|
|
#define SPIDER_NET_DESCR_RXRERRMIS 0x00001000
|
|
|
|
|
#define SPIDER_NET_DESCR_UNUSED 0x077fe0e0
|
|
|
|
|
|
2006-07-13 09:54:08 +00:00
|
|
|
#define SPIDER_NET_DESCR_IND_PROC_MASK 0xF0000000
|
|
|
|
|
#define SPIDER_NET_DESCR_COMPLETE 0x00000000 /* used in rx and tx */
|
|
|
|
|
#define SPIDER_NET_DESCR_RESPONSE_ERROR 0x10000000 /* used in rx and tx */
|
|
|
|
|
#define SPIDER_NET_DESCR_PROTECTION_ERROR 0x20000000 /* used in rx and tx */
|
|
|
|
|
#define SPIDER_NET_DESCR_FRAME_END 0x40000000 /* used in rx */
|
|
|
|
|
#define SPIDER_NET_DESCR_FORCE_END 0x50000000 /* used in rx and tx */
|
|
|
|
|
#define SPIDER_NET_DESCR_CARDOWNED 0xA0000000 /* used in rx and tx */
|
|
|
|
|
#define SPIDER_NET_DESCR_NOT_IN_USE 0xF0000000
|
[PATCH] powerpc/cell spidernet low watermark patch.
Implement basic low-watermark support for the transmit queue.
Hardware low-watermarks allow a properly configured kernel
to continously stream data to a device and not have to handle
any interrupts at all in doing so. Correct zero-interrupt
operation can be actually observed for this driver, when the
socket buffer is made large enough.
The basic idea of a low-watermark interrupt is as follows.
The device driver queues up a bunch of packets for the hardware
to transmit, and then kicks the hardware to get it started.
As the hardware drains the queue of pending, untransmitted
packets, the device driver will want to know when the queue
is almost empty, so that it can queue some more packets.
If the queue drains down to the low waterark, then an interrupt
will be generated. However, if the kernel/driver continues
to add enough packets to keep the queue partially filled,
no interrupt will actually be generated, and the hardware
can continue streaming packets indefinitely in this mode.
The impelmentation is done by setting the DESCR_TXDESFLG flag
in one of the packets. When the hardware sees this flag, it will
interrupt the device driver. Because this flag is on a fixed
packet, rather than at fixed location in the queue, the
code below needs to move the flag as more packets are
queued up. This implementation attempts to keep the flag
at about 1/4 from "empty".
Signed-off-by: Linas Vepstas <linas@austin.ibm.com>
Signed-off-by: James K Lewis <jklewis@us.ibm.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2006-10-10 21:11:33 +00:00
|
|
|
#define SPIDER_NET_DESCR_TXDESFLG 0x00800000
|
2005-09-05 22:19:29 +00:00
|
|
|
|
2007-06-14 23:12:23 +00:00
|
|
|
#define SPIDER_NET_DESCR_BAD_STATUS (SPIDER_NET_DESCR_RXDEN0IS | \
|
|
|
|
|
SPIDER_NET_DESCR_RXRERRIS | \
|
|
|
|
|
SPIDER_NET_DESCR_RXDEN0IMS | \
|
|
|
|
|
SPIDER_NET_DESCR_RXINVDIMS | \
|
|
|
|
|
SPIDER_NET_DESCR_RXRERRMIS | \
|
|
|
|
|
SPIDER_NET_DESCR_UNUSED)
|
|
|
|
|
|
2007-02-20 22:40:06 +00:00
|
|
|
/* Descriptor, as defined by the hardware */
|
|
|
|
|
struct spider_net_hw_descr {
|
2006-01-12 22:16:43 +00:00
|
|
|
u32 buf_addr;
|
2005-09-05 22:19:29 +00:00
|
|
|
u32 buf_size;
|
2006-01-12 22:16:43 +00:00
|
|
|
u32 next_descr_addr;
|
2005-09-05 22:19:29 +00:00
|
|
|
u32 dmac_cmd_status;
|
|
|
|
|
u32 result_size;
|
|
|
|
|
u32 valid_size; /* all zeroes for tx */
|
|
|
|
|
u32 data_status;
|
|
|
|
|
u32 data_error; /* all zeroes for tx */
|
2007-02-20 22:40:06 +00:00
|
|
|
} __attribute__((aligned(32)));
|
2005-09-05 22:19:29 +00:00
|
|
|
|
2007-02-20 22:40:06 +00:00
|
|
|
struct spider_net_descr {
|
|
|
|
|
struct spider_net_hw_descr *hwdescr;
|
2005-09-05 22:19:29 +00:00
|
|
|
struct sk_buff *skb;
|
2006-01-12 22:16:44 +00:00
|
|
|
u32 bus_addr;
|
2005-09-05 22:19:29 +00:00
|
|
|
struct spider_net_descr *next;
|
|
|
|
|
struct spider_net_descr *prev;
|
2007-02-20 22:40:06 +00:00
|
|
|
};
|
2005-09-05 22:19:29 +00:00
|
|
|
|
|
|
|
|
struct spider_net_descr_chain {
|
2006-07-13 09:54:08 +00:00
|
|
|
spinlock_t lock;
|
2005-09-05 22:19:29 +00:00
|
|
|
struct spider_net_descr *head;
|
|
|
|
|
struct spider_net_descr *tail;
|
2006-12-13 21:06:59 +00:00
|
|
|
struct spider_net_descr *ring;
|
|
|
|
|
int num_desc;
|
2007-02-20 22:40:06 +00:00
|
|
|
struct spider_net_hw_descr *hwring;
|
2006-12-13 21:06:59 +00:00
|
|
|
dma_addr_t dma_addr;
|
2005-09-05 22:19:29 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
/* descriptor data_status bits */
|
2006-01-12 22:16:44 +00:00
|
|
|
#define SPIDER_NET_RX_IPCHK 29
|
|
|
|
|
#define SPIDER_NET_RX_TCPCHK 28
|
2005-09-05 22:19:29 +00:00
|
|
|
#define SPIDER_NET_VLAN_PACKET 21
|
2006-01-12 22:16:44 +00:00
|
|
|
#define SPIDER_NET_DATA_STATUS_CKSUM_MASK ( (1 << SPIDER_NET_RX_IPCHK) | \
|
|
|
|
|
(1 << SPIDER_NET_RX_TCPCHK) )
|
2005-09-05 22:19:29 +00:00
|
|
|
|
|
|
|
|
/* descriptor data_error bits */
|
2006-01-12 22:16:44 +00:00
|
|
|
#define SPIDER_NET_RX_IPCHKERR 27
|
|
|
|
|
#define SPIDER_NET_RX_RXTCPCHKERR 28
|
|
|
|
|
|
|
|
|
|
#define SPIDER_NET_DATA_ERR_CKSUM_MASK (1 << SPIDER_NET_RX_IPCHKERR)
|
2005-09-05 22:19:29 +00:00
|
|
|
|
2006-01-12 22:16:44 +00:00
|
|
|
/* the cases we don't pass the packet to the stack.
|
|
|
|
|
* 701b8000 would be correct, but every packets gets that flag */
|
|
|
|
|
#define SPIDER_NET_DESTROY_RX_FLAGS 0x700b8000
|
2005-09-05 22:19:29 +00:00
|
|
|
|
|
|
|
|
/* this will be bigger some time */
|
|
|
|
|
struct spider_net_options {
|
|
|
|
|
int rx_csum; /* for rx: if 0 ip_summed=NONE,
|
|
|
|
|
if 1 and hw has verified, ip_summed=UNNECESSARY */
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
#define SPIDER_NET_DEFAULT_MSG ( NETIF_MSG_DRV | \
|
|
|
|
|
NETIF_MSG_PROBE | \
|
|
|
|
|
NETIF_MSG_LINK | \
|
|
|
|
|
NETIF_MSG_TIMER | \
|
|
|
|
|
NETIF_MSG_IFDOWN | \
|
|
|
|
|
NETIF_MSG_IFUP | \
|
|
|
|
|
NETIF_MSG_RX_ERR | \
|
|
|
|
|
NETIF_MSG_TX_ERR | \
|
|
|
|
|
NETIF_MSG_TX_QUEUED | \
|
|
|
|
|
NETIF_MSG_INTR | \
|
|
|
|
|
NETIF_MSG_TX_DONE | \
|
|
|
|
|
NETIF_MSG_RX_STATUS | \
|
|
|
|
|
NETIF_MSG_PKTDATA | \
|
|
|
|
|
NETIF_MSG_HW | \
|
|
|
|
|
NETIF_MSG_WOL )
|
|
|
|
|
|
2006-09-23 00:22:53 +00:00
|
|
|
struct spider_net_extra_stats {
|
|
|
|
|
unsigned long rx_desc_error;
|
|
|
|
|
unsigned long tx_timeouts;
|
|
|
|
|
unsigned long alloc_rx_skb_error;
|
|
|
|
|
unsigned long rx_iommu_map_error;
|
|
|
|
|
unsigned long tx_iommu_map_error;
|
|
|
|
|
unsigned long rx_desc_unk_state;
|
|
|
|
|
};
|
|
|
|
|
|
2005-09-05 22:19:29 +00:00
|
|
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struct spider_net_card {
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struct net_device *netdev;
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struct pci_dev *pdev;
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struct mii_phy phy;
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2007-02-20 22:39:13 +00:00
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int medium;
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2005-09-05 22:19:29 +00:00
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void __iomem *regs;
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struct spider_net_descr_chain tx_chain;
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struct spider_net_descr_chain rx_chain;
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[PATCH] powerpc/cell spidernet low watermark patch.
Implement basic low-watermark support for the transmit queue.
Hardware low-watermarks allow a properly configured kernel
to continously stream data to a device and not have to handle
any interrupts at all in doing so. Correct zero-interrupt
operation can be actually observed for this driver, when the
socket buffer is made large enough.
The basic idea of a low-watermark interrupt is as follows.
The device driver queues up a bunch of packets for the hardware
to transmit, and then kicks the hardware to get it started.
As the hardware drains the queue of pending, untransmitted
packets, the device driver will want to know when the queue
is almost empty, so that it can queue some more packets.
If the queue drains down to the low waterark, then an interrupt
will be generated. However, if the kernel/driver continues
to add enough packets to keep the queue partially filled,
no interrupt will actually be generated, and the hardware
can continue streaming packets indefinitely in this mode.
The impelmentation is done by setting the DESCR_TXDESFLG flag
in one of the packets. When the hardware sees this flag, it will
interrupt the device driver. Because this flag is on a fixed
packet, rather than at fixed location in the queue, the
code below needs to move the flag as more packets are
queued up. This implementation attempts to keep the flag
at about 1/4 from "empty".
Signed-off-by: Linas Vepstas <linas@austin.ibm.com>
Signed-off-by: James K Lewis <jklewis@us.ibm.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2006-10-10 21:11:33 +00:00
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struct spider_net_descr *low_watermark;
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2005-09-05 22:19:29 +00:00
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2007-02-20 22:33:41 +00:00
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int aneg_count;
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struct timer_list aneg_timer;
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2006-01-12 22:16:44 +00:00
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struct timer_list tx_timer;
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2005-09-05 22:19:29 +00:00
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struct work_struct tx_timeout_task;
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atomic_t tx_timeout_task_counter;
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wait_queue_head_t waitq;
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spidernet: Cure RX ram full bug
This patch fixes a rare deadlock that can occur when the kernel
is not able to empty out the RX ring quickly enough. Below follows
a detailed description of the bug and the fix.
As long as the OS can empty out the RX buffers at a rate faster than
the hardware can fill them, there is no problem. If, for some reason,
the OS fails to empty the RX ring fast enough, the hardware GDACTDPA
pointer will catch up to the head, notice the not-empty condition,
ad stop. However, RX packets may still continue arriving on the wire.
The spidernet chip can save some limited number of these in local RAM.
When this local ram fills up, the spider chip will issue an interrupt
indicating this (GHIINT0STS will show ERRINT, and the GRMFLLINT bit
will be set in GHIINT1STS). When te RX ram full condition occurs,
a certain bug/feature is triggered that has to be specially handled.
This section describes the special handling for this condition.
When the OS finally has a chance to run, it will empty out the RX ring.
In particular, it will clear the descriptor on which the hardware had
stopped. However, once the hardware has decided that a certain
descriptor is invalid, it will not restart at that descriptor; instead
it will restart at the next descr. This potentially will lead to a
deadlock condition, as the tail pointer will be pointing at this descr,
which, from the OS point of view, is empty; the OS will be waiting for
this descr to be filled. However, the hardware has skipped this descr,
and is filling the next descrs. Since the OS doesn't see this, there
is a potential deadlock, with the OS waiting for one descr to fill,
while the hardware is waiting for a differen set of descrs to become
empty.
A call to show_rx_chain() at this point indicates the nature of the
problem. A typical print when the network is hung shows the following:
net eth1: Spider RX RAM full, incoming packets might be discarded!
net eth1: Total number of descrs=256
net eth1: Chain tail located at descr=255
net eth1: Chain head is at 255
net eth1: HW curr desc (GDACTDPA) is at 0
net eth1: Have 1 descrs with stat=xa0800000
net eth1: HW next desc (GDACNEXTDA) is at 1
net eth1: Have 127 descrs with stat=x40800101
net eth1: Have 1 descrs with stat=x40800001
net eth1: Have 126 descrs with stat=x40800101
net eth1: Last 1 descrs with stat=xa0800000
Both the tail and head pointers are pointing at descr 255, which is
marked xa... which is "empty". Thus, from the OS point of view, there
is nothing to be done. In particular, there is the implicit assumption
that everything in front of the "empty" descr must surely also be empty,
as explained in the last section. The OS is waiting for descr 255 to
become non-empty, which, in this case, will never happen.
The HW pointer is at descr 0. This descr is marked 0x4.. or "full".
Since its already full, the hardware can do nothing more, and thus has
halted processing. Notice that descrs 0 through 254 are all marked
"full", while descr 254 and 255 are empty. (The "Last 1 descrs" is
descr 254, since tail was at 255.) Thus, the system is deadlocked,
and there can be no forward progress; the OS thinks there's nothing
to do, and the hardware has nowhere to put incoming data.
This bug/feature is worked around with the spider_net_resync_head_ptr()
routine. When the driver receives RX interrupts, but an examination
of the RX chain seems to show it is empty, then it is probable that
the hardware has skipped a descr or two (sometimes dozens under heavy
network conditions). The spider_net_resync_head_ptr() subroutine will
search the ring for the next full descr, and the driver will resume
operations there. Since this will leave "holes" in the ring, there
is also a spider_net_resync_tail_ptr() that will skip over such holes.
Signed-off-by: Linas Vepstas <linas@austin.ibm.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-06-11 18:21:13 +00:00
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int num_rx_ints;
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2007-06-11 18:26:50 +00:00
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int ignore_rx_ramfull;
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2005-09-05 22:19:29 +00:00
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/* for ethtool */
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int msg_enable;
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2006-12-13 21:06:59 +00:00
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struct net_device_stats netdev_stats;
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2006-09-23 00:22:53 +00:00
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struct spider_net_extra_stats spider_stats;
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2006-12-13 21:06:59 +00:00
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struct spider_net_options options;
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2007-02-20 22:40:06 +00:00
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/* Must be last item in struct */
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struct spider_net_descr darray[0];
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2005-09-05 22:19:29 +00:00
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};
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#define pr_err(fmt,arg...) \
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printk(KERN_ERR fmt ,##arg)
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#endif
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