2019-05-28 17:10:04 +00:00
|
|
|
// SPDX-License-Identifier: GPL-2.0-only
|
2014-05-20 02:18:27 +00:00
|
|
|
/*
|
|
|
|
*
|
|
|
|
* Implementation of primary ALSA driver code base for NVIDIA Tegra HDA.
|
|
|
|
*/
|
|
|
|
|
|
|
|
#include <linux/clk.h>
|
|
|
|
#include <linux/clocksource.h>
|
|
|
|
#include <linux/completion.h>
|
|
|
|
#include <linux/delay.h>
|
|
|
|
#include <linux/dma-mapping.h>
|
|
|
|
#include <linux/init.h>
|
|
|
|
#include <linux/interrupt.h>
|
|
|
|
#include <linux/io.h>
|
|
|
|
#include <linux/kernel.h>
|
|
|
|
#include <linux/module.h>
|
|
|
|
#include <linux/moduleparam.h>
|
|
|
|
#include <linux/mutex.h>
|
|
|
|
#include <linux/of_device.h>
|
2021-01-20 00:31:50 +00:00
|
|
|
#include <linux/reset.h>
|
2014-05-20 02:18:27 +00:00
|
|
|
#include <linux/slab.h>
|
|
|
|
#include <linux/time.h>
|
2018-11-29 03:58:52 +00:00
|
|
|
#include <linux/string.h>
|
2019-01-22 07:33:16 +00:00
|
|
|
#include <linux/pm_runtime.h>
|
2014-05-20 02:18:27 +00:00
|
|
|
|
|
|
|
#include <sound/core.h>
|
|
|
|
#include <sound/initval.h>
|
|
|
|
|
2018-08-22 20:24:57 +00:00
|
|
|
#include <sound/hda_codec.h>
|
2014-05-20 02:18:27 +00:00
|
|
|
#include "hda_controller.h"
|
|
|
|
|
|
|
|
/* Defines for Nvidia Tegra HDA support */
|
|
|
|
#define HDA_BAR0 0x8000
|
|
|
|
|
|
|
|
#define HDA_CFG_CMD 0x1004
|
|
|
|
#define HDA_CFG_BAR0 0x1010
|
|
|
|
|
|
|
|
#define HDA_ENABLE_IO_SPACE (1 << 0)
|
|
|
|
#define HDA_ENABLE_MEM_SPACE (1 << 1)
|
|
|
|
#define HDA_ENABLE_BUS_MASTER (1 << 2)
|
|
|
|
#define HDA_ENABLE_SERR (1 << 8)
|
|
|
|
#define HDA_DISABLE_INTR (1 << 10)
|
|
|
|
#define HDA_BAR0_INIT_PROGRAM 0xFFFFFFFF
|
|
|
|
#define HDA_BAR0_FINAL_PROGRAM (1 << 14)
|
|
|
|
|
|
|
|
/* IPFS */
|
|
|
|
#define HDA_IPFS_CONFIG 0x180
|
|
|
|
#define HDA_IPFS_EN_FPCI 0x1
|
|
|
|
|
|
|
|
#define HDA_IPFS_FPCI_BAR0 0x80
|
|
|
|
#define HDA_FPCI_BAR0_START 0x40
|
|
|
|
|
|
|
|
#define HDA_IPFS_INTR_MASK 0x188
|
|
|
|
#define HDA_IPFS_EN_INTR (1 << 16)
|
|
|
|
|
2020-05-04 08:16:14 +00:00
|
|
|
/* FPCI */
|
|
|
|
#define FPCI_DBG_CFG_2 0x10F4
|
|
|
|
#define FPCI_GCAP_NSDO_SHIFT 18
|
|
|
|
#define FPCI_GCAP_NSDO_MASK (0x3 << FPCI_GCAP_NSDO_SHIFT)
|
|
|
|
|
2014-05-20 02:18:27 +00:00
|
|
|
/* max number of SDs */
|
|
|
|
#define NUM_CAPTURE_SD 1
|
|
|
|
#define NUM_PLAYBACK_SD 1
|
|
|
|
|
2020-05-04 08:16:14 +00:00
|
|
|
/*
|
|
|
|
* Tegra194 does not reflect correct number of SDO lines. Below macro
|
|
|
|
* is used to update the GCAP register to workaround the issue.
|
|
|
|
*/
|
|
|
|
#define TEGRA194_NUM_SDO_LINES 4
|
|
|
|
|
2014-05-20 02:18:27 +00:00
|
|
|
struct hda_tegra {
|
|
|
|
struct azx chip;
|
|
|
|
struct device *dev;
|
2021-01-20 00:31:50 +00:00
|
|
|
struct reset_control *reset;
|
2021-01-20 00:31:49 +00:00
|
|
|
struct clk_bulk_data clocks[3];
|
|
|
|
unsigned int nclocks;
|
2014-05-20 02:18:27 +00:00
|
|
|
void __iomem *regs;
|
2015-09-24 09:00:18 +00:00
|
|
|
struct work_struct probe_work;
|
2014-05-20 02:18:27 +00:00
|
|
|
};
|
|
|
|
|
2014-05-26 19:15:20 +00:00
|
|
|
#ifdef CONFIG_PM
|
2014-05-20 02:18:27 +00:00
|
|
|
static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
|
|
|
|
module_param(power_save, bint, 0644);
|
|
|
|
MODULE_PARM_DESC(power_save,
|
|
|
|
"Automatic power-saving timeout (in seconds, 0 = disable).");
|
2014-05-26 19:15:20 +00:00
|
|
|
#else
|
2015-02-20 08:26:04 +00:00
|
|
|
#define power_save 0
|
2014-05-26 19:15:20 +00:00
|
|
|
#endif
|
2014-05-20 02:18:27 +00:00
|
|
|
|
2018-08-08 15:12:58 +00:00
|
|
|
static const struct hda_controller_ops hda_tegra_ops; /* nothing special */
|
2014-05-20 02:18:27 +00:00
|
|
|
|
|
|
|
static void hda_tegra_init(struct hda_tegra *hda)
|
|
|
|
{
|
|
|
|
u32 v;
|
|
|
|
|
|
|
|
/* Enable PCI access */
|
|
|
|
v = readl(hda->regs + HDA_IPFS_CONFIG);
|
|
|
|
v |= HDA_IPFS_EN_FPCI;
|
|
|
|
writel(v, hda->regs + HDA_IPFS_CONFIG);
|
|
|
|
|
|
|
|
/* Enable MEM/IO space and bus master */
|
|
|
|
v = readl(hda->regs + HDA_CFG_CMD);
|
|
|
|
v &= ~HDA_DISABLE_INTR;
|
|
|
|
v |= HDA_ENABLE_MEM_SPACE | HDA_ENABLE_IO_SPACE |
|
|
|
|
HDA_ENABLE_BUS_MASTER | HDA_ENABLE_SERR;
|
|
|
|
writel(v, hda->regs + HDA_CFG_CMD);
|
|
|
|
|
|
|
|
writel(HDA_BAR0_INIT_PROGRAM, hda->regs + HDA_CFG_BAR0);
|
|
|
|
writel(HDA_BAR0_FINAL_PROGRAM, hda->regs + HDA_CFG_BAR0);
|
|
|
|
writel(HDA_FPCI_BAR0_START, hda->regs + HDA_IPFS_FPCI_BAR0);
|
|
|
|
|
|
|
|
v = readl(hda->regs + HDA_IPFS_INTR_MASK);
|
|
|
|
v |= HDA_IPFS_EN_INTR;
|
|
|
|
writel(v, hda->regs + HDA_IPFS_INTR_MASK);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* power management
|
|
|
|
*/
|
2019-03-04 20:33:25 +00:00
|
|
|
static int __maybe_unused hda_tegra_suspend(struct device *dev)
|
2014-05-20 02:18:27 +00:00
|
|
|
{
|
|
|
|
struct snd_card *card = dev_get_drvdata(dev);
|
2019-01-22 07:33:20 +00:00
|
|
|
int rc;
|
2014-05-20 02:18:27 +00:00
|
|
|
|
2019-01-22 07:33:20 +00:00
|
|
|
rc = pm_runtime_force_suspend(dev);
|
|
|
|
if (rc < 0)
|
|
|
|
return rc;
|
2014-05-20 02:18:27 +00:00
|
|
|
snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2019-03-04 20:33:25 +00:00
|
|
|
static int __maybe_unused hda_tegra_resume(struct device *dev)
|
2014-05-20 02:18:27 +00:00
|
|
|
{
|
|
|
|
struct snd_card *card = dev_get_drvdata(dev);
|
2019-01-22 07:33:20 +00:00
|
|
|
int rc;
|
2014-05-20 02:18:27 +00:00
|
|
|
|
2019-01-22 07:33:20 +00:00
|
|
|
rc = pm_runtime_force_resume(dev);
|
|
|
|
if (rc < 0)
|
|
|
|
return rc;
|
2014-05-20 02:18:27 +00:00
|
|
|
snd_power_change_state(card, SNDRV_CTL_POWER_D0);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2019-03-04 20:33:25 +00:00
|
|
|
static int __maybe_unused hda_tegra_runtime_suspend(struct device *dev)
|
2019-01-22 07:33:18 +00:00
|
|
|
{
|
2019-01-22 07:33:20 +00:00
|
|
|
struct snd_card *card = dev_get_drvdata(dev);
|
|
|
|
struct azx *chip = card->private_data;
|
|
|
|
struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
|
|
|
|
|
|
|
|
if (chip && chip->running) {
|
2020-08-25 05:24:15 +00:00
|
|
|
/* enable controller wake up event */
|
|
|
|
azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
|
|
|
|
STATESTS_INT_MASK);
|
|
|
|
|
2019-01-22 07:33:20 +00:00
|
|
|
azx_stop_chip(chip);
|
|
|
|
azx_enter_link_reset(chip);
|
|
|
|
}
|
2021-01-20 00:31:49 +00:00
|
|
|
clk_bulk_disable_unprepare(hda->nclocks, hda->clocks);
|
2019-01-22 07:33:20 +00:00
|
|
|
|
2019-01-22 07:33:18 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2019-03-04 20:33:25 +00:00
|
|
|
static int __maybe_unused hda_tegra_runtime_resume(struct device *dev)
|
2019-01-22 07:33:18 +00:00
|
|
|
{
|
2019-01-22 07:33:20 +00:00
|
|
|
struct snd_card *card = dev_get_drvdata(dev);
|
|
|
|
struct azx *chip = card->private_data;
|
|
|
|
struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
|
|
|
|
int rc;
|
|
|
|
|
2021-01-20 00:31:50 +00:00
|
|
|
if (!chip->running) {
|
|
|
|
rc = reset_control_assert(hda->reset);
|
|
|
|
if (rc)
|
|
|
|
return rc;
|
|
|
|
}
|
|
|
|
|
2021-01-20 00:31:49 +00:00
|
|
|
rc = clk_bulk_prepare_enable(hda->nclocks, hda->clocks);
|
2019-01-22 07:33:20 +00:00
|
|
|
if (rc != 0)
|
|
|
|
return rc;
|
|
|
|
if (chip && chip->running) {
|
|
|
|
hda_tegra_init(hda);
|
|
|
|
azx_init_chip(chip, 1);
|
2020-08-25 05:24:15 +00:00
|
|
|
/* disable controller wake up event*/
|
|
|
|
azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
|
|
|
|
~STATESTS_INT_MASK);
|
2021-01-20 00:31:50 +00:00
|
|
|
} else {
|
|
|
|
usleep_range(10, 100);
|
|
|
|
|
|
|
|
rc = reset_control_deassert(hda->reset);
|
|
|
|
if (rc)
|
|
|
|
return rc;
|
2019-01-22 07:33:20 +00:00
|
|
|
}
|
|
|
|
|
2019-01-22 07:33:18 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2014-05-20 02:18:27 +00:00
|
|
|
static const struct dev_pm_ops hda_tegra_pm = {
|
|
|
|
SET_SYSTEM_SLEEP_PM_OPS(hda_tegra_suspend, hda_tegra_resume)
|
2019-01-22 07:33:18 +00:00
|
|
|
SET_RUNTIME_PM_OPS(hda_tegra_runtime_suspend,
|
|
|
|
hda_tegra_runtime_resume,
|
|
|
|
NULL)
|
2014-05-20 02:18:27 +00:00
|
|
|
};
|
|
|
|
|
2015-04-14 20:13:18 +00:00
|
|
|
static int hda_tegra_dev_disconnect(struct snd_device *device)
|
|
|
|
{
|
|
|
|
struct azx *chip = device->device_data;
|
|
|
|
|
|
|
|
chip->bus.shutdown = 1;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2014-05-20 02:18:27 +00:00
|
|
|
/*
|
|
|
|
* destructor
|
|
|
|
*/
|
|
|
|
static int hda_tegra_dev_free(struct snd_device *device)
|
|
|
|
{
|
|
|
|
struct azx *chip = device->device_data;
|
2015-09-24 09:00:18 +00:00
|
|
|
struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
|
2014-05-20 02:18:27 +00:00
|
|
|
|
2015-09-24 09:00:18 +00:00
|
|
|
cancel_work_sync(&hda->probe_work);
|
2015-04-14 20:13:18 +00:00
|
|
|
if (azx_bus(chip)->chip_init) {
|
2015-04-14 16:13:13 +00:00
|
|
|
azx_stop_all_streams(chip);
|
2014-05-20 02:18:27 +00:00
|
|
|
azx_stop_chip(chip);
|
|
|
|
}
|
|
|
|
|
|
|
|
azx_free_stream_pages(chip);
|
2015-04-14 20:13:18 +00:00
|
|
|
azx_free_streams(chip);
|
2015-04-16 10:02:30 +00:00
|
|
|
snd_hdac_bus_exit(azx_bus(chip));
|
2014-05-20 02:18:27 +00:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int hda_tegra_init_chip(struct azx *chip, struct platform_device *pdev)
|
|
|
|
{
|
|
|
|
struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
|
2015-04-14 20:13:18 +00:00
|
|
|
struct hdac_bus *bus = azx_bus(chip);
|
2014-05-20 02:18:27 +00:00
|
|
|
struct device *dev = hda->dev;
|
|
|
|
struct resource *res;
|
|
|
|
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
|
|
hda->regs = devm_ioremap_resource(dev, res);
|
2015-02-14 02:32:24 +00:00
|
|
|
if (IS_ERR(hda->regs))
|
|
|
|
return PTR_ERR(hda->regs);
|
2014-05-20 02:18:27 +00:00
|
|
|
|
2015-04-14 20:13:18 +00:00
|
|
|
bus->remap_addr = hda->regs + HDA_BAR0;
|
|
|
|
bus->addr = res->start + HDA_BAR0;
|
2014-05-20 02:18:27 +00:00
|
|
|
|
|
|
|
hda_tegra_init(hda);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int hda_tegra_first_init(struct azx *chip, struct platform_device *pdev)
|
|
|
|
{
|
2020-05-04 08:16:14 +00:00
|
|
|
struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
|
2015-04-14 20:13:18 +00:00
|
|
|
struct hdac_bus *bus = azx_bus(chip);
|
2014-05-20 02:18:27 +00:00
|
|
|
struct snd_card *card = chip->card;
|
|
|
|
int err;
|
|
|
|
unsigned short gcap;
|
|
|
|
int irq_id = platform_get_irq(pdev, 0);
|
2019-02-20 15:13:24 +00:00
|
|
|
const char *sname, *drv_name = "tegra-hda";
|
|
|
|
struct device_node *np = pdev->dev.of_node;
|
2014-05-20 02:18:27 +00:00
|
|
|
|
|
|
|
err = hda_tegra_init_chip(chip, pdev);
|
|
|
|
if (err)
|
|
|
|
return err;
|
|
|
|
|
|
|
|
err = devm_request_irq(chip->card->dev, irq_id, azx_interrupt,
|
|
|
|
IRQF_SHARED, KBUILD_MODNAME, chip);
|
|
|
|
if (err) {
|
|
|
|
dev_err(chip->card->dev,
|
|
|
|
"unable to request IRQ %d, disabling device\n",
|
|
|
|
irq_id);
|
|
|
|
return err;
|
|
|
|
}
|
2015-04-14 20:13:18 +00:00
|
|
|
bus->irq = irq_id;
|
2020-08-05 09:52:21 +00:00
|
|
|
bus->dma_stop_delay = 100;
|
2019-12-10 06:34:20 +00:00
|
|
|
card->sync_irq = bus->irq;
|
2014-05-20 02:18:27 +00:00
|
|
|
|
2020-05-04 08:16:14 +00:00
|
|
|
/*
|
|
|
|
* Tegra194 has 4 SDO lines and the STRIPE can be used to
|
|
|
|
* indicate how many of the SDO lines the stream should be
|
|
|
|
* striped. But GCAP register does not reflect the true
|
|
|
|
* capability of HW. Below workaround helps to fix this.
|
|
|
|
*
|
|
|
|
* GCAP_NSDO is bits 19:18 in T_AZA_DBG_CFG_2,
|
|
|
|
* 0 for 1 SDO, 1 for 2 SDO, 2 for 4 SDO lines.
|
|
|
|
*/
|
|
|
|
if (of_device_is_compatible(np, "nvidia,tegra194-hda")) {
|
|
|
|
u32 val;
|
|
|
|
|
|
|
|
dev_info(card->dev, "Override SDO lines to %u\n",
|
|
|
|
TEGRA194_NUM_SDO_LINES);
|
|
|
|
|
|
|
|
val = readl(hda->regs + FPCI_DBG_CFG_2) & ~FPCI_GCAP_NSDO_MASK;
|
|
|
|
val |= (TEGRA194_NUM_SDO_LINES >> 1) << FPCI_GCAP_NSDO_SHIFT;
|
|
|
|
writel(val, hda->regs + FPCI_DBG_CFG_2);
|
|
|
|
}
|
|
|
|
|
2014-05-20 02:18:27 +00:00
|
|
|
gcap = azx_readw(chip, GCAP);
|
|
|
|
dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
|
|
|
|
|
2020-08-05 09:52:19 +00:00
|
|
|
chip->align_buffer_size = 1;
|
|
|
|
|
2014-05-20 02:18:27 +00:00
|
|
|
/* read number of streams from GCAP register instead of using
|
|
|
|
* hardcoded value
|
|
|
|
*/
|
|
|
|
chip->capture_streams = (gcap >> 8) & 0x0f;
|
|
|
|
chip->playback_streams = (gcap >> 12) & 0x0f;
|
|
|
|
if (!chip->playback_streams && !chip->capture_streams) {
|
|
|
|
/* gcap didn't give any info, switching to old method */
|
|
|
|
chip->playback_streams = NUM_PLAYBACK_SD;
|
|
|
|
chip->capture_streams = NUM_CAPTURE_SD;
|
|
|
|
}
|
|
|
|
chip->capture_index_offset = 0;
|
|
|
|
chip->playback_index_offset = chip->capture_streams;
|
|
|
|
chip->num_streams = chip->playback_streams + chip->capture_streams;
|
|
|
|
|
2015-04-14 20:13:18 +00:00
|
|
|
/* initialize streams */
|
|
|
|
err = azx_init_streams(chip);
|
2015-05-05 12:56:21 +00:00
|
|
|
if (err < 0) {
|
|
|
|
dev_err(card->dev, "failed to initialize streams: %d\n", err);
|
2014-05-20 02:18:27 +00:00
|
|
|
return err;
|
2015-05-05 12:56:21 +00:00
|
|
|
}
|
2014-05-20 02:18:27 +00:00
|
|
|
|
2015-04-14 20:13:18 +00:00
|
|
|
err = azx_alloc_stream_pages(chip);
|
2015-05-05 12:56:21 +00:00
|
|
|
if (err < 0) {
|
|
|
|
dev_err(card->dev, "failed to allocate stream pages: %d\n",
|
|
|
|
err);
|
2015-04-14 20:13:18 +00:00
|
|
|
return err;
|
2015-05-05 12:56:21 +00:00
|
|
|
}
|
2014-05-20 02:18:27 +00:00
|
|
|
|
|
|
|
/* initialize chip */
|
|
|
|
azx_init_chip(chip, 1);
|
|
|
|
|
2020-05-04 08:16:16 +00:00
|
|
|
/*
|
|
|
|
* Playback (for 44.1K/48K, 2-channel, 16-bps) fails with
|
|
|
|
* 4 SDO lines due to legacy design limitation. Following
|
|
|
|
* is, from HD Audio Specification (Revision 1.0a), used to
|
|
|
|
* control striping of the stream across multiple SDO lines
|
|
|
|
* for sample rates <= 48K.
|
|
|
|
*
|
|
|
|
* { ((num_channels * bits_per_sample) / number of SDOs) >= 8 }
|
|
|
|
*
|
|
|
|
* Due to legacy design issue it is recommended that above
|
|
|
|
* ratio must be greater than 8. Since number of SDO lines is
|
|
|
|
* in powers of 2, next available ratio is 16 which can be
|
|
|
|
* used as a limiting factor here.
|
|
|
|
*/
|
ALSA: hda/tegra: fix tegra-hda on tegra30 soc
Currently hda on tegra30 fails to open a stream with an input/output error.
For example:
speaker-test -Dhw:0,3 -c 2
speaker-test 1.2.2
Playback device is hw:0,3
Stream parameters are 48000Hz, S16_LE, 2 channels
Using 16 octaves of pink noise
Rate set to 48000Hz (requested 48000Hz)
Buffer size range from 64 to 16384
Period size range from 32 to 8192
Using max buffer size 16384
Periods = 4
was set period_size = 4096
was set buffer_size = 16384
0 - Front Left
Write error: -5,Input/output error
xrun_recovery failed: -5,Input/output error
Transfer failed: Input/output error
The tegra-hda device was introduced in tegra30 but only utilized in
tegra124 until recent chips. Tegra210/186 work only due to a hardware
change. For this reason it is unknown when this issue first manifested.
Discussions with the hardware team show this applies to all current tegra
chips. It has been resolved in the tegra234, which does not have hda
support at this time.
The explanation from the hardware team is this:
Below is the striping formula referenced from HD audio spec.
{ ((num_channels * bits_per_sample) / number of SDOs) >= 8 }
The current issue is seen because Tegra HW has a problem with boundary
condition (= 8) for striping. The reason why it is not seen on
Tegra210/Tegra186 is because it uses max 2SDO lines. Max SDO lines is
read from GCAP register.
For the given stream (channels = 2, bps = 16);
ratio = (channels * bps) / NSDO = 32 / NSDO;
On Tegra30, ratio = 32/4 = 8 (FAIL)
On Tegra210/186, ratio = 32/2 = 16 (PASS)
On Tegra194, ratio = 32/4 = 8 (FAIL) ==> Earlier workaround was
applied for it
If Tegra210/186 is forced to use 4SDO, it fails there as well. So the
behavior is consistent across all these chips.
Applying the fix in [1] universally resolves this issue on tegra30-hda.
Tested on the Ouya game console and the tf201 tablet.
[1] commit 60019d8c650d ("ALSA: hda/tegra: workaround playback failure on
Tegra194")
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Ion Agorria <ion@agorria.com>
Reviewed-by: Sameer Pujar <spujar@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
Link: https://lore.kernel.org/r/20210108135913.2421585-3-pgwipeout@gmail.com
Signed-off-by: Takashi Iwai <tiwai@suse.de>
2021-01-08 13:59:13 +00:00
|
|
|
if (of_device_is_compatible(np, "nvidia,tegra30-hda"))
|
2020-05-04 08:16:16 +00:00
|
|
|
chip->bus.core.sdo_limit = 16;
|
|
|
|
|
2014-05-20 02:18:27 +00:00
|
|
|
/* codec detection */
|
2015-04-14 20:13:18 +00:00
|
|
|
if (!bus->codec_mask) {
|
2014-05-20 02:18:27 +00:00
|
|
|
dev_err(card->dev, "no codecs found!\n");
|
|
|
|
return -ENODEV;
|
|
|
|
}
|
|
|
|
|
2018-11-29 03:58:52 +00:00
|
|
|
/* driver name */
|
2019-02-20 15:13:24 +00:00
|
|
|
strncpy(card->driver, drv_name, sizeof(card->driver));
|
2018-11-29 03:58:52 +00:00
|
|
|
/* shortname for card */
|
2019-02-20 15:13:24 +00:00
|
|
|
sname = of_get_property(np, "nvidia,model", NULL);
|
|
|
|
if (!sname)
|
|
|
|
sname = drv_name;
|
2018-11-29 03:58:52 +00:00
|
|
|
if (strlen(sname) > sizeof(card->shortname))
|
|
|
|
dev_info(card->dev, "truncating shortname for card\n");
|
|
|
|
strncpy(card->shortname, sname, sizeof(card->shortname));
|
|
|
|
|
|
|
|
/* longname for card */
|
2014-05-20 02:18:27 +00:00
|
|
|
snprintf(card->longname, sizeof(card->longname),
|
|
|
|
"%s at 0x%lx irq %i",
|
2015-04-14 20:13:18 +00:00
|
|
|
card->shortname, bus->addr, bus->irq);
|
2014-05-20 02:18:27 +00:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* constructor
|
|
|
|
*/
|
2015-09-24 09:00:18 +00:00
|
|
|
|
|
|
|
static void hda_tegra_probe_work(struct work_struct *work);
|
|
|
|
|
2014-05-20 02:18:27 +00:00
|
|
|
static int hda_tegra_create(struct snd_card *card,
|
|
|
|
unsigned int driver_caps,
|
|
|
|
struct hda_tegra *hda)
|
|
|
|
{
|
2020-01-03 08:16:24 +00:00
|
|
|
static const struct snd_device_ops ops = {
|
2015-04-14 20:13:18 +00:00
|
|
|
.dev_disconnect = hda_tegra_dev_disconnect,
|
2014-05-20 02:18:27 +00:00
|
|
|
.dev_free = hda_tegra_dev_free,
|
|
|
|
};
|
|
|
|
struct azx *chip;
|
|
|
|
int err;
|
|
|
|
|
|
|
|
chip = &hda->chip;
|
|
|
|
|
|
|
|
mutex_init(&chip->open_mutex);
|
|
|
|
chip->card = card;
|
2015-04-14 15:26:00 +00:00
|
|
|
chip->ops = &hda_tegra_ops;
|
2014-05-20 02:18:27 +00:00
|
|
|
chip->driver_caps = driver_caps;
|
|
|
|
chip->driver_type = driver_caps & 0xff;
|
|
|
|
chip->dev_index = 0;
|
|
|
|
INIT_LIST_HEAD(&chip->pcm_list);
|
|
|
|
|
|
|
|
chip->codec_probe_mask = -1;
|
|
|
|
|
|
|
|
chip->single_cmd = false;
|
|
|
|
chip->snoop = true;
|
|
|
|
|
2015-09-24 09:00:18 +00:00
|
|
|
INIT_WORK(&hda->probe_work, hda_tegra_probe_work);
|
|
|
|
|
2019-08-07 18:32:08 +00:00
|
|
|
err = azx_bus_init(chip, NULL);
|
2015-05-05 12:45:57 +00:00
|
|
|
if (err < 0)
|
|
|
|
return err;
|
|
|
|
|
2020-07-14 16:08:41 +00:00
|
|
|
chip->bus.core.sync_write = 0;
|
2019-12-12 19:11:01 +00:00
|
|
|
chip->bus.core.needs_damn_long_delay = 1;
|
ALSA: hda: Apply aligned MMIO access only conditionally
It turned out that the recent simplification of HD-audio bus access
helpers caused a regression on the virtual HD-audio device on QEMU
with ARM platforms. The driver got a CORB/RIRB timeout and couldn't
probe any codecs.
The essential difference that caused a problem was the enforced
aligned MMIO accesses by simplification. Since snd-hda-tegra driver
is enabled on ARM, it enables CONFIG_SND_HDA_ALIGNED_MMIO, which makes
the all HD-audio drivers using the aligned MMIO accesses. While this
is mandatory for snd-hda-tegra, it seems that snd-hda-intel on ARM
gets broken by this access pattern.
For addressing the regression, this patch introduces a new flag,
aligned_mmio, to hdac_bus object, and applies the aligned MMIO only
when this flag is set. This change affects only platforms with
CONFIG_SND_HDA_ALIGNED_MMIO set, i.e. mostly only for ARM platforms.
Unfortunately the patch became a big bigger than it should be, just
because the former calls didn't take hdac_bus object in the argument,
hence we had to extend the call patterns.
Fixes: 19abfefd4c76 ("ALSA: hda: Direct MMIO accesses")
BugLink: https://bugzilla.opensuse.org/show_bug.cgi?id=1161152
Cc: <stable@vger.kernel.org>
Link: https://lore.kernel.org/r/20200120104127.28985-1-tiwai@suse.de
Signed-off-by: Takashi Iwai <tiwai@suse.de>
2020-01-20 10:41:27 +00:00
|
|
|
chip->bus.core.aligned_mmio = 1;
|
2015-12-17 07:23:39 +00:00
|
|
|
|
2014-05-20 02:18:27 +00:00
|
|
|
err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
|
|
|
|
if (err < 0) {
|
|
|
|
dev_err(card->dev, "Error creating device\n");
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct of_device_id hda_tegra_match[] = {
|
|
|
|
{ .compatible = "nvidia,tegra30-hda" },
|
2020-05-04 08:16:14 +00:00
|
|
|
{ .compatible = "nvidia,tegra194-hda" },
|
2014-05-20 02:18:27 +00:00
|
|
|
{},
|
|
|
|
};
|
2014-05-20 18:26:12 +00:00
|
|
|
MODULE_DEVICE_TABLE(of, hda_tegra_match);
|
2014-05-20 02:18:27 +00:00
|
|
|
|
|
|
|
static int hda_tegra_probe(struct platform_device *pdev)
|
|
|
|
{
|
2019-01-22 07:33:21 +00:00
|
|
|
const unsigned int driver_flags = AZX_DCAPS_CORBRP_SELF_CLEAR |
|
|
|
|
AZX_DCAPS_PM_RUNTIME;
|
2014-05-20 02:18:27 +00:00
|
|
|
struct snd_card *card;
|
|
|
|
struct azx *chip;
|
|
|
|
struct hda_tegra *hda;
|
|
|
|
int err;
|
|
|
|
|
|
|
|
hda = devm_kzalloc(&pdev->dev, sizeof(*hda), GFP_KERNEL);
|
|
|
|
if (!hda)
|
|
|
|
return -ENOMEM;
|
|
|
|
hda->dev = &pdev->dev;
|
|
|
|
chip = &hda->chip;
|
|
|
|
|
|
|
|
err = snd_card_new(&pdev->dev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1,
|
|
|
|
THIS_MODULE, 0, &card);
|
|
|
|
if (err < 0) {
|
|
|
|
dev_err(&pdev->dev, "Error creating card!\n");
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
2021-01-20 00:31:50 +00:00
|
|
|
hda->reset = devm_reset_control_array_get_exclusive(&pdev->dev);
|
|
|
|
if (IS_ERR(hda->reset)) {
|
|
|
|
err = PTR_ERR(hda->reset);
|
|
|
|
goto out_free;
|
|
|
|
}
|
|
|
|
|
2021-01-20 00:31:49 +00:00
|
|
|
hda->clocks[hda->nclocks++].id = "hda";
|
|
|
|
hda->clocks[hda->nclocks++].id = "hda2hdmi";
|
|
|
|
hda->clocks[hda->nclocks++].id = "hda2codec_2x";
|
|
|
|
|
|
|
|
err = devm_clk_bulk_get(&pdev->dev, hda->nclocks, hda->clocks);
|
2019-01-22 07:33:17 +00:00
|
|
|
if (err < 0)
|
|
|
|
goto out_free;
|
|
|
|
|
2015-04-14 15:26:00 +00:00
|
|
|
err = hda_tegra_create(card, driver_flags, hda);
|
2014-05-20 02:18:27 +00:00
|
|
|
if (err < 0)
|
|
|
|
goto out_free;
|
|
|
|
card->private_data = chip;
|
|
|
|
|
|
|
|
dev_set_drvdata(&pdev->dev, card);
|
2019-01-22 07:33:16 +00:00
|
|
|
|
|
|
|
pm_runtime_enable(hda->dev);
|
|
|
|
if (!azx_has_pm_runtime(chip))
|
|
|
|
pm_runtime_forbid(hda->dev);
|
|
|
|
|
2015-09-24 09:00:18 +00:00
|
|
|
schedule_work(&hda->probe_work);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
out_free:
|
|
|
|
snd_card_free(card);
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void hda_tegra_probe_work(struct work_struct *work)
|
|
|
|
{
|
|
|
|
struct hda_tegra *hda = container_of(work, struct hda_tegra, probe_work);
|
|
|
|
struct azx *chip = &hda->chip;
|
|
|
|
struct platform_device *pdev = to_platform_device(hda->dev);
|
|
|
|
int err;
|
2014-05-20 02:18:27 +00:00
|
|
|
|
2019-01-22 07:33:16 +00:00
|
|
|
pm_runtime_get_sync(hda->dev);
|
2014-05-20 02:18:27 +00:00
|
|
|
err = hda_tegra_first_init(chip, pdev);
|
|
|
|
if (err < 0)
|
|
|
|
goto out_free;
|
|
|
|
|
|
|
|
/* create codec instances */
|
2018-12-03 15:53:16 +00:00
|
|
|
err = azx_probe_codecs(chip, 8);
|
2014-05-20 02:18:27 +00:00
|
|
|
if (err < 0)
|
|
|
|
goto out_free;
|
|
|
|
|
|
|
|
err = azx_codec_configure(chip);
|
|
|
|
if (err < 0)
|
|
|
|
goto out_free;
|
|
|
|
|
|
|
|
err = snd_card_register(chip->card);
|
|
|
|
if (err < 0)
|
|
|
|
goto out_free;
|
|
|
|
|
|
|
|
chip->running = 1;
|
2015-04-14 20:13:18 +00:00
|
|
|
snd_hda_set_power_save(&chip->bus, power_save * 1000);
|
2014-05-20 02:18:27 +00:00
|
|
|
|
2015-09-24 09:00:18 +00:00
|
|
|
out_free:
|
2019-01-22 07:33:16 +00:00
|
|
|
pm_runtime_put(hda->dev);
|
2015-09-24 09:00:18 +00:00
|
|
|
return; /* no error return from async probe */
|
2014-05-20 02:18:27 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static int hda_tegra_remove(struct platform_device *pdev)
|
|
|
|
{
|
2019-01-22 07:33:16 +00:00
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = snd_card_free(dev_get_drvdata(&pdev->dev));
|
|
|
|
pm_runtime_disable(&pdev->dev);
|
|
|
|
|
|
|
|
return ret;
|
2014-05-20 02:18:27 +00:00
|
|
|
}
|
|
|
|
|
2015-03-05 16:21:32 +00:00
|
|
|
static void hda_tegra_shutdown(struct platform_device *pdev)
|
|
|
|
{
|
|
|
|
struct snd_card *card = dev_get_drvdata(&pdev->dev);
|
|
|
|
struct azx *chip;
|
|
|
|
|
|
|
|
if (!card)
|
|
|
|
return;
|
|
|
|
chip = card->private_data;
|
|
|
|
if (chip && chip->running)
|
|
|
|
azx_stop_chip(chip);
|
|
|
|
}
|
|
|
|
|
2014-05-20 02:18:27 +00:00
|
|
|
static struct platform_driver tegra_platform_hda = {
|
|
|
|
.driver = {
|
|
|
|
.name = "tegra-hda",
|
|
|
|
.pm = &hda_tegra_pm,
|
|
|
|
.of_match_table = hda_tegra_match,
|
|
|
|
},
|
|
|
|
.probe = hda_tegra_probe,
|
|
|
|
.remove = hda_tegra_remove,
|
2015-03-05 16:21:32 +00:00
|
|
|
.shutdown = hda_tegra_shutdown,
|
2014-05-20 02:18:27 +00:00
|
|
|
};
|
|
|
|
module_platform_driver(tegra_platform_hda);
|
|
|
|
|
|
|
|
MODULE_DESCRIPTION("Tegra HDA bus driver");
|
|
|
|
MODULE_LICENSE("GPL v2");
|