2011-01-20 07:50:55 +00:00
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/*
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* This file contains low level CPU setup functions.
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* Copyright (C) 2003 Benjamin Herrenschmidt (benh@kernel.crashing.org)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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*/
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#include <asm/processor.h>
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#include <asm/page.h>
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#include <asm/cputable.h>
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#include <asm/ppc_asm.h>
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#include <asm/asm-offsets.h>
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#include <asm/cache.h>
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2016-03-01 07:29:20 +00:00
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#include <asm/book3s/64/mmu-hash.h>
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2011-01-20 07:50:55 +00:00
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/* Entry: r3 = crap, r4 = ptr to cputable entry
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*
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* Note that we can be called twice for pseudo-PVRs
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*/
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_GLOBAL(__setup_cpu_power7)
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mflr r11
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bl __init_hvmode_206
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mtlr r11
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beqlr
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2011-03-01 04:46:09 +00:00
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li r0,0
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mtspr SPRN_LPID,r0
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2012-11-05 03:40:18 +00:00
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mfspr r3,SPRN_LPCR
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2011-01-20 07:50:55 +00:00
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bl __init_LPCR
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2013-10-30 14:34:56 +00:00
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bl __init_tlb_power7
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2011-01-20 07:50:55 +00:00
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mtlr r11
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blr
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_GLOBAL(__restore_cpu_power7)
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mflr r11
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mfmsr r3
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rldicl. r0,r3,4,63
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beqlr
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2011-03-01 04:46:09 +00:00
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li r0,0
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mtspr SPRN_LPID,r0
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2012-11-05 03:40:18 +00:00
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mfspr r3,SPRN_LPCR
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2011-01-20 07:50:55 +00:00
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bl __init_LPCR
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2013-10-30 14:34:56 +00:00
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bl __init_tlb_power7
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2012-10-30 19:34:14 +00:00
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mtlr r11
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blr
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_GLOBAL(__setup_cpu_power8)
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mflr r11
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2013-03-04 19:45:50 +00:00
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bl __init_FSCR
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2013-04-25 19:28:22 +00:00
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bl __init_PMU
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2012-10-30 19:34:14 +00:00
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bl __init_hvmode_206
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mtlr r11
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beqlr
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li r0,0
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mtspr SPRN_LPID,r0
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2012-11-05 03:40:18 +00:00
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mfspr r3,SPRN_LPCR
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2014-06-11 05:59:28 +00:00
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ori r3, r3, LPCR_PECEDH
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2012-10-30 19:34:14 +00:00
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bl __init_LPCR
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2013-03-05 17:35:24 +00:00
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bl __init_HFSCR
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2013-10-30 14:34:56 +00:00
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bl __init_tlb_power8
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2013-04-25 19:28:22 +00:00
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bl __init_PMU_HV
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2012-10-30 19:34:14 +00:00
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mtlr r11
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blr
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_GLOBAL(__restore_cpu_power8)
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mflr r11
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2013-03-04 19:45:50 +00:00
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bl __init_FSCR
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2013-04-25 19:28:22 +00:00
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bl __init_PMU
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2012-10-30 19:34:14 +00:00
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mfmsr r3
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rldicl. r0,r3,4,63
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2013-04-24 21:00:37 +00:00
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mtlr r11
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2012-10-30 19:34:14 +00:00
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beqlr
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li r0,0
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mtspr SPRN_LPID,r0
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2012-11-05 03:40:18 +00:00
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mfspr r3,SPRN_LPCR
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2014-06-11 05:59:28 +00:00
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ori r3, r3, LPCR_PECEDH
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2012-10-30 19:34:14 +00:00
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bl __init_LPCR
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2013-03-05 17:35:24 +00:00
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bl __init_HFSCR
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2013-10-30 14:34:56 +00:00
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bl __init_tlb_power8
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2013-04-25 19:28:22 +00:00
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bl __init_PMU_HV
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2011-01-20 07:50:55 +00:00
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mtlr r11
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blr
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2016-02-19 00:16:24 +00:00
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_GLOBAL(__setup_cpu_power9)
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mflr r11
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bl __init_FSCR
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bl __init_hvmode_206
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mtlr r11
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beqlr
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li r0,0
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mtspr SPRN_LPID,r0
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mfspr r3,SPRN_LPCR
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ori r3, r3, LPCR_PECEDH
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bl __init_LPCR
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bl __init_HFSCR
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bl __init_tlb_power9
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mtlr r11
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blr
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_GLOBAL(__restore_cpu_power9)
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mflr r11
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bl __init_FSCR
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mfmsr r3
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rldicl. r0,r3,4,63
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mtlr r11
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beqlr
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li r0,0
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mtspr SPRN_LPID,r0
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mfspr r3,SPRN_LPCR
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ori r3, r3, LPCR_PECEDH
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bl __init_LPCR
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bl __init_HFSCR
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bl __init_tlb_power9
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mtlr r11
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blr
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2011-01-20 07:50:55 +00:00
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__init_hvmode_206:
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powerpc, KVM: Split HVMODE_206 cpu feature bit into separate HV and architecture bits
This replaces the single CPU_FTR_HVMODE_206 bit with two bits, one to
indicate that we have a usable hypervisor mode, and another to indicate
that the processor conforms to PowerISA version 2.06. We also add
another bit to indicate that the processor conforms to ISA version 2.01
and set that for PPC970 and derivatives.
Some PPC970 chips (specifically those in Apple machines) have a
hypervisor mode in that MSR[HV] is always 1, but the hypervisor mode
is not useful in the sense that there is no way to run any code in
supervisor mode (HV=0 PR=0). On these processors, the LPES0 and LPES1
bits in HID4 are always 0, and we use that as a way of detecting that
hypervisor mode is not useful.
Where we have a feature section in assembly code around code that
only applies on POWER7 in hypervisor mode, we use a construct like
END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
The definition of END_FTR_SECTION_IFSET is such that the code will
be enabled (not overwritten with nops) only if all bits in the
provided mask are set.
Note that the CPU feature check in __tlbie() only needs to check the
ARCH_206 bit, not the HVMODE bit, because __tlbie() can only get called
if we are running bare-metal, i.e. in hypervisor mode.
Signed-off-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
2011-06-29 00:26:11 +00:00
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/* Disable CPU_FTR_HVMODE and exit if MSR:HV is not set */
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2011-01-20 07:50:55 +00:00
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mfmsr r3
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rldicl. r0,r3,4,63
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bnelr
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ld r5,CPU_SPEC_FEATURES(r4)
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powerpc, KVM: Split HVMODE_206 cpu feature bit into separate HV and architecture bits
This replaces the single CPU_FTR_HVMODE_206 bit with two bits, one to
indicate that we have a usable hypervisor mode, and another to indicate
that the processor conforms to PowerISA version 2.06. We also add
another bit to indicate that the processor conforms to ISA version 2.01
and set that for PPC970 and derivatives.
Some PPC970 chips (specifically those in Apple machines) have a
hypervisor mode in that MSR[HV] is always 1, but the hypervisor mode
is not useful in the sense that there is no way to run any code in
supervisor mode (HV=0 PR=0). On these processors, the LPES0 and LPES1
bits in HID4 are always 0, and we use that as a way of detecting that
hypervisor mode is not useful.
Where we have a feature section in assembly code around code that
only applies on POWER7 in hypervisor mode, we use a construct like
END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
The definition of END_FTR_SECTION_IFSET is such that the code will
be enabled (not overwritten with nops) only if all bits in the
provided mask are set.
Note that the CPU feature check in __tlbie() only needs to check the
ARCH_206 bit, not the HVMODE bit, because __tlbie() can only get called
if we are running bare-metal, i.e. in hypervisor mode.
Signed-off-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
2011-06-29 00:26:11 +00:00
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LOAD_REG_IMMEDIATE(r6,CPU_FTR_HVMODE)
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2011-01-20 07:50:55 +00:00
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xor r5,r5,r6
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std r5,CPU_SPEC_FEATURES(r4)
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blr
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__init_LPCR:
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/* Setup a sane LPCR:
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2012-11-05 03:40:18 +00:00
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* Called with initial LPCR in R3
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2011-01-20 07:50:55 +00:00
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*
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2011-04-05 04:20:31 +00:00
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* LPES = 0b01 (HSRR0/1 used for 0x500)
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2011-01-20 07:50:55 +00:00
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* PECE = 0b111
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2011-01-24 02:25:55 +00:00
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* DPFD = 4
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2011-06-29 00:20:24 +00:00
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* HDICE = 0
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* VC = 0b100 (VPM0=1, VPM1=0, ISL=0)
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* VRMASD = 0b10000 (L=1, LP=00)
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2011-01-20 07:50:55 +00:00
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*
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* Other bits untouched for now
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*/
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2011-06-29 00:20:24 +00:00
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li r5,1
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rldimi r3,r5, LPCR_LPES_SH, 64-LPCR_LPES_SH-2
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2011-01-20 07:50:55 +00:00
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ori r3,r3,(LPCR_PECE0|LPCR_PECE1|LPCR_PECE2)
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2011-01-24 02:25:55 +00:00
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li r5,4
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2011-06-29 00:20:24 +00:00
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rldimi r3,r5, LPCR_DPFD_SH, 64-LPCR_DPFD_SH-3
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clrrdi r3,r3,1 /* clear HDICE */
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li r5,4
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rldimi r3,r5, LPCR_VC_SH, 0
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li r5,0x10
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rldimi r3,r5, LPCR_VRMASD_SH, 64-LPCR_VRMASD_SH-5
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2011-01-20 07:50:55 +00:00
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mtspr SPRN_LPCR,r3
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isync
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blr
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2011-03-01 04:46:09 +00:00
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2013-02-07 15:46:58 +00:00
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__init_FSCR:
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mfspr r3,SPRN_FSCR
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2013-04-30 20:17:03 +00:00
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ori r3,r3,FSCR_TAR|FSCR_DSCR|FSCR_EBB
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2013-02-07 15:46:58 +00:00
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mtspr SPRN_FSCR,r3
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blr
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2013-03-05 17:35:24 +00:00
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__init_HFSCR:
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mfspr r3,SPRN_HFSCR
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2013-04-25 20:54:55 +00:00
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ori r3,r3,HFSCR_TAR|HFSCR_TM|HFSCR_BHRB|HFSCR_PM|\
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2013-04-30 20:17:03 +00:00
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HFSCR_DSCR|HFSCR_VECVSX|HFSCR_FP|HFSCR_EBB
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2013-03-05 17:35:24 +00:00
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mtspr SPRN_HFSCR,r3
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blr
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2013-10-30 14:34:56 +00:00
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/*
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* Clear the TLB using the specified IS form of tlbiel instruction
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* (invalidate by congruence class). P7 has 128 CCs., P8 has 512.
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*/
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__init_tlb_power7:
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2016-02-19 00:16:23 +00:00
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li r6,POWER7_TLB_SETS
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2013-10-30 14:34:56 +00:00
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mtctr r6
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2014-12-19 03:11:05 +00:00
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li r7,0xc00 /* IS field = 0b11 */
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2013-10-30 14:34:56 +00:00
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ptesync
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2: tlbiel r7
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addi r7,r7,0x1000
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bdnz 2b
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ptesync
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1: blr
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__init_tlb_power8:
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2016-02-19 00:16:23 +00:00
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li r6,POWER8_TLB_SETS
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2011-03-01 04:46:09 +00:00
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mtctr r6
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2014-12-19 03:11:05 +00:00
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li r7,0xc00 /* IS field = 0b11 */
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2011-03-01 04:46:09 +00:00
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ptesync
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2: tlbiel r7
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addi r7,r7,0x1000
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bdnz 2b
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ptesync
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1: blr
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2013-04-25 19:28:22 +00:00
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2016-02-19 00:16:24 +00:00
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__init_tlb_power9:
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li r6,POWER9_TLB_SETS_HASH
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mtctr r6
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li r7,0xc00 /* IS field = 0b11 */
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ptesync
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2: tlbiel r7
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addi r7,r7,0x1000
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bdnz 2b
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ptesync
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1: blr
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2013-04-25 19:28:22 +00:00
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__init_PMU_HV:
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li r5,0
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mtspr SPRN_MMCRC,r5
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mtspr SPRN_MMCRH,r5
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blr
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__init_PMU:
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li r5,0
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mtspr SPRN_MMCRS,r5
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mtspr SPRN_MMCRA,r5
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mtspr SPRN_MMCR0,r5
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mtspr SPRN_MMCR1,r5
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mtspr SPRN_MMCR2,r5
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blr
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