forked from Minki/linux
185 lines
4.7 KiB
C
185 lines
4.7 KiB
C
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/*
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* Copyright (c) 2013 MundoReader S.L.
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* Author: Heiko Stuebner <heiko@sntech.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/smp.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <asm/cacheflush.h>
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#include <asm/smp_scu.h>
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#include <asm/smp_plat.h>
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#include <asm/mach/map.h>
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#include "core.h"
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static void __iomem *scu_base_addr;
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static void __iomem *sram_base_addr;
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static int ncores;
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#define PMU_PWRDN_CON 0x08
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#define PMU_PWRDN_ST 0x0c
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#define PMU_PWRDN_SCU 4
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static void __iomem *pmu_base_addr;
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static inline bool pmu_power_domain_is_on(int pd)
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{
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return !(readl_relaxed(pmu_base_addr + PMU_PWRDN_ST) & BIT(pd));
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}
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static void pmu_set_power_domain(int pd, bool on)
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{
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u32 val = readl_relaxed(pmu_base_addr + PMU_PWRDN_CON);
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if (on)
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val &= ~BIT(pd);
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else
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val |= BIT(pd);
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writel(val, pmu_base_addr + PMU_PWRDN_CON);
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while (pmu_power_domain_is_on(pd) != on) { }
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}
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/*
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* Handling of CPU cores
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*/
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static int __cpuinit rockchip_boot_secondary(unsigned int cpu,
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struct task_struct *idle)
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{
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if (!sram_base_addr || !pmu_base_addr) {
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pr_err("%s: sram or pmu missing for cpu boot\n", __func__);
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return -ENXIO;
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}
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if (cpu >= ncores) {
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pr_err("%s: cpu %d outside maximum number of cpus %d\n",
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__func__, cpu, ncores);
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return -ENXIO;
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}
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/* start the core */
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pmu_set_power_domain(0 + cpu, true);
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return 0;
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}
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/**
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* rockchip_smp_prepare_sram - populate necessary sram block
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* Starting cores execute the code residing at the start of the on-chip sram
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* after power-on. Therefore make sure, this sram region is reserved and
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* big enough. After this check, copy the trampoline code that directs the
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* core to the real startup code in ram into the sram-region.
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* @node: mmio-sram device node
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*/
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static int __init rockchip_smp_prepare_sram(struct device_node *node)
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{
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unsigned int trampoline_sz = &rockchip_secondary_trampoline_end -
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&rockchip_secondary_trampoline;
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struct resource res;
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unsigned int rsize;
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int ret;
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ret = of_address_to_resource(node, 0, &res);
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if (ret < 0) {
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pr_err("%s: could not get address for node %s\n",
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__func__, node->full_name);
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return ret;
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}
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rsize = resource_size(&res);
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if (rsize < trampoline_sz) {
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pr_err("%s: reserved block with size 0x%x is to small for trampoline size 0x%x\n",
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__func__, rsize, trampoline_sz);
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return -EINVAL;
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}
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sram_base_addr = of_iomap(node, 0);
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/* set the boot function for the sram code */
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rockchip_boot_fn = virt_to_phys(rockchip_secondary_startup);
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/* copy the trampoline to sram, that runs during startup of the core */
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memcpy(sram_base_addr, &rockchip_secondary_trampoline, trampoline_sz);
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flush_cache_all();
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outer_clean_range(0, trampoline_sz);
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dsb_sev();
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return 0;
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}
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static void __init rockchip_smp_prepare_cpus(unsigned int max_cpus)
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{
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struct device_node *node;
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unsigned int i;
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node = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
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if (!node) {
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pr_err("%s: missing scu\n", __func__);
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return;
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}
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scu_base_addr = of_iomap(node, 0);
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if (!scu_base_addr) {
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pr_err("%s: could not map scu registers\n", __func__);
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return;
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}
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node = of_find_compatible_node(NULL, NULL, "rockchip,rk3066-smp-sram");
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if (!node) {
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pr_err("%s: could not find sram dt node\n", __func__);
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return;
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}
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if (rockchip_smp_prepare_sram(node))
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return;
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node = of_find_compatible_node(NULL, NULL, "rockchip,rk3066-pmu");
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if (!node) {
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pr_err("%s: could not find sram dt node\n", __func__);
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return;
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}
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pmu_base_addr = of_iomap(node, 0);
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if (!pmu_base_addr) {
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pr_err("%s: could not map pmu registers\n", __func__);
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return;
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}
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/* enable the SCU power domain */
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pmu_set_power_domain(PMU_PWRDN_SCU, true);
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/*
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* While the number of cpus is gathered from dt, also get the number
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* of cores from the scu to verify this value when booting the cores.
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*/
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ncores = scu_get_core_count(scu_base_addr);
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scu_enable(scu_base_addr);
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/* Make sure that all cores except the first are really off */
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for (i = 1; i < ncores; i++)
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pmu_set_power_domain(0 + i, false);
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}
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struct smp_operations rockchip_smp_ops __initdata = {
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.smp_prepare_cpus = rockchip_smp_prepare_cpus,
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.smp_boot_secondary = rockchip_boot_secondary,
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};
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