2013-08-08 11:34:54 +00:00
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/* MOXA ART Ethernet (RTL8201CP) driver.
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*
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* Copyright (C) 2013 Jonas Jensen
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*
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* Jonas Jensen <jonas.jensen@gmail.com>
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*
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* Based on code from
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* Moxa Technology Co., Ltd. <www.moxa.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/module.h>
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#include <linux/netdevice.h>
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#include <linux/etherdevice.h>
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#include <linux/skbuff.h>
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#include <linux/dma-mapping.h>
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#include <linux/ethtool.h>
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#include <linux/platform_device.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/crc32.h>
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#include <linux/crc32c.h>
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#include "moxart_ether.h"
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static inline void moxart_emac_write(struct net_device *ndev,
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unsigned int reg, unsigned long value)
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{
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struct moxart_mac_priv_t *priv = netdev_priv(ndev);
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writel(value, priv->base + reg);
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}
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static void moxart_update_mac_address(struct net_device *ndev)
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{
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moxart_emac_write(ndev, REG_MAC_MS_ADDRESS,
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((ndev->dev_addr[0] << 8) | (ndev->dev_addr[1])));
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moxart_emac_write(ndev, REG_MAC_MS_ADDRESS + 4,
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((ndev->dev_addr[2] << 24) |
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(ndev->dev_addr[3] << 16) |
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(ndev->dev_addr[4] << 8) |
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(ndev->dev_addr[5])));
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}
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static int moxart_set_mac_address(struct net_device *ndev, void *addr)
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{
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struct sockaddr *address = addr;
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if (!is_valid_ether_addr(address->sa_data))
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return -EADDRNOTAVAIL;
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memcpy(ndev->dev_addr, address->sa_data, ndev->addr_len);
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moxart_update_mac_address(ndev);
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return 0;
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}
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static void moxart_mac_free_memory(struct net_device *ndev)
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{
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struct moxart_mac_priv_t *priv = netdev_priv(ndev);
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int i;
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for (i = 0; i < RX_DESC_NUM; i++)
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dma_unmap_single(&ndev->dev, priv->rx_mapping[i],
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priv->rx_buf_size, DMA_FROM_DEVICE);
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if (priv->tx_desc_base)
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dma_free_coherent(NULL, TX_REG_DESC_SIZE * TX_DESC_NUM,
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priv->tx_desc_base, priv->tx_base);
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if (priv->rx_desc_base)
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dma_free_coherent(NULL, RX_REG_DESC_SIZE * RX_DESC_NUM,
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priv->rx_desc_base, priv->rx_base);
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kfree(priv->tx_buf_base);
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kfree(priv->rx_buf_base);
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}
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static void moxart_mac_reset(struct net_device *ndev)
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{
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struct moxart_mac_priv_t *priv = netdev_priv(ndev);
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writel(SW_RST, priv->base + REG_MAC_CTRL);
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while (readl(priv->base + REG_MAC_CTRL) & SW_RST)
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mdelay(10);
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writel(0, priv->base + REG_INTERRUPT_MASK);
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priv->reg_maccr = RX_BROADPKT | FULLDUP | CRC_APD | RX_FTL;
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}
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static void moxart_mac_enable(struct net_device *ndev)
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{
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struct moxart_mac_priv_t *priv = netdev_priv(ndev);
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writel(0x00001010, priv->base + REG_INT_TIMER_CTRL);
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writel(0x00000001, priv->base + REG_APOLL_TIMER_CTRL);
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writel(0x00000390, priv->base + REG_DMA_BLEN_CTRL);
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priv->reg_imr |= (RPKT_FINISH_M | XPKT_FINISH_M);
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writel(priv->reg_imr, priv->base + REG_INTERRUPT_MASK);
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priv->reg_maccr |= (RCV_EN | XMT_EN | RDMA_EN | XDMA_EN);
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writel(priv->reg_maccr, priv->base + REG_MAC_CTRL);
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}
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static void moxart_mac_setup_desc_ring(struct net_device *ndev)
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{
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struct moxart_mac_priv_t *priv = netdev_priv(ndev);
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void __iomem *desc;
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int i;
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for (i = 0; i < TX_DESC_NUM; i++) {
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desc = priv->tx_desc_base + i * TX_REG_DESC_SIZE;
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memset(desc, 0, TX_REG_DESC_SIZE);
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priv->tx_buf[i] = priv->tx_buf_base + priv->tx_buf_size * i;
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}
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writel(TX_DESC1_END, desc + TX_REG_OFFSET_DESC1);
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priv->tx_head = 0;
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priv->tx_tail = 0;
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for (i = 0; i < RX_DESC_NUM; i++) {
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desc = priv->rx_desc_base + i * RX_REG_DESC_SIZE;
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memset(desc, 0, RX_REG_DESC_SIZE);
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writel(RX_DESC0_DMA_OWN, desc + RX_REG_OFFSET_DESC0);
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writel(RX_BUF_SIZE & RX_DESC1_BUF_SIZE_MASK,
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desc + RX_REG_OFFSET_DESC1);
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priv->rx_buf[i] = priv->rx_buf_base + priv->rx_buf_size * i;
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priv->rx_mapping[i] = dma_map_single(&ndev->dev,
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priv->rx_buf[i],
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priv->rx_buf_size,
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DMA_FROM_DEVICE);
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if (dma_mapping_error(&ndev->dev, priv->rx_mapping[i]))
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netdev_err(ndev, "DMA mapping error\n");
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writel(priv->rx_mapping[i],
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desc + RX_REG_OFFSET_DESC2 + RX_DESC2_ADDRESS_PHYS);
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writel(priv->rx_buf[i],
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desc + RX_REG_OFFSET_DESC2 + RX_DESC2_ADDRESS_VIRT);
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}
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writel(RX_DESC1_END, desc + RX_REG_OFFSET_DESC1);
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priv->rx_head = 0;
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/* reset the MAC controler TX/RX desciptor base address */
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writel(priv->tx_base, priv->base + REG_TXR_BASE_ADDRESS);
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writel(priv->rx_base, priv->base + REG_RXR_BASE_ADDRESS);
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}
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static int moxart_mac_open(struct net_device *ndev)
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{
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struct moxart_mac_priv_t *priv = netdev_priv(ndev);
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if (!is_valid_ether_addr(ndev->dev_addr))
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return -EADDRNOTAVAIL;
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napi_enable(&priv->napi);
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moxart_mac_reset(ndev);
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moxart_update_mac_address(ndev);
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moxart_mac_setup_desc_ring(ndev);
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moxart_mac_enable(ndev);
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netif_start_queue(ndev);
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netdev_dbg(ndev, "%s: IMR=0x%x, MACCR=0x%x\n",
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__func__, readl(priv->base + REG_INTERRUPT_MASK),
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readl(priv->base + REG_MAC_CTRL));
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return 0;
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}
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static int moxart_mac_stop(struct net_device *ndev)
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{
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struct moxart_mac_priv_t *priv = netdev_priv(ndev);
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napi_disable(&priv->napi);
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netif_stop_queue(ndev);
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/* disable all interrupts */
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writel(0, priv->base + REG_INTERRUPT_MASK);
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/* disable all functions */
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writel(0, priv->base + REG_MAC_CTRL);
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return 0;
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}
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static int moxart_rx_poll(struct napi_struct *napi, int budget)
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{
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struct moxart_mac_priv_t *priv = container_of(napi,
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struct moxart_mac_priv_t,
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napi);
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struct net_device *ndev = priv->ndev;
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struct sk_buff *skb;
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void __iomem *desc;
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unsigned int desc0, len;
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int rx_head = priv->rx_head;
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int rx = 0;
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while (1) {
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desc = priv->rx_desc_base + (RX_REG_DESC_SIZE * rx_head);
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desc0 = readl(desc + RX_REG_OFFSET_DESC0);
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if (desc0 & RX_DESC0_DMA_OWN)
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break;
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if (desc0 & (RX_DESC0_ERR | RX_DESC0_CRC_ERR | RX_DESC0_FTL |
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RX_DESC0_RUNT | RX_DESC0_ODD_NB)) {
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net_dbg_ratelimited("packet error\n");
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priv->stats.rx_dropped++;
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priv->stats.rx_errors++;
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continue;
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}
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len = desc0 & RX_DESC0_FRAME_LEN_MASK;
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if (len > RX_BUF_SIZE)
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len = RX_BUF_SIZE;
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2014-08-25 14:22:32 +00:00
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dma_sync_single_for_cpu(&ndev->dev,
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priv->rx_mapping[rx_head],
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priv->rx_buf_size, DMA_FROM_DEVICE);
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2014-08-25 14:22:22 +00:00
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skb = netdev_alloc_skb_ip_align(ndev, len);
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2013-08-08 11:34:54 +00:00
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if (unlikely(!skb)) {
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2014-08-25 14:22:22 +00:00
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net_dbg_ratelimited("netdev_alloc_skb_ip_align failed\n");
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2013-08-08 11:34:54 +00:00
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priv->stats.rx_dropped++;
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priv->stats.rx_errors++;
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}
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2014-08-25 14:22:22 +00:00
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memcpy(skb->data, priv->rx_buf[rx_head], len);
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2013-08-08 11:34:54 +00:00
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skb_put(skb, len);
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skb->protocol = eth_type_trans(skb, ndev);
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napi_gro_receive(&priv->napi, skb);
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rx++;
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ndev->last_rx = jiffies;
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priv->stats.rx_packets++;
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priv->stats.rx_bytes += len;
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if (desc0 & RX_DESC0_MULTICAST)
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priv->stats.multicast++;
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writel(RX_DESC0_DMA_OWN, desc + RX_REG_OFFSET_DESC0);
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rx_head = RX_NEXT(rx_head);
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priv->rx_head = rx_head;
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if (rx >= budget)
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break;
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}
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if (rx < budget) {
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napi_gro_flush(napi, false);
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__napi_complete(napi);
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}
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priv->reg_imr |= RPKT_FINISH_M;
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writel(priv->reg_imr, priv->base + REG_INTERRUPT_MASK);
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return rx;
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}
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static void moxart_tx_finished(struct net_device *ndev)
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{
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struct moxart_mac_priv_t *priv = netdev_priv(ndev);
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unsigned tx_head = priv->tx_head;
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unsigned tx_tail = priv->tx_tail;
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while (tx_tail != tx_head) {
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dma_unmap_single(&ndev->dev, priv->tx_mapping[tx_tail],
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priv->tx_len[tx_tail], DMA_TO_DEVICE);
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priv->stats.tx_packets++;
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priv->stats.tx_bytes += priv->tx_skb[tx_tail]->len;
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dev_kfree_skb_irq(priv->tx_skb[tx_tail]);
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priv->tx_skb[tx_tail] = NULL;
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tx_tail = TX_NEXT(tx_tail);
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}
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priv->tx_tail = tx_tail;
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}
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static irqreturn_t moxart_mac_interrupt(int irq, void *dev_id)
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{
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struct net_device *ndev = (struct net_device *) dev_id;
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struct moxart_mac_priv_t *priv = netdev_priv(ndev);
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unsigned int ists = readl(priv->base + REG_INTERRUPT_STATUS);
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if (ists & XPKT_OK_INT_STS)
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moxart_tx_finished(ndev);
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if (ists & RPKT_FINISH) {
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if (napi_schedule_prep(&priv->napi)) {
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priv->reg_imr &= ~RPKT_FINISH_M;
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writel(priv->reg_imr, priv->base + REG_INTERRUPT_MASK);
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__napi_schedule(&priv->napi);
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}
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}
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return IRQ_HANDLED;
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}
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static int moxart_mac_start_xmit(struct sk_buff *skb, struct net_device *ndev)
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{
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struct moxart_mac_priv_t *priv = netdev_priv(ndev);
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void __iomem *desc;
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unsigned int len;
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unsigned int tx_head = priv->tx_head;
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u32 txdes1;
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2013-08-18 08:09:30 +00:00
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int ret = NETDEV_TX_BUSY;
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2013-08-08 11:34:54 +00:00
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desc = priv->tx_desc_base + (TX_REG_DESC_SIZE * tx_head);
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spin_lock_irq(&priv->txlock);
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if (readl(desc + TX_REG_OFFSET_DESC0) & TX_DESC0_DMA_OWN) {
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net_dbg_ratelimited("no TX space for packet\n");
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priv->stats.tx_dropped++;
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2013-08-18 08:09:30 +00:00
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goto out_unlock;
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2013-08-08 11:34:54 +00:00
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}
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len = skb->len > TX_BUF_SIZE ? TX_BUF_SIZE : skb->len;
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priv->tx_mapping[tx_head] = dma_map_single(&ndev->dev, skb->data,
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len, DMA_TO_DEVICE);
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if (dma_mapping_error(&ndev->dev, priv->tx_mapping[tx_head])) {
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netdev_err(ndev, "DMA mapping error\n");
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2013-08-18 08:09:30 +00:00
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goto out_unlock;
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2013-08-08 11:34:54 +00:00
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}
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priv->tx_len[tx_head] = len;
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priv->tx_skb[tx_head] = skb;
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writel(priv->tx_mapping[tx_head],
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|
|
desc + TX_REG_OFFSET_DESC2 + TX_DESC2_ADDRESS_PHYS);
|
|
|
|
writel(skb->data,
|
|
|
|
desc + TX_REG_OFFSET_DESC2 + TX_DESC2_ADDRESS_VIRT);
|
|
|
|
|
|
|
|
if (skb->len < ETH_ZLEN) {
|
|
|
|
memset(&skb->data[skb->len],
|
|
|
|
0, ETH_ZLEN - skb->len);
|
|
|
|
len = ETH_ZLEN;
|
|
|
|
}
|
|
|
|
|
2014-08-25 14:22:32 +00:00
|
|
|
dma_sync_single_for_device(&ndev->dev, priv->tx_mapping[tx_head],
|
|
|
|
priv->tx_buf_size, DMA_TO_DEVICE);
|
|
|
|
|
2014-08-25 14:22:11 +00:00
|
|
|
txdes1 = TX_DESC1_LTS | TX_DESC1_FTS | (len & TX_DESC1_BUF_SIZE_MASK);
|
|
|
|
if (tx_head == TX_DESC_NUM_MASK)
|
|
|
|
txdes1 |= TX_DESC1_END;
|
2013-08-08 11:34:54 +00:00
|
|
|
writel(txdes1, desc + TX_REG_OFFSET_DESC1);
|
|
|
|
writel(TX_DESC0_DMA_OWN, desc + TX_REG_OFFSET_DESC0);
|
|
|
|
|
|
|
|
/* start to send packet */
|
|
|
|
writel(0xffffffff, priv->base + REG_TX_POLL_DEMAND);
|
|
|
|
|
|
|
|
priv->tx_head = TX_NEXT(tx_head);
|
|
|
|
|
|
|
|
ndev->trans_start = jiffies;
|
2013-08-18 08:09:30 +00:00
|
|
|
ret = NETDEV_TX_OK;
|
|
|
|
out_unlock:
|
2013-08-08 11:34:54 +00:00
|
|
|
spin_unlock_irq(&priv->txlock);
|
|
|
|
|
2013-08-18 08:09:30 +00:00
|
|
|
return ret;
|
2013-08-08 11:34:54 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static struct net_device_stats *moxart_mac_get_stats(struct net_device *ndev)
|
|
|
|
{
|
|
|
|
struct moxart_mac_priv_t *priv = netdev_priv(ndev);
|
|
|
|
|
|
|
|
return &priv->stats;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void moxart_mac_setmulticast(struct net_device *ndev)
|
|
|
|
{
|
|
|
|
struct moxart_mac_priv_t *priv = netdev_priv(ndev);
|
|
|
|
struct netdev_hw_addr *ha;
|
|
|
|
int crc_val;
|
|
|
|
|
|
|
|
netdev_for_each_mc_addr(ha, ndev) {
|
|
|
|
crc_val = crc32_le(~0, ha->addr, ETH_ALEN);
|
|
|
|
crc_val = (crc_val >> 26) & 0x3f;
|
|
|
|
if (crc_val >= 32) {
|
|
|
|
writel(readl(priv->base + REG_MCAST_HASH_TABLE1) |
|
|
|
|
(1UL << (crc_val - 32)),
|
|
|
|
priv->base + REG_MCAST_HASH_TABLE1);
|
|
|
|
} else {
|
|
|
|
writel(readl(priv->base + REG_MCAST_HASH_TABLE0) |
|
|
|
|
(1UL << crc_val),
|
|
|
|
priv->base + REG_MCAST_HASH_TABLE0);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void moxart_mac_set_rx_mode(struct net_device *ndev)
|
|
|
|
{
|
|
|
|
struct moxart_mac_priv_t *priv = netdev_priv(ndev);
|
|
|
|
|
|
|
|
spin_lock_irq(&priv->txlock);
|
|
|
|
|
|
|
|
(ndev->flags & IFF_PROMISC) ? (priv->reg_maccr |= RCV_ALL) :
|
|
|
|
(priv->reg_maccr &= ~RCV_ALL);
|
|
|
|
|
|
|
|
(ndev->flags & IFF_ALLMULTI) ? (priv->reg_maccr |= RX_MULTIPKT) :
|
|
|
|
(priv->reg_maccr &= ~RX_MULTIPKT);
|
|
|
|
|
|
|
|
if ((ndev->flags & IFF_MULTICAST) && netdev_mc_count(ndev)) {
|
|
|
|
priv->reg_maccr |= HT_MULTI_EN;
|
|
|
|
moxart_mac_setmulticast(ndev);
|
|
|
|
} else {
|
|
|
|
priv->reg_maccr &= ~HT_MULTI_EN;
|
|
|
|
}
|
|
|
|
|
|
|
|
writel(priv->reg_maccr, priv->base + REG_MAC_CTRL);
|
|
|
|
|
|
|
|
spin_unlock_irq(&priv->txlock);
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct net_device_ops moxart_netdev_ops = {
|
|
|
|
.ndo_open = moxart_mac_open,
|
|
|
|
.ndo_stop = moxart_mac_stop,
|
|
|
|
.ndo_start_xmit = moxart_mac_start_xmit,
|
|
|
|
.ndo_get_stats = moxart_mac_get_stats,
|
|
|
|
.ndo_set_rx_mode = moxart_mac_set_rx_mode,
|
|
|
|
.ndo_set_mac_address = moxart_set_mac_address,
|
|
|
|
.ndo_validate_addr = eth_validate_addr,
|
|
|
|
.ndo_change_mtu = eth_change_mtu,
|
|
|
|
};
|
|
|
|
|
|
|
|
static int moxart_mac_probe(struct platform_device *pdev)
|
|
|
|
{
|
|
|
|
struct device *p_dev = &pdev->dev;
|
|
|
|
struct device_node *node = p_dev->of_node;
|
|
|
|
struct net_device *ndev;
|
|
|
|
struct moxart_mac_priv_t *priv;
|
|
|
|
struct resource *res;
|
|
|
|
unsigned int irq;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ndev = alloc_etherdev(sizeof(struct moxart_mac_priv_t));
|
|
|
|
if (!ndev)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
irq = irq_of_parse_and_map(node, 0);
|
|
|
|
if (irq <= 0) {
|
|
|
|
netdev_err(ndev, "irq_of_parse_and_map failed\n");
|
2013-10-08 03:19:19 +00:00
|
|
|
ret = -EINVAL;
|
|
|
|
goto irq_map_fail;
|
2013-08-08 11:34:54 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
priv = netdev_priv(ndev);
|
|
|
|
priv->ndev = ndev;
|
|
|
|
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
|
|
ndev->base_addr = res->start;
|
|
|
|
priv->base = devm_ioremap_resource(p_dev, res);
|
|
|
|
ret = IS_ERR(priv->base);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(p_dev, "devm_ioremap_resource failed\n");
|
|
|
|
goto init_fail;
|
|
|
|
}
|
|
|
|
|
|
|
|
spin_lock_init(&priv->txlock);
|
|
|
|
|
|
|
|
priv->tx_buf_size = TX_BUF_SIZE;
|
2014-08-25 14:22:22 +00:00
|
|
|
priv->rx_buf_size = RX_BUF_SIZE;
|
2013-08-08 11:34:54 +00:00
|
|
|
|
|
|
|
priv->tx_desc_base = dma_alloc_coherent(NULL, TX_REG_DESC_SIZE *
|
|
|
|
TX_DESC_NUM, &priv->tx_base,
|
|
|
|
GFP_DMA | GFP_KERNEL);
|
2013-10-08 03:19:19 +00:00
|
|
|
if (priv->tx_desc_base == NULL) {
|
|
|
|
ret = -ENOMEM;
|
2013-08-08 11:34:54 +00:00
|
|
|
goto init_fail;
|
2013-10-08 03:19:19 +00:00
|
|
|
}
|
2013-08-08 11:34:54 +00:00
|
|
|
|
|
|
|
priv->rx_desc_base = dma_alloc_coherent(NULL, RX_REG_DESC_SIZE *
|
|
|
|
RX_DESC_NUM, &priv->rx_base,
|
|
|
|
GFP_DMA | GFP_KERNEL);
|
2013-10-08 03:19:19 +00:00
|
|
|
if (priv->rx_desc_base == NULL) {
|
|
|
|
ret = -ENOMEM;
|
2013-08-08 11:34:54 +00:00
|
|
|
goto init_fail;
|
2013-10-08 03:19:19 +00:00
|
|
|
}
|
2013-08-08 11:34:54 +00:00
|
|
|
|
|
|
|
priv->tx_buf_base = kmalloc(priv->tx_buf_size * TX_DESC_NUM,
|
|
|
|
GFP_ATOMIC);
|
2013-10-08 03:19:19 +00:00
|
|
|
if (!priv->tx_buf_base) {
|
|
|
|
ret = -ENOMEM;
|
2013-08-08 11:34:54 +00:00
|
|
|
goto init_fail;
|
2013-10-08 03:19:19 +00:00
|
|
|
}
|
2013-08-08 11:34:54 +00:00
|
|
|
|
|
|
|
priv->rx_buf_base = kmalloc(priv->rx_buf_size * RX_DESC_NUM,
|
|
|
|
GFP_ATOMIC);
|
2013-10-08 03:19:19 +00:00
|
|
|
if (!priv->rx_buf_base) {
|
|
|
|
ret = -ENOMEM;
|
2013-08-08 11:34:54 +00:00
|
|
|
goto init_fail;
|
2013-10-08 03:19:19 +00:00
|
|
|
}
|
2013-08-08 11:34:54 +00:00
|
|
|
|
|
|
|
platform_set_drvdata(pdev, ndev);
|
|
|
|
|
|
|
|
ret = devm_request_irq(p_dev, irq, moxart_mac_interrupt, 0,
|
|
|
|
pdev->name, ndev);
|
|
|
|
if (ret) {
|
|
|
|
netdev_err(ndev, "devm_request_irq failed\n");
|
|
|
|
goto init_fail;
|
|
|
|
}
|
|
|
|
|
|
|
|
ether_setup(ndev);
|
|
|
|
ndev->netdev_ops = &moxart_netdev_ops;
|
|
|
|
netif_napi_add(ndev, &priv->napi, moxart_rx_poll, RX_DESC_NUM);
|
|
|
|
ndev->priv_flags |= IFF_UNICAST_FLT;
|
|
|
|
ndev->irq = irq;
|
|
|
|
|
|
|
|
SET_NETDEV_DEV(ndev, &pdev->dev);
|
|
|
|
|
|
|
|
ret = register_netdev(ndev);
|
|
|
|
if (ret) {
|
|
|
|
free_netdev(ndev);
|
|
|
|
goto init_fail;
|
|
|
|
}
|
|
|
|
|
|
|
|
netdev_dbg(ndev, "%s: IRQ=%d address=%pM\n",
|
|
|
|
__func__, ndev->irq, ndev->dev_addr);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
init_fail:
|
|
|
|
netdev_err(ndev, "init failed\n");
|
|
|
|
moxart_mac_free_memory(ndev);
|
2013-10-08 03:19:19 +00:00
|
|
|
irq_map_fail:
|
|
|
|
free_netdev(ndev);
|
2013-08-08 11:34:54 +00:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int moxart_remove(struct platform_device *pdev)
|
|
|
|
{
|
|
|
|
struct net_device *ndev = platform_get_drvdata(pdev);
|
|
|
|
|
|
|
|
unregister_netdev(ndev);
|
|
|
|
free_irq(ndev->irq, ndev);
|
|
|
|
moxart_mac_free_memory(ndev);
|
|
|
|
free_netdev(ndev);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct of_device_id moxart_mac_match[] = {
|
|
|
|
{ .compatible = "moxa,moxart-mac" },
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
2013-09-30 13:18:27 +00:00
|
|
|
static struct platform_driver moxart_mac_driver = {
|
2013-08-08 11:34:54 +00:00
|
|
|
.probe = moxart_mac_probe,
|
|
|
|
.remove = moxart_remove,
|
|
|
|
.driver = {
|
|
|
|
.name = "moxart-ethernet",
|
|
|
|
.owner = THIS_MODULE,
|
|
|
|
.of_match_table = moxart_mac_match,
|
|
|
|
},
|
|
|
|
};
|
|
|
|
module_platform_driver(moxart_mac_driver);
|
|
|
|
|
|
|
|
MODULE_DESCRIPTION("MOXART RTL8201CP Ethernet driver");
|
|
|
|
MODULE_LICENSE("GPL v2");
|
|
|
|
MODULE_AUTHOR("Jonas Jensen <jonas.jensen@gmail.com>");
|