2005-04-16 22:20:36 +00:00
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/*
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2008-08-05 15:14:15 +00:00
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* arch/arm/plat-omap/include/mach/entry-macro.S
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2005-04-16 22:20:36 +00:00
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*
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* Low-level IRQ helper macros for OMAP-based platforms
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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2008-08-05 15:14:15 +00:00
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#include <mach/hardware.h>
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#include <mach/io.h>
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#include <mach/irqs.h>
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2005-04-16 22:20:36 +00:00
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2005-09-07 16:20:27 +00:00
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#if defined(CONFIG_ARCH_OMAP1)
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2005-11-10 14:26:53 +00:00
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#if defined(CONFIG_ARCH_OMAP730) && \
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(defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX))
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#error "FIXME: OMAP730 doesn't support multiple-OMAP"
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#elif defined(CONFIG_ARCH_OMAP730)
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#define INT_IH2_IRQ INT_730_IH2_IRQ
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#elif defined(CONFIG_ARCH_OMAP15XX)
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#define INT_IH2_IRQ INT_1510_IH2_IRQ
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#elif defined(CONFIG_ARCH_OMAP16XX)
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#define INT_IH2_IRQ INT_1610_IH2_IRQ
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#else
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#warning "IH2 IRQ defaulted"
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#define INT_IH2_IRQ INT_1510_IH2_IRQ
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#endif
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2005-04-16 22:20:36 +00:00
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.macro disable_fiq
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.endm
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2007-02-16 21:16:32 +00:00
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.macro get_irqnr_preamble, base, tmp
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.endm
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.macro arch_ret_to_user, tmp1, tmp2
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.endm
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2005-04-16 22:20:36 +00:00
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.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
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ldr \base, =IO_ADDRESS(OMAP_IH1_BASE)
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ldr \irqnr, [\base, #IRQ_ITR_REG_OFFSET]
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ldr \tmp, [\base, #IRQ_MIR_REG_OFFSET]
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mov \irqstat, #0xffffffff
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bic \tmp, \irqstat, \tmp
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tst \irqnr, \tmp
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beq 1510f
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ldr \irqnr, [\base, #IRQ_SIR_FIQ_REG_OFFSET]
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cmp \irqnr, #0
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ldreq \irqnr, [\base, #IRQ_SIR_IRQ_REG_OFFSET]
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cmpeq \irqnr, #INT_IH2_IRQ
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ldreq \base, =IO_ADDRESS(OMAP_IH2_BASE)
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ldreq \irqnr, [\base, #IRQ_SIR_IRQ_REG_OFFSET]
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addeqs \irqnr, \irqnr, #32
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1510:
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.endm
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2008-10-09 14:51:41 +00:00
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#endif
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#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
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2005-09-07 16:20:27 +00:00
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2008-08-05 15:14:15 +00:00
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#include <mach/omap24xx.h>
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2008-10-09 14:51:41 +00:00
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#include <mach/omap34xx.h>
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2009-05-25 18:08:35 +00:00
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/* REVISIT: This should be set dynamically if CONFIG_MULTI_OMAP2 is selected */
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#if defined(CONFIG_ARCH_OMAP2420) || defined(CONFIG_ARCH_OMAP2430)
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#define OMAP2_VA_IC_BASE IO_ADDRESS(OMAP24XX_IC_BASE)
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#elif defined(CONFIG_ARCH_OMAP34XX)
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#define OMAP2_VA_IC_BASE IO_ADDRESS(OMAP34XX_IC_BASE)
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2008-10-09 14:51:41 +00:00
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#endif
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ARM: OMAP: Fix get_irqnr_and_base to clear spurious interrupt bits
On omap24xx, INTCPS_SIR_IRQ_OFFSET bits [6:0] contains the current
active interrupt number.
However, on 34xx INTCPS_SIR_IRQ_OFFSET bits [31:7] also contains the
SPURIOUSIRQFLAG, which gets set if the interrupt sorting information
is invalid.
If the SPURIOUSIRQFLAG bits are not ignored, the interrupt code will
occasionally produce a bunch of confusing errors:
irq -33, desc: c02ddcc8, depth: 0, count: 0, unhandled: 0
->handle_irq(): c006f23c, handle_bad_irq+0x0/0x22c
->chip(): 00000000, 0x0
->action(): 00000000
Fix this by masking out only the ACTIVEIRQ bits. Also fix a
confusing comment.
Signed-off-by: Tony Lindgren <tony@atomide.com>
2008-11-04 21:35:07 +00:00
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#define INTCPS_SIR_IRQ_OFFSET 0x0040 /* Active interrupt offset */
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#define ACTIVEIRQ_MASK 0x7f /* Active interrupt bits */
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2005-09-07 16:20:27 +00:00
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.macro disable_fiq
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.endm
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2007-03-01 12:46:43 +00:00
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.macro get_irqnr_preamble, base, tmp
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.endm
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.macro arch_ret_to_user, tmp1, tmp2
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.endm
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2005-09-07 16:20:27 +00:00
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.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
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2008-03-18 08:04:51 +00:00
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ldr \base, =OMAP2_VA_IC_BASE
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2005-09-07 16:20:27 +00:00
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ldr \irqnr, [\base, #0x98] /* IRQ pending reg 1 */
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cmp \irqnr, #0x0
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bne 2222f
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ldr \irqnr, [\base, #0xb8] /* IRQ pending reg 2 */
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cmp \irqnr, #0x0
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bne 2222f
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ldr \irqnr, [\base, #0xd8] /* IRQ pending reg 3 */
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cmp \irqnr, #0x0
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2222:
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2008-10-09 14:51:41 +00:00
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ldrne \irqnr, [\base, #INTCPS_SIR_IRQ_OFFSET]
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ARM: OMAP: Fix get_irqnr_and_base to clear spurious interrupt bits
On omap24xx, INTCPS_SIR_IRQ_OFFSET bits [6:0] contains the current
active interrupt number.
However, on 34xx INTCPS_SIR_IRQ_OFFSET bits [31:7] also contains the
SPURIOUSIRQFLAG, which gets set if the interrupt sorting information
is invalid.
If the SPURIOUSIRQFLAG bits are not ignored, the interrupt code will
occasionally produce a bunch of confusing errors:
irq -33, desc: c02ddcc8, depth: 0, count: 0, unhandled: 0
->handle_irq(): c006f23c, handle_bad_irq+0x0/0x22c
->chip(): 00000000, 0x0
->action(): 00000000
Fix this by masking out only the ACTIVEIRQ bits. Also fix a
confusing comment.
Signed-off-by: Tony Lindgren <tony@atomide.com>
2008-11-04 21:35:07 +00:00
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and \irqnr, \irqnr, #ACTIVEIRQ_MASK /* Clear spurious bits */
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2005-09-07 16:20:27 +00:00
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.endm
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.macro irq_prio_table
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.endm
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#endif
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