forked from Minki/linux
177 lines
3.6 KiB
Plaintext
177 lines
3.6 KiB
Plaintext
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/*
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* Copyright 2015 Savoir-faire Linux
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*
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* This device tree is based on imx51-babbage.dts
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*
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* Licensed under the X11 license or the GPL v2 (or later)
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*/
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/dts-v1/;
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#include "imx51.dtsi"
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/ {
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model = "Technologic Systems TS-4800";
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compatible = "technologic,imx51-ts4800", "fsl,imx51";
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chosen {
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stdout-path = &uart1;
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};
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memory {
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reg = <0x90000000 0x10000000>;
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};
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soc {
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fpga {
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compatible = "simple-bus";
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reg = <0xb0000000 0x1d000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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syscon: syscon@b0010000 {
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compatible = "syscon", "simple-mfd";
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reg = <0xb0010000 0x3d>;
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reg-io-width = <2>;
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wdt@e {
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compatible = "technologic,ts4800-wdt";
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syscon = <&syscon 0xe>;
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};
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};
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};
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};
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clocks {
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ckih1 {
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clock-frequency = <22579200>;
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};
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ckih2 {
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clock-frequency = <24576000>;
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};
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};
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};
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&esdhc1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_esdhc1>;
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cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
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wp-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
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status = "okay";
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};
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&fec {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fec>;
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phy-mode = "mii";
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phy-reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>;
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phy-reset-duration = <1>;
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status = "okay";
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};
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&i2c2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c2>;
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status = "okay";
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rtc: m41t00@68 {
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compatible = "stm,m41t00";
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reg = <0x68>;
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};
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};
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&uart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1>;
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status = "okay";
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};
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&uart2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart2>;
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status = "okay";
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};
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&uart3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart3>;
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status = "okay";
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};
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&iomuxc {
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pinctrl_ecspi1: ecspi1grp {
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fsl,pins = <
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MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185
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MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185
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MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185
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MX51_PAD_CSPI1_SS0__GPIO4_24 0x85 /* CS0 */
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>;
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};
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pinctrl_esdhc1: esdhc1grp {
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fsl,pins = <
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MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5
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MX51_PAD_SD1_CLK__SD1_CLK 0x20d5
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MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5
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MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5
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MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5
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MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5
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MX51_PAD_GPIO1_0__GPIO1_0 0x100
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MX51_PAD_GPIO1_1__GPIO1_1 0x100
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>;
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};
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pinctrl_fec: fecgrp {
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fsl,pins = <
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MX51_PAD_EIM_EB2__FEC_MDIO 0x000001f5
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MX51_PAD_EIM_EB3__FEC_RDATA1 0x00000085
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MX51_PAD_EIM_CS2__FEC_RDATA2 0x00000085
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MX51_PAD_EIM_CS3__FEC_RDATA3 0x00000085
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MX51_PAD_EIM_CS4__FEC_RX_ER 0x00000180
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MX51_PAD_EIM_CS5__FEC_CRS 0x00000180
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MX51_PAD_DISP2_DAT10__FEC_COL 0x00000180
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MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x00000180
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MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x00002180
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MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x00002004
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MX51_PAD_NANDF_CS2__FEC_TX_ER 0x00002004
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MX51_PAD_DI2_PIN2__FEC_MDC 0x00002004
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MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x00002004
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MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x00002004
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MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x00002004
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MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x00002004
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MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x00002180
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MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x000020a4
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MX51_PAD_EIM_A20__GPIO2_14 0x00000085 /* Phy Reset */
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>;
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};
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pinctrl_i2c2: i2c2grp {
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fsl,pins = <
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MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed
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MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed
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>;
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};
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pinctrl_uart1: uart1grp {
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fsl,pins = <
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MX51_PAD_UART1_RXD__UART1_RXD 0x1c5
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MX51_PAD_UART1_TXD__UART1_TXD 0x1c5
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>;
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};
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pinctrl_uart2: uart2grp {
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fsl,pins = <
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MX51_PAD_UART2_RXD__UART2_RXD 0x1c5
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MX51_PAD_UART2_TXD__UART2_TXD 0x1c5
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>;
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};
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pinctrl_uart3: uart3grp {
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fsl,pins = <
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MX51_PAD_EIM_D25__UART3_RXD 0x1c5
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MX51_PAD_EIM_D26__UART3_TXD 0x1c5
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>;
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};
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};
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