linux/Documentation/ABI/testing/sysfs-driver-tegra-fuse

What:		/sys/devices/*/<our-device>/fuse
Date:		February 2014
Contact:	Peter De Schrijver <pdeschrijver@nvidia.com>
Description:	read-only access to the efuses on Tegra20, Tegra30, Tegra114
		and Tegra124 SoC's from NVIDIA. The efuses contain write once
		data programmed at the factory. The data is layed out in 32bit
		words in LSB first format. Each bit represents a single value
		as decoded from the fuse registers. Bits order/assignment
		exactly matches the HW registers, including any unused bits.
Users:		any user space application which wants to read the efuses on
		Tegra SoC's
soc/tegra: Add efuse driver for Tegra Implement fuse driver for Tegra20, Tegra30, Tegra114 and Tegra124. This replaces functionality previously provided in arch/arm/mach-tegra, which is removed in this patch. While at it, move the only user of the global tegra_revision variable over to tegra_sku_info.revision and export tegra_fuse_readl() to allow drivers to read calibration fuses. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> 2014-06-12 15:36:37 +00:00			`What: /sys/devices/*/<our-device>/fuse`
			`Date: February 2014`
			`Contact: Peter De Schrijver <pdeschrijver@nvidia.com>`
			`Description: read-only access to the efuses on Tegra20, Tegra30, Tegra114`
			`and Tegra124 SoC's from NVIDIA. The efuses contain write once`
			`data programmed at the factory. The data is layed out in 32bit`
			`words in LSB first format. Each bit represents a single value`
			`as decoded from the fuse registers. Bits order/assignment`
			`exactly matches the HW registers, including any unused bits.`
			`Users: any user space application which wants to read the efuses on`
			`Tegra SoC's`