2010-05-21 20:26:39 +00:00
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/*
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* Copyright © 2008-2010 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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* Authors:
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* Eric Anholt <eric@anholt.net>
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* Zou Nan hai <nanhai.zou@intel.com>
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* Xiang Hai hao<haihao.xiang@intel.com>
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*
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*/
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2015-12-06 10:26:30 +00:00
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#include <linux/log2.h>
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2012-10-02 17:01:07 +00:00
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#include <drm/drmP.h>
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2010-05-21 20:26:39 +00:00
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#include "i915_drv.h"
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2012-10-02 17:01:07 +00:00
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#include <drm/i915_drm.h>
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2010-05-21 20:26:39 +00:00
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#include "i915_trace.h"
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2010-09-19 13:40:43 +00:00
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#include "intel_drv.h"
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2010-05-21 20:26:39 +00:00
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2016-04-29 08:07:05 +00:00
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/* Rough estimate of the typical request size, performing a flush,
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* set-context and then emitting the batch.
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*/
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#define LEGACY_REQUEST_SIZE 200
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2017-05-04 13:08:44 +00:00
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static unsigned int __intel_ring_space(unsigned int head,
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unsigned int tail,
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unsigned int size)
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2011-01-20 17:00:10 +00:00
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{
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2017-05-04 13:08:44 +00:00
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/*
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* "If the Ring Buffer Head Pointer and the Tail Pointer are on the
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* same cacheline, the Head Pointer must not be greater than the Tail
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* Pointer."
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*/
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GEM_BUG_ON(!is_power_of_2(size));
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return (head - tail - CACHELINE_BYTES) & (size - 1);
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2011-01-20 17:00:10 +00:00
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}
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2016-08-02 21:50:22 +00:00
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void intel_ring_update_space(struct intel_ring *ring)
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2014-11-27 11:22:49 +00:00
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{
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2017-04-25 13:00:49 +00:00
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ring->space = __intel_ring_space(ring->head, ring->emit, ring->size);
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2014-11-27 11:22:49 +00:00
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}
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2011-01-04 17:34:02 +00:00
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static int
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2016-08-02 21:50:25 +00:00
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gen2_render_ring_flush(struct drm_i915_gem_request *req, u32 mode)
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2012-04-18 10:12:11 +00:00
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{
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2017-02-14 11:32:42 +00:00
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u32 cmd, *cs;
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2012-04-18 10:12:11 +00:00
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cmd = MI_FLUSH;
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2016-08-02 21:50:25 +00:00
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if (mode & EMIT_INVALIDATE)
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2012-04-18 10:12:11 +00:00
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cmd |= MI_READ_FLUSH;
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2017-02-14 11:32:42 +00:00
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cs = intel_ring_begin(req, 2);
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if (IS_ERR(cs))
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return PTR_ERR(cs);
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2012-04-18 10:12:11 +00:00
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2017-02-14 11:32:42 +00:00
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*cs++ = cmd;
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*cs++ = MI_NOOP;
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intel_ring_advance(req, cs);
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2012-04-18 10:12:11 +00:00
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return 0;
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}
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static int
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2016-08-02 21:50:25 +00:00
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gen4_render_ring_flush(struct drm_i915_gem_request *req, u32 mode)
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2010-05-21 20:26:39 +00:00
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{
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2017-02-14 11:32:42 +00:00
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u32 cmd, *cs;
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2010-08-07 10:01:22 +00:00
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2011-03-19 22:26:49 +00:00
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/*
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* read/write caches:
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*
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* I915_GEM_DOMAIN_RENDER is always invalidated, but is
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* only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
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* also flushed at 2d versus 3d pipeline switches.
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*
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* read-only caches:
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*
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* I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
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* MI_READ_FLUSH is set, and is always flushed on 965.
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*
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* I915_GEM_DOMAIN_COMMAND may not exist?
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*
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* I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
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* invalidated when MI_EXE_FLUSH is set.
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*
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* I915_GEM_DOMAIN_VERTEX, which exists on 965, is
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* invalidated with every MI_FLUSH.
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*
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* TLBs:
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*
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* On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
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* and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
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* I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
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* are flushed at any MI_FLUSH.
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*/
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2016-08-02 21:50:18 +00:00
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cmd = MI_FLUSH;
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2016-08-02 21:50:25 +00:00
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if (mode & EMIT_INVALIDATE) {
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2011-03-19 22:26:49 +00:00
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cmd |= MI_EXE_FLUSH;
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2016-08-02 21:50:18 +00:00
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if (IS_G4X(req->i915) || IS_GEN5(req->i915))
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cmd |= MI_INVALIDATE_ISP;
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}
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2010-11-30 14:07:47 +00:00
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2017-02-14 11:32:42 +00:00
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cs = intel_ring_begin(req, 2);
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if (IS_ERR(cs))
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return PTR_ERR(cs);
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2011-01-04 17:34:02 +00:00
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2017-02-14 11:32:42 +00:00
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*cs++ = cmd;
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*cs++ = MI_NOOP;
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intel_ring_advance(req, cs);
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2011-01-04 17:34:02 +00:00
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return 0;
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2010-05-21 01:08:55 +00:00
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}
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2011-10-16 08:23:31 +00:00
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/**
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* Emits a PIPE_CONTROL with a non-zero post-sync operation, for
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* implementing two workarounds on gen6. From section 1.4.7.1
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* "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
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*
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* [DevSNB-C+{W/A}] Before any depth stall flush (including those
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* produced by non-pipelined state commands), software needs to first
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* send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
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* 0.
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*
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* [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
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* =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
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*
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* And the workaround for these two requires this workaround first:
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*
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* [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
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* BEFORE the pipe-control with a post-sync op and no write-cache
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* flushes.
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*
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* And this last workaround is tricky because of the requirements on
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* that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
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* volume 2 part 1:
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*
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* "1 of the following must also be set:
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* - Render Target Cache Flush Enable ([12] of DW1)
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* - Depth Cache Flush Enable ([0] of DW1)
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* - Stall at Pixel Scoreboard ([1] of DW1)
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* - Depth Stall ([13] of DW1)
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* - Post-Sync Operation ([13] of DW1)
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* - Notify Enable ([8] of DW1)"
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*
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* The cache flushes require the workaround flush that triggered this
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* one, so we can't use it. Depth stall would trigger the same.
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* Post-sync nonzero is what triggered this second workaround, so we
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* can't use that one either. Notify enable is IRQs, which aren't
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* really our business. That leaves only stall at scoreboard.
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*/
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static int
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2015-05-29 16:43:58 +00:00
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intel_emit_post_sync_nonzero_flush(struct drm_i915_gem_request *req)
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2011-10-16 08:23:31 +00:00
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{
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2016-08-02 21:50:18 +00:00
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u32 scratch_addr =
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2016-08-15 09:49:07 +00:00
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i915_ggtt_offset(req->engine->scratch) + 2 * CACHELINE_BYTES;
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2017-02-14 11:32:42 +00:00
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u32 *cs;
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cs = intel_ring_begin(req, 6);
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if (IS_ERR(cs))
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return PTR_ERR(cs);
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*cs++ = GFX_OP_PIPE_CONTROL(5);
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*cs++ = PIPE_CONTROL_CS_STALL | PIPE_CONTROL_STALL_AT_SCOREBOARD;
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*cs++ = scratch_addr | PIPE_CONTROL_GLOBAL_GTT;
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*cs++ = 0; /* low dword */
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*cs++ = 0; /* high dword */
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*cs++ = MI_NOOP;
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intel_ring_advance(req, cs);
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cs = intel_ring_begin(req, 6);
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if (IS_ERR(cs))
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return PTR_ERR(cs);
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*cs++ = GFX_OP_PIPE_CONTROL(5);
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*cs++ = PIPE_CONTROL_QW_WRITE;
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*cs++ = scratch_addr | PIPE_CONTROL_GLOBAL_GTT;
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*cs++ = 0;
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*cs++ = 0;
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*cs++ = MI_NOOP;
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intel_ring_advance(req, cs);
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2011-10-16 08:23:31 +00:00
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return 0;
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}
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static int
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2016-08-02 21:50:25 +00:00
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gen6_render_ring_flush(struct drm_i915_gem_request *req, u32 mode)
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2011-10-16 08:23:31 +00:00
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{
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2016-08-02 21:50:18 +00:00
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u32 scratch_addr =
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2016-08-15 09:49:07 +00:00
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i915_ggtt_offset(req->engine->scratch) + 2 * CACHELINE_BYTES;
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2017-02-14 11:32:42 +00:00
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u32 *cs, flags = 0;
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2011-10-16 08:23:31 +00:00
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int ret;
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2012-08-17 21:35:42 +00:00
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/* Force SNB workarounds for PIPE_CONTROL flushes */
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2015-05-29 16:43:58 +00:00
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ret = intel_emit_post_sync_nonzero_flush(req);
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2012-08-17 21:35:42 +00:00
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if (ret)
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return ret;
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2011-10-16 08:23:31 +00:00
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/* Just flush everything. Experiments have shown that reducing the
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* number of bits based on the write domains has little performance
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* impact.
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*/
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2016-08-02 21:50:25 +00:00
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if (mode & EMIT_FLUSH) {
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2012-08-10 09:18:10 +00:00
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flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
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flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
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/*
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* Ensure that any following seqno writes only happen
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* when the render cache is indeed flushed.
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*/
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2012-06-28 07:48:42 +00:00
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flags |= PIPE_CONTROL_CS_STALL;
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2012-08-10 09:18:10 +00:00
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}
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2016-08-02 21:50:25 +00:00
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if (mode & EMIT_INVALIDATE) {
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2012-08-10 09:18:10 +00:00
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flags |= PIPE_CONTROL_TLB_INVALIDATE;
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flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
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flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
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flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
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flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
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flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
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/*
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* TLB invalidate requires a post-sync write.
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*/
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2012-10-25 19:15:47 +00:00
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flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
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2012-08-10 09:18:10 +00:00
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}
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2011-10-16 08:23:31 +00:00
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2017-02-14 11:32:42 +00:00
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cs = intel_ring_begin(req, 4);
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if (IS_ERR(cs))
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return PTR_ERR(cs);
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2011-10-16 08:23:31 +00:00
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2017-02-14 11:32:42 +00:00
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*cs++ = GFX_OP_PIPE_CONTROL(4);
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*cs++ = flags;
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*cs++ = scratch_addr | PIPE_CONTROL_GLOBAL_GTT;
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*cs++ = 0;
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intel_ring_advance(req, cs);
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2011-10-16 08:23:31 +00:00
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return 0;
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}
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drm/i915: add workarounds to gen7_render_ring_flush
From Bspec, Vol 2a, Section 1.9.3.4 "PIPE_CONTROL", intro section
detailing the various workarounds:
"[DevIVB {W/A}, DevHSW {W/A}]: Pipe_control with CS-stall bit
set must be issued before a pipe-control command that has the State
Cache Invalidate bit set."
Note that public Bspec has different numbering, it's Vol2Part1,
Section 1.10.4.1 "PIPE_CONTROL" there.
There's also a second workaround for the PIPE_CONTROL command itself:
"[DevIVB, DevVLV, DevHSW] {WA}: Every 4th PIPE_CONTROL command, not
counting the PIPE_CONTROL with only read-cache-invalidate bit(s) set,
must have a CS_STALL bit set"
For simplicity we simply set the CS_STALL bit on every pipe_control on
gen7+
Note that this massively helps on some hsw machines, together with the
following patch to unconditionally set the CS_STALL bit on every
pipe_control it prevents a gpu hang every few seconds.
This is a regression that has been introduced in the pipe_control
cleanup:
commit 6c6cf5aa9c583478b19e23149feaa92d01fb8c2d
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date: Fri Jul 20 18:02:28 2012 +0100
drm/i915: Only apply the SNB pipe control w/a to gen6
It looks like the massive snb pipe_control workaround also papered
over any issues on ivb and hsw.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
[danvet: squashed both workarounds together, pimped commit message
with Bsepc citations, regression commit citation and changed the
comment in the code a bit to clarify that we unconditionally set
CS_STALL to avoid being hurt by trying to be clever.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-08-17 21:35:43 +00:00
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static int
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2015-05-29 16:43:58 +00:00
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gen7_render_ring_cs_stall_wa(struct drm_i915_gem_request *req)
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drm/i915: add workarounds to gen7_render_ring_flush
From Bspec, Vol 2a, Section 1.9.3.4 "PIPE_CONTROL", intro section
detailing the various workarounds:
"[DevIVB {W/A}, DevHSW {W/A}]: Pipe_control with CS-stall bit
set must be issued before a pipe-control command that has the State
Cache Invalidate bit set."
Note that public Bspec has different numbering, it's Vol2Part1,
Section 1.10.4.1 "PIPE_CONTROL" there.
There's also a second workaround for the PIPE_CONTROL command itself:
"[DevIVB, DevVLV, DevHSW] {WA}: Every 4th PIPE_CONTROL command, not
counting the PIPE_CONTROL with only read-cache-invalidate bit(s) set,
must have a CS_STALL bit set"
For simplicity we simply set the CS_STALL bit on every pipe_control on
gen7+
Note that this massively helps on some hsw machines, together with the
following patch to unconditionally set the CS_STALL bit on every
pipe_control it prevents a gpu hang every few seconds.
This is a regression that has been introduced in the pipe_control
cleanup:
commit 6c6cf5aa9c583478b19e23149feaa92d01fb8c2d
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date: Fri Jul 20 18:02:28 2012 +0100
drm/i915: Only apply the SNB pipe control w/a to gen6
It looks like the massive snb pipe_control workaround also papered
over any issues on ivb and hsw.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
[danvet: squashed both workarounds together, pimped commit message
with Bsepc citations, regression commit citation and changed the
comment in the code a bit to clarify that we unconditionally set
CS_STALL to avoid being hurt by trying to be clever.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-08-17 21:35:43 +00:00
|
|
|
{
|
2017-02-14 11:32:42 +00:00
|
|
|
u32 *cs;
|
drm/i915: add workarounds to gen7_render_ring_flush
From Bspec, Vol 2a, Section 1.9.3.4 "PIPE_CONTROL", intro section
detailing the various workarounds:
"[DevIVB {W/A}, DevHSW {W/A}]: Pipe_control with CS-stall bit
set must be issued before a pipe-control command that has the State
Cache Invalidate bit set."
Note that public Bspec has different numbering, it's Vol2Part1,
Section 1.10.4.1 "PIPE_CONTROL" there.
There's also a second workaround for the PIPE_CONTROL command itself:
"[DevIVB, DevVLV, DevHSW] {WA}: Every 4th PIPE_CONTROL command, not
counting the PIPE_CONTROL with only read-cache-invalidate bit(s) set,
must have a CS_STALL bit set"
For simplicity we simply set the CS_STALL bit on every pipe_control on
gen7+
Note that this massively helps on some hsw machines, together with the
following patch to unconditionally set the CS_STALL bit on every
pipe_control it prevents a gpu hang every few seconds.
This is a regression that has been introduced in the pipe_control
cleanup:
commit 6c6cf5aa9c583478b19e23149feaa92d01fb8c2d
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date: Fri Jul 20 18:02:28 2012 +0100
drm/i915: Only apply the SNB pipe control w/a to gen6
It looks like the massive snb pipe_control workaround also papered
over any issues on ivb and hsw.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
[danvet: squashed both workarounds together, pimped commit message
with Bsepc citations, regression commit citation and changed the
comment in the code a bit to clarify that we unconditionally set
CS_STALL to avoid being hurt by trying to be clever.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-08-17 21:35:43 +00:00
|
|
|
|
2017-02-14 11:32:42 +00:00
|
|
|
cs = intel_ring_begin(req, 4);
|
|
|
|
if (IS_ERR(cs))
|
|
|
|
return PTR_ERR(cs);
|
drm/i915: add workarounds to gen7_render_ring_flush
From Bspec, Vol 2a, Section 1.9.3.4 "PIPE_CONTROL", intro section
detailing the various workarounds:
"[DevIVB {W/A}, DevHSW {W/A}]: Pipe_control with CS-stall bit
set must be issued before a pipe-control command that has the State
Cache Invalidate bit set."
Note that public Bspec has different numbering, it's Vol2Part1,
Section 1.10.4.1 "PIPE_CONTROL" there.
There's also a second workaround for the PIPE_CONTROL command itself:
"[DevIVB, DevVLV, DevHSW] {WA}: Every 4th PIPE_CONTROL command, not
counting the PIPE_CONTROL with only read-cache-invalidate bit(s) set,
must have a CS_STALL bit set"
For simplicity we simply set the CS_STALL bit on every pipe_control on
gen7+
Note that this massively helps on some hsw machines, together with the
following patch to unconditionally set the CS_STALL bit on every
pipe_control it prevents a gpu hang every few seconds.
This is a regression that has been introduced in the pipe_control
cleanup:
commit 6c6cf5aa9c583478b19e23149feaa92d01fb8c2d
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date: Fri Jul 20 18:02:28 2012 +0100
drm/i915: Only apply the SNB pipe control w/a to gen6
It looks like the massive snb pipe_control workaround also papered
over any issues on ivb and hsw.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
[danvet: squashed both workarounds together, pimped commit message
with Bsepc citations, regression commit citation and changed the
comment in the code a bit to clarify that we unconditionally set
CS_STALL to avoid being hurt by trying to be clever.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-08-17 21:35:43 +00:00
|
|
|
|
2017-02-14 11:32:42 +00:00
|
|
|
*cs++ = GFX_OP_PIPE_CONTROL(4);
|
|
|
|
*cs++ = PIPE_CONTROL_CS_STALL | PIPE_CONTROL_STALL_AT_SCOREBOARD;
|
|
|
|
*cs++ = 0;
|
|
|
|
*cs++ = 0;
|
|
|
|
intel_ring_advance(req, cs);
|
drm/i915: add workarounds to gen7_render_ring_flush
From Bspec, Vol 2a, Section 1.9.3.4 "PIPE_CONTROL", intro section
detailing the various workarounds:
"[DevIVB {W/A}, DevHSW {W/A}]: Pipe_control with CS-stall bit
set must be issued before a pipe-control command that has the State
Cache Invalidate bit set."
Note that public Bspec has different numbering, it's Vol2Part1,
Section 1.10.4.1 "PIPE_CONTROL" there.
There's also a second workaround for the PIPE_CONTROL command itself:
"[DevIVB, DevVLV, DevHSW] {WA}: Every 4th PIPE_CONTROL command, not
counting the PIPE_CONTROL with only read-cache-invalidate bit(s) set,
must have a CS_STALL bit set"
For simplicity we simply set the CS_STALL bit on every pipe_control on
gen7+
Note that this massively helps on some hsw machines, together with the
following patch to unconditionally set the CS_STALL bit on every
pipe_control it prevents a gpu hang every few seconds.
This is a regression that has been introduced in the pipe_control
cleanup:
commit 6c6cf5aa9c583478b19e23149feaa92d01fb8c2d
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date: Fri Jul 20 18:02:28 2012 +0100
drm/i915: Only apply the SNB pipe control w/a to gen6
It looks like the massive snb pipe_control workaround also papered
over any issues on ivb and hsw.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
[danvet: squashed both workarounds together, pimped commit message
with Bsepc citations, regression commit citation and changed the
comment in the code a bit to clarify that we unconditionally set
CS_STALL to avoid being hurt by trying to be clever.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-08-17 21:35:43 +00:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2012-08-17 21:35:41 +00:00
|
|
|
static int
|
2016-08-02 21:50:25 +00:00
|
|
|
gen7_render_ring_flush(struct drm_i915_gem_request *req, u32 mode)
|
2012-08-17 21:35:41 +00:00
|
|
|
{
|
2016-08-02 21:50:18 +00:00
|
|
|
u32 scratch_addr =
|
2016-08-15 09:49:07 +00:00
|
|
|
i915_ggtt_offset(req->engine->scratch) + 2 * CACHELINE_BYTES;
|
2017-02-14 11:32:42 +00:00
|
|
|
u32 *cs, flags = 0;
|
2012-08-17 21:35:41 +00:00
|
|
|
|
drm/i915: add workarounds to gen7_render_ring_flush
From Bspec, Vol 2a, Section 1.9.3.4 "PIPE_CONTROL", intro section
detailing the various workarounds:
"[DevIVB {W/A}, DevHSW {W/A}]: Pipe_control with CS-stall bit
set must be issued before a pipe-control command that has the State
Cache Invalidate bit set."
Note that public Bspec has different numbering, it's Vol2Part1,
Section 1.10.4.1 "PIPE_CONTROL" there.
There's also a second workaround for the PIPE_CONTROL command itself:
"[DevIVB, DevVLV, DevHSW] {WA}: Every 4th PIPE_CONTROL command, not
counting the PIPE_CONTROL with only read-cache-invalidate bit(s) set,
must have a CS_STALL bit set"
For simplicity we simply set the CS_STALL bit on every pipe_control on
gen7+
Note that this massively helps on some hsw machines, together with the
following patch to unconditionally set the CS_STALL bit on every
pipe_control it prevents a gpu hang every few seconds.
This is a regression that has been introduced in the pipe_control
cleanup:
commit 6c6cf5aa9c583478b19e23149feaa92d01fb8c2d
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date: Fri Jul 20 18:02:28 2012 +0100
drm/i915: Only apply the SNB pipe control w/a to gen6
It looks like the massive snb pipe_control workaround also papered
over any issues on ivb and hsw.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
[danvet: squashed both workarounds together, pimped commit message
with Bsepc citations, regression commit citation and changed the
comment in the code a bit to clarify that we unconditionally set
CS_STALL to avoid being hurt by trying to be clever.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-08-17 21:35:43 +00:00
|
|
|
/*
|
|
|
|
* Ensure that any following seqno writes only happen when the render
|
|
|
|
* cache is indeed flushed.
|
|
|
|
*
|
|
|
|
* Workaround: 4th PIPE_CONTROL command (except the ones with only
|
|
|
|
* read-cache invalidate bits set) must have the CS_STALL bit set. We
|
|
|
|
* don't try to be clever and just set it unconditionally.
|
|
|
|
*/
|
|
|
|
flags |= PIPE_CONTROL_CS_STALL;
|
|
|
|
|
2012-08-17 21:35:41 +00:00
|
|
|
/* Just flush everything. Experiments have shown that reducing the
|
|
|
|
* number of bits based on the write domains has little performance
|
|
|
|
* impact.
|
|
|
|
*/
|
2016-08-02 21:50:25 +00:00
|
|
|
if (mode & EMIT_FLUSH) {
|
2012-08-17 21:35:41 +00:00
|
|
|
flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
|
|
|
|
flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
|
2016-01-14 02:59:39 +00:00
|
|
|
flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
|
2015-08-21 15:08:41 +00:00
|
|
|
flags |= PIPE_CONTROL_FLUSH_ENABLE;
|
2012-08-17 21:35:41 +00:00
|
|
|
}
|
2016-08-02 21:50:25 +00:00
|
|
|
if (mode & EMIT_INVALIDATE) {
|
2012-08-17 21:35:41 +00:00
|
|
|
flags |= PIPE_CONTROL_TLB_INVALIDATE;
|
|
|
|
flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
|
|
|
|
flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
|
|
|
|
flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
|
|
|
|
flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
|
|
|
|
flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
|
2014-12-16 08:44:31 +00:00
|
|
|
flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR;
|
2012-08-17 21:35:41 +00:00
|
|
|
/*
|
|
|
|
* TLB invalidate requires a post-sync write.
|
|
|
|
*/
|
|
|
|
flags |= PIPE_CONTROL_QW_WRITE;
|
2013-02-14 19:53:51 +00:00
|
|
|
flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
|
drm/i915: add workarounds to gen7_render_ring_flush
From Bspec, Vol 2a, Section 1.9.3.4 "PIPE_CONTROL", intro section
detailing the various workarounds:
"[DevIVB {W/A}, DevHSW {W/A}]: Pipe_control with CS-stall bit
set must be issued before a pipe-control command that has the State
Cache Invalidate bit set."
Note that public Bspec has different numbering, it's Vol2Part1,
Section 1.10.4.1 "PIPE_CONTROL" there.
There's also a second workaround for the PIPE_CONTROL command itself:
"[DevIVB, DevVLV, DevHSW] {WA}: Every 4th PIPE_CONTROL command, not
counting the PIPE_CONTROL with only read-cache-invalidate bit(s) set,
must have a CS_STALL bit set"
For simplicity we simply set the CS_STALL bit on every pipe_control on
gen7+
Note that this massively helps on some hsw machines, together with the
following patch to unconditionally set the CS_STALL bit on every
pipe_control it prevents a gpu hang every few seconds.
This is a regression that has been introduced in the pipe_control
cleanup:
commit 6c6cf5aa9c583478b19e23149feaa92d01fb8c2d
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date: Fri Jul 20 18:02:28 2012 +0100
drm/i915: Only apply the SNB pipe control w/a to gen6
It looks like the massive snb pipe_control workaround also papered
over any issues on ivb and hsw.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
[danvet: squashed both workarounds together, pimped commit message
with Bsepc citations, regression commit citation and changed the
comment in the code a bit to clarify that we unconditionally set
CS_STALL to avoid being hurt by trying to be clever.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-08-17 21:35:43 +00:00
|
|
|
|
2014-12-16 08:44:32 +00:00
|
|
|
flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
|
|
|
|
|
drm/i915: add workarounds to gen7_render_ring_flush
From Bspec, Vol 2a, Section 1.9.3.4 "PIPE_CONTROL", intro section
detailing the various workarounds:
"[DevIVB {W/A}, DevHSW {W/A}]: Pipe_control with CS-stall bit
set must be issued before a pipe-control command that has the State
Cache Invalidate bit set."
Note that public Bspec has different numbering, it's Vol2Part1,
Section 1.10.4.1 "PIPE_CONTROL" there.
There's also a second workaround for the PIPE_CONTROL command itself:
"[DevIVB, DevVLV, DevHSW] {WA}: Every 4th PIPE_CONTROL command, not
counting the PIPE_CONTROL with only read-cache-invalidate bit(s) set,
must have a CS_STALL bit set"
For simplicity we simply set the CS_STALL bit on every pipe_control on
gen7+
Note that this massively helps on some hsw machines, together with the
following patch to unconditionally set the CS_STALL bit on every
pipe_control it prevents a gpu hang every few seconds.
This is a regression that has been introduced in the pipe_control
cleanup:
commit 6c6cf5aa9c583478b19e23149feaa92d01fb8c2d
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date: Fri Jul 20 18:02:28 2012 +0100
drm/i915: Only apply the SNB pipe control w/a to gen6
It looks like the massive snb pipe_control workaround also papered
over any issues on ivb and hsw.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
[danvet: squashed both workarounds together, pimped commit message
with Bsepc citations, regression commit citation and changed the
comment in the code a bit to clarify that we unconditionally set
CS_STALL to avoid being hurt by trying to be clever.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-08-17 21:35:43 +00:00
|
|
|
/* Workaround: we must issue a pipe_control with CS-stall bit
|
|
|
|
* set before a pipe_control command that has the state cache
|
|
|
|
* invalidate bit set. */
|
2015-05-29 16:43:58 +00:00
|
|
|
gen7_render_ring_cs_stall_wa(req);
|
2012-08-17 21:35:41 +00:00
|
|
|
}
|
|
|
|
|
2017-02-14 11:32:42 +00:00
|
|
|
cs = intel_ring_begin(req, 4);
|
|
|
|
if (IS_ERR(cs))
|
|
|
|
return PTR_ERR(cs);
|
2012-08-17 21:35:41 +00:00
|
|
|
|
2017-02-14 11:32:42 +00:00
|
|
|
*cs++ = GFX_OP_PIPE_CONTROL(4);
|
|
|
|
*cs++ = flags;
|
|
|
|
*cs++ = scratch_addr;
|
|
|
|
*cs++ = 0;
|
|
|
|
intel_ring_advance(req, cs);
|
2012-08-17 21:35:41 +00:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2014-06-27 23:04:20 +00:00
|
|
|
static int
|
2017-02-16 12:23:25 +00:00
|
|
|
gen8_render_ring_flush(struct drm_i915_gem_request *req, u32 mode)
|
2014-06-27 23:04:20 +00:00
|
|
|
{
|
2017-02-16 12:23:25 +00:00
|
|
|
u32 flags;
|
2017-02-14 11:32:42 +00:00
|
|
|
u32 *cs;
|
2014-06-27 23:04:20 +00:00
|
|
|
|
2017-02-16 12:23:25 +00:00
|
|
|
cs = intel_ring_begin(req, mode & EMIT_INVALIDATE ? 12 : 6);
|
2017-02-14 11:32:42 +00:00
|
|
|
if (IS_ERR(cs))
|
|
|
|
return PTR_ERR(cs);
|
2014-06-27 23:04:20 +00:00
|
|
|
|
2017-02-16 12:23:25 +00:00
|
|
|
flags = PIPE_CONTROL_CS_STALL;
|
2013-11-03 04:07:27 +00:00
|
|
|
|
2016-08-02 21:50:25 +00:00
|
|
|
if (mode & EMIT_FLUSH) {
|
2013-11-03 04:07:27 +00:00
|
|
|
flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
|
|
|
|
flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
|
2016-01-14 02:59:39 +00:00
|
|
|
flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
|
2015-08-21 15:08:41 +00:00
|
|
|
flags |= PIPE_CONTROL_FLUSH_ENABLE;
|
2013-11-03 04:07:27 +00:00
|
|
|
}
|
2016-08-02 21:50:25 +00:00
|
|
|
if (mode & EMIT_INVALIDATE) {
|
2013-11-03 04:07:27 +00:00
|
|
|
flags |= PIPE_CONTROL_TLB_INVALIDATE;
|
|
|
|
flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
|
|
|
|
flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
|
|
|
|
flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
|
|
|
|
flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
|
|
|
|
flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
|
|
|
|
flags |= PIPE_CONTROL_QW_WRITE;
|
|
|
|
flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
|
2014-01-27 22:20:16 +00:00
|
|
|
|
|
|
|
/* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
|
2017-02-16 12:23:25 +00:00
|
|
|
cs = gen8_emit_pipe_control(cs,
|
|
|
|
PIPE_CONTROL_CS_STALL |
|
|
|
|
PIPE_CONTROL_STALL_AT_SCOREBOARD,
|
|
|
|
0);
|
2013-11-03 04:07:27 +00:00
|
|
|
}
|
|
|
|
|
2017-02-16 12:23:25 +00:00
|
|
|
cs = gen8_emit_pipe_control(cs, flags,
|
|
|
|
i915_ggtt_offset(req->engine->scratch) +
|
|
|
|
2 * CACHELINE_BYTES);
|
|
|
|
|
|
|
|
intel_ring_advance(req, cs);
|
|
|
|
|
|
|
|
return 0;
|
2013-11-03 04:07:27 +00:00
|
|
|
}
|
|
|
|
|
2016-03-16 11:00:37 +00:00
|
|
|
static void ring_setup_phys_status_page(struct intel_engine_cs *engine)
|
2013-07-03 10:56:54 +00:00
|
|
|
{
|
2016-05-06 14:40:21 +00:00
|
|
|
struct drm_i915_private *dev_priv = engine->i915;
|
2013-07-03 10:56:54 +00:00
|
|
|
u32 addr;
|
|
|
|
|
|
|
|
addr = dev_priv->status_page_dmah->busaddr;
|
2016-05-06 14:40:21 +00:00
|
|
|
if (INTEL_GEN(dev_priv) >= 4)
|
2013-07-03 10:56:54 +00:00
|
|
|
addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
|
|
|
|
I915_WRITE(HWS_PGA, addr);
|
|
|
|
}
|
|
|
|
|
2016-03-16 11:00:37 +00:00
|
|
|
static void intel_ring_setup_status_page(struct intel_engine_cs *engine)
|
2015-02-10 19:32:17 +00:00
|
|
|
{
|
2016-05-06 14:40:21 +00:00
|
|
|
struct drm_i915_private *dev_priv = engine->i915;
|
drm/i915: Type safe register read/write
Make I915_READ and I915_WRITE more type safe by wrapping the register
offset in a struct. This should eliminate most of the fumbles we've had
with misplaced parens.
This only takes care of normal mmio registers. We could extend the idea
to other register types and define each with its own struct. That way
you wouldn't be able to accidentally pass the wrong thing to a specific
register access function.
The gpio_reg setup is probably the ugliest thing left. But I figure I'd
just leave it for now, and wait for some divine inspiration to strike
before making it nice.
As for the generated code, it's actually a bit better sometimes. Eg.
looking at i915_irq_handler(), we can see the following change:
lea 0x70024(%rdx,%rax,1),%r9d
mov $0x1,%edx
- movslq %r9d,%r9
- mov %r9,%rsi
- mov %r9,-0x58(%rbp)
- callq *0xd8(%rbx)
+ mov %r9d,%esi
+ mov %r9d,-0x48(%rbp)
callq *0xd8(%rbx)
So previously gcc thought the register offset might be signed and
decided to sign extend it, just in case. The rest appears to be
mostly just minor shuffling of instructions.
v2: i915_mmio_reg_{offset,equal,valid}() helpers added
s/_REG/_MMIO/ in the register defines
mo more switch statements left to worry about
ring_emit stuff got sorted in a prep patch
cmd parser, lrc context and w/a batch buildup also in prep patch
vgpu stuff cleaned up and moved to a prep patch
all other unrelated changes split out
v3: Rebased due to BXT DSI/BLC, MOCS, etc.
v4: Rebased due to churn, s/i915_mmio_reg_t/i915_reg_t/
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/1447853606-2751-1-git-send-email-ville.syrjala@linux.intel.com
2015-11-18 13:33:26 +00:00
|
|
|
i915_reg_t mmio;
|
2015-02-10 19:32:17 +00:00
|
|
|
|
|
|
|
/* The ring status page addresses are no longer next to the rest of
|
|
|
|
* the ring registers as of gen7.
|
|
|
|
*/
|
2016-05-06 14:40:21 +00:00
|
|
|
if (IS_GEN7(dev_priv)) {
|
2016-03-16 11:00:37 +00:00
|
|
|
switch (engine->id) {
|
2015-02-10 19:32:17 +00:00
|
|
|
case RCS:
|
|
|
|
mmio = RENDER_HWS_PGA_GEN7;
|
|
|
|
break;
|
|
|
|
case BCS:
|
|
|
|
mmio = BLT_HWS_PGA_GEN7;
|
|
|
|
break;
|
|
|
|
/*
|
|
|
|
* VCS2 actually doesn't exist on Gen7. Only shut up
|
|
|
|
* gcc switch check warning
|
|
|
|
*/
|
|
|
|
case VCS2:
|
|
|
|
case VCS:
|
|
|
|
mmio = BSD_HWS_PGA_GEN7;
|
|
|
|
break;
|
|
|
|
case VECS:
|
|
|
|
mmio = VEBOX_HWS_PGA_GEN7;
|
|
|
|
break;
|
|
|
|
}
|
2016-05-06 14:40:21 +00:00
|
|
|
} else if (IS_GEN6(dev_priv)) {
|
2016-03-16 11:00:37 +00:00
|
|
|
mmio = RING_HWS_PGA_GEN6(engine->mmio_base);
|
2015-02-10 19:32:17 +00:00
|
|
|
} else {
|
|
|
|
/* XXX: gen8 returns to sanity */
|
2016-03-16 11:00:37 +00:00
|
|
|
mmio = RING_HWS_PGA(engine->mmio_base);
|
2015-02-10 19:32:17 +00:00
|
|
|
}
|
|
|
|
|
2016-08-15 09:48:57 +00:00
|
|
|
I915_WRITE(mmio, engine->status_page.ggtt_offset);
|
2015-02-10 19:32:17 +00:00
|
|
|
POSTING_READ(mmio);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Flush the TLB for this page
|
|
|
|
*
|
|
|
|
* FIXME: These two bits have disappeared on gen8, so a question
|
|
|
|
* arises: do we still need this and if so how should we go about
|
|
|
|
* invalidating the TLB?
|
|
|
|
*/
|
2016-05-10 09:57:08 +00:00
|
|
|
if (IS_GEN(dev_priv, 6, 7)) {
|
2016-03-16 11:00:37 +00:00
|
|
|
i915_reg_t reg = RING_INSTPM(engine->mmio_base);
|
2015-02-10 19:32:17 +00:00
|
|
|
|
|
|
|
/* ring should be idle before issuing a sync flush*/
|
2016-03-16 11:00:37 +00:00
|
|
|
WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0);
|
2015-02-10 19:32:17 +00:00
|
|
|
|
|
|
|
I915_WRITE(reg,
|
|
|
|
_MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
|
|
|
|
INSTPM_SYNC_FLUSH));
|
2016-06-30 14:33:29 +00:00
|
|
|
if (intel_wait_for_register(dev_priv,
|
|
|
|
reg, INSTPM_SYNC_FLUSH, 0,
|
|
|
|
1000))
|
2015-02-10 19:32:17 +00:00
|
|
|
DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
|
2016-03-16 11:00:37 +00:00
|
|
|
engine->name);
|
2015-02-10 19:32:17 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2016-03-16 11:00:37 +00:00
|
|
|
static bool stop_ring(struct intel_engine_cs *engine)
|
2010-05-21 01:08:55 +00:00
|
|
|
{
|
2016-05-06 14:40:21 +00:00
|
|
|
struct drm_i915_private *dev_priv = engine->i915;
|
2010-05-21 01:08:55 +00:00
|
|
|
|
2016-08-15 09:49:11 +00:00
|
|
|
if (INTEL_GEN(dev_priv) > 2) {
|
2016-03-16 11:00:37 +00:00
|
|
|
I915_WRITE_MODE(engine, _MASKED_BIT_ENABLE(STOP_RING));
|
2016-06-30 14:33:30 +00:00
|
|
|
if (intel_wait_for_register(dev_priv,
|
|
|
|
RING_MI_MODE(engine->mmio_base),
|
|
|
|
MODE_IDLE,
|
|
|
|
MODE_IDLE,
|
|
|
|
1000)) {
|
2016-03-16 11:00:37 +00:00
|
|
|
DRM_ERROR("%s : timed out trying to stop ring\n",
|
|
|
|
engine->name);
|
2014-08-11 08:21:35 +00:00
|
|
|
/* Sometimes we observe that the idle flag is not
|
|
|
|
* set even though the ring is empty. So double
|
|
|
|
* check before giving up.
|
|
|
|
*/
|
2016-03-16 11:00:37 +00:00
|
|
|
if (I915_READ_HEAD(engine) != I915_READ_TAIL(engine))
|
2014-08-11 08:21:35 +00:00
|
|
|
return false;
|
2014-04-02 15:36:07 +00:00
|
|
|
}
|
|
|
|
}
|
2012-06-04 09:18:15 +00:00
|
|
|
|
2016-03-16 11:00:37 +00:00
|
|
|
I915_WRITE_CTL(engine, 0);
|
|
|
|
I915_WRITE_HEAD(engine, 0);
|
2016-08-02 21:50:29 +00:00
|
|
|
I915_WRITE_TAIL(engine, 0);
|
2010-05-21 01:08:55 +00:00
|
|
|
|
2016-08-15 09:49:11 +00:00
|
|
|
if (INTEL_GEN(dev_priv) > 2) {
|
2016-03-16 11:00:37 +00:00
|
|
|
(void)I915_READ_CTL(engine);
|
|
|
|
I915_WRITE_MODE(engine, _MASKED_BIT_DISABLE(STOP_RING));
|
2014-04-02 15:36:07 +00:00
|
|
|
}
|
2014-03-12 11:09:40 +00:00
|
|
|
|
2016-03-16 11:00:37 +00:00
|
|
|
return (I915_READ_HEAD(engine) & HEAD_ADDR) == 0;
|
2014-04-02 15:36:07 +00:00
|
|
|
}
|
2010-05-21 01:08:55 +00:00
|
|
|
|
2016-03-16 11:00:37 +00:00
|
|
|
static int init_ring_common(struct intel_engine_cs *engine)
|
2014-04-02 15:36:07 +00:00
|
|
|
{
|
2016-05-06 14:40:21 +00:00
|
|
|
struct drm_i915_private *dev_priv = engine->i915;
|
2016-08-02 21:50:21 +00:00
|
|
|
struct intel_ring *ring = engine->buffer;
|
2014-04-02 15:36:07 +00:00
|
|
|
int ret = 0;
|
|
|
|
|
2015-01-16 09:34:40 +00:00
|
|
|
intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
|
2014-04-02 15:36:07 +00:00
|
|
|
|
2016-03-16 11:00:37 +00:00
|
|
|
if (!stop_ring(engine)) {
|
2014-04-02 15:36:07 +00:00
|
|
|
/* G45 ring initialization often fails to reset head to zero */
|
2010-12-05 20:42:33 +00:00
|
|
|
DRM_DEBUG_KMS("%s head not reset to zero "
|
|
|
|
"ctl %08x head %08x tail %08x start %08x\n",
|
2016-03-16 11:00:37 +00:00
|
|
|
engine->name,
|
|
|
|
I915_READ_CTL(engine),
|
|
|
|
I915_READ_HEAD(engine),
|
|
|
|
I915_READ_TAIL(engine),
|
|
|
|
I915_READ_START(engine));
|
2010-05-21 01:08:55 +00:00
|
|
|
|
2016-03-16 11:00:37 +00:00
|
|
|
if (!stop_ring(engine)) {
|
2010-12-05 20:42:33 +00:00
|
|
|
DRM_ERROR("failed to set %s head to zero "
|
|
|
|
"ctl %08x head %08x tail %08x start %08x\n",
|
2016-03-16 11:00:37 +00:00
|
|
|
engine->name,
|
|
|
|
I915_READ_CTL(engine),
|
|
|
|
I915_READ_HEAD(engine),
|
|
|
|
I915_READ_TAIL(engine),
|
|
|
|
I915_READ_START(engine));
|
2014-04-02 15:36:07 +00:00
|
|
|
ret = -EIO;
|
|
|
|
goto out;
|
2010-12-05 20:42:33 +00:00
|
|
|
}
|
2010-05-21 01:08:55 +00:00
|
|
|
}
|
|
|
|
|
2016-08-17 19:30:56 +00:00
|
|
|
if (HWS_NEEDS_PHYSICAL(dev_priv))
|
2016-03-16 11:00:37 +00:00
|
|
|
ring_setup_phys_status_page(engine);
|
2016-08-17 19:30:56 +00:00
|
|
|
else
|
|
|
|
intel_ring_setup_status_page(engine);
|
2014-04-02 15:36:07 +00:00
|
|
|
|
2016-10-07 06:53:26 +00:00
|
|
|
intel_engine_reset_breadcrumbs(engine);
|
2016-09-09 13:11:53 +00:00
|
|
|
|
2014-08-07 14:29:53 +00:00
|
|
|
/* Enforce ordering by reading HEAD register back */
|
2016-03-16 11:00:37 +00:00
|
|
|
I915_READ_HEAD(engine);
|
2014-08-07 14:29:53 +00:00
|
|
|
|
2012-08-07 07:54:14 +00:00
|
|
|
/* Initialize the ring. This must happen _after_ we've cleared the ring
|
|
|
|
* registers with the above sequence (the readback of the HEAD registers
|
|
|
|
* also enforces ordering), otherwise the hw might lose the new ring
|
|
|
|
* register values. */
|
2016-08-15 09:49:07 +00:00
|
|
|
I915_WRITE_START(engine, i915_ggtt_offset(ring->vma));
|
2014-08-07 14:39:54 +00:00
|
|
|
|
|
|
|
/* WaClearRingBufHeadRegAtInit:ctg,elk */
|
2016-03-16 11:00:37 +00:00
|
|
|
if (I915_READ_HEAD(engine))
|
2014-08-07 14:39:54 +00:00
|
|
|
DRM_DEBUG("%s initialization failed [head=%08x], fudging\n",
|
2016-03-16 11:00:37 +00:00
|
|
|
engine->name, I915_READ_HEAD(engine));
|
2016-09-09 13:11:53 +00:00
|
|
|
|
|
|
|
intel_ring_update_space(ring);
|
|
|
|
I915_WRITE_HEAD(engine, ring->head);
|
|
|
|
I915_WRITE_TAIL(engine, ring->tail);
|
|
|
|
(void)I915_READ_TAIL(engine);
|
2014-08-07 14:39:54 +00:00
|
|
|
|
2016-10-04 20:11:25 +00:00
|
|
|
I915_WRITE_CTL(engine, RING_CTL_SIZE(ring->size) | RING_VALID);
|
2010-05-21 01:08:55 +00:00
|
|
|
|
|
|
|
/* If the head is still not zero, the ring is dead */
|
2017-04-11 10:13:40 +00:00
|
|
|
if (intel_wait_for_register(dev_priv, RING_CTL(engine->mmio_base),
|
|
|
|
RING_VALID, RING_VALID,
|
|
|
|
50)) {
|
2010-11-09 10:16:56 +00:00
|
|
|
DRM_ERROR("%s initialization failed "
|
2016-09-09 13:11:53 +00:00
|
|
|
"ctl %08x (valid? %d) head %08x [%08x] tail %08x [%08x] start %08x [expected %08x]\n",
|
2016-03-16 11:00:37 +00:00
|
|
|
engine->name,
|
|
|
|
I915_READ_CTL(engine),
|
|
|
|
I915_READ_CTL(engine) & RING_VALID,
|
2016-09-09 13:11:53 +00:00
|
|
|
I915_READ_HEAD(engine), ring->head,
|
|
|
|
I915_READ_TAIL(engine), ring->tail,
|
2016-03-16 11:00:37 +00:00
|
|
|
I915_READ_START(engine),
|
2016-08-15 09:49:07 +00:00
|
|
|
i915_ggtt_offset(ring->vma));
|
2012-06-04 09:18:15 +00:00
|
|
|
ret = -EIO;
|
|
|
|
goto out;
|
2010-05-21 01:08:55 +00:00
|
|
|
}
|
|
|
|
|
2016-03-21 16:26:59 +00:00
|
|
|
intel_engine_init_hangcheck(engine);
|
2013-06-10 10:20:19 +00:00
|
|
|
|
2012-06-04 09:18:15 +00:00
|
|
|
out:
|
2015-01-16 09:34:40 +00:00
|
|
|
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
|
2012-06-04 09:18:15 +00:00
|
|
|
|
|
|
|
return ret;
|
2010-05-21 01:08:55 +00:00
|
|
|
}
|
|
|
|
|
2016-09-09 13:11:53 +00:00
|
|
|
static void reset_ring_common(struct intel_engine_cs *engine,
|
|
|
|
struct drm_i915_gem_request *request)
|
|
|
|
{
|
2017-02-07 15:24:37 +00:00
|
|
|
/* Try to restore the logical GPU state to match the continuation
|
|
|
|
* of the request queue. If we skip the context/PD restore, then
|
|
|
|
* the next request may try to execute assuming that its context
|
|
|
|
* is valid and loaded on the GPU and so may try to access invalid
|
|
|
|
* memory, prompting repeated GPU hangs.
|
|
|
|
*
|
|
|
|
* If the request was guilty, we still restore the logical state
|
|
|
|
* in case the next request requires it (e.g. the aliasing ppgtt),
|
|
|
|
* but skip over the hung batch.
|
|
|
|
*
|
|
|
|
* If the request was innocent, we try to replay the request with
|
|
|
|
* the restored context.
|
|
|
|
*/
|
|
|
|
if (request) {
|
|
|
|
struct drm_i915_private *dev_priv = request->i915;
|
|
|
|
struct intel_context *ce = &request->ctx->engine[engine->id];
|
|
|
|
struct i915_hw_ppgtt *ppgtt;
|
|
|
|
|
|
|
|
/* FIXME consider gen8 reset */
|
|
|
|
|
|
|
|
if (ce->state) {
|
|
|
|
I915_WRITE(CCID,
|
|
|
|
i915_ggtt_offset(ce->state) |
|
|
|
|
BIT(8) /* must be set! */ |
|
|
|
|
CCID_EXTENDED_STATE_SAVE |
|
|
|
|
CCID_EXTENDED_STATE_RESTORE |
|
|
|
|
CCID_EN);
|
|
|
|
}
|
|
|
|
|
|
|
|
ppgtt = request->ctx->ppgtt ?: engine->i915->mm.aliasing_ppgtt;
|
|
|
|
if (ppgtt) {
|
|
|
|
u32 pd_offset = ppgtt->pd.base.ggtt_offset << 10;
|
|
|
|
|
|
|
|
I915_WRITE(RING_PP_DIR_DCLV(engine), PP_DIR_DCLV_2G);
|
|
|
|
I915_WRITE(RING_PP_DIR_BASE(engine), pd_offset);
|
|
|
|
|
|
|
|
/* Wait for the PD reload to complete */
|
|
|
|
if (intel_wait_for_register(dev_priv,
|
|
|
|
RING_PP_DIR_BASE(engine),
|
|
|
|
BIT(0), 0,
|
|
|
|
10))
|
|
|
|
DRM_ERROR("Wait for reload of ppgtt page-directory timed out\n");
|
2016-09-09 13:11:53 +00:00
|
|
|
|
2017-02-07 15:24:37 +00:00
|
|
|
ppgtt->pd_dirty_rings &= ~intel_engine_flag(engine);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* If the rq hung, jump to its breadcrumb and skip the batch */
|
2017-03-21 10:25:52 +00:00
|
|
|
if (request->fence.error == -EIO)
|
|
|
|
request->ring->head = request->postfix;
|
2017-02-07 15:24:37 +00:00
|
|
|
} else {
|
|
|
|
engine->legacy_active_context = NULL;
|
|
|
|
}
|
2016-09-09 13:11:53 +00:00
|
|
|
}
|
|
|
|
|
2015-05-29 16:43:44 +00:00
|
|
|
static int intel_rcs_ctx_init(struct drm_i915_gem_request *req)
|
2014-12-02 15:19:07 +00:00
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
|
2015-05-29 16:43:54 +00:00
|
|
|
ret = intel_ring_workarounds_emit(req);
|
2014-12-02 15:19:07 +00:00
|
|
|
if (ret != 0)
|
|
|
|
return ret;
|
|
|
|
|
2016-10-28 12:58:31 +00:00
|
|
|
ret = i915_gem_render_state_emit(req);
|
2014-12-02 15:19:07 +00:00
|
|
|
if (ret)
|
2016-01-29 16:49:05 +00:00
|
|
|
return ret;
|
2014-12-02 15:19:07 +00:00
|
|
|
|
2016-01-29 16:49:05 +00:00
|
|
|
return 0;
|
2014-12-02 15:19:07 +00:00
|
|
|
}
|
|
|
|
|
2016-03-16 11:00:37 +00:00
|
|
|
static int init_render_ring(struct intel_engine_cs *engine)
|
2010-05-21 01:08:55 +00:00
|
|
|
{
|
2016-05-06 14:40:21 +00:00
|
|
|
struct drm_i915_private *dev_priv = engine->i915;
|
2016-03-16 11:00:37 +00:00
|
|
|
int ret = init_ring_common(engine);
|
2014-06-19 17:07:15 +00:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
2010-08-30 08:12:42 +00:00
|
|
|
|
2014-03-25 12:31:50 +00:00
|
|
|
/* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
|
2016-05-10 09:57:08 +00:00
|
|
|
if (IS_GEN(dev_priv, 4, 6))
|
2012-04-24 12:04:12 +00:00
|
|
|
I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
|
2013-01-20 16:11:20 +00:00
|
|
|
|
|
|
|
/* We need to disable the AsyncFlip performance optimisations in order
|
|
|
|
* to use MI_WAIT_FOR_EVENT within the CS. It should already be
|
|
|
|
* programmed to '1' on all products.
|
2013-05-03 17:48:11 +00:00
|
|
|
*
|
2015-06-02 12:37:37 +00:00
|
|
|
* WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
|
2013-01-20 16:11:20 +00:00
|
|
|
*/
|
2016-05-10 09:57:08 +00:00
|
|
|
if (IS_GEN(dev_priv, 6, 7))
|
2013-01-20 16:11:20 +00:00
|
|
|
I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
|
|
|
|
|
2013-01-20 16:33:32 +00:00
|
|
|
/* Required for the hardware to program scanline values for waiting */
|
2014-03-24 17:30:04 +00:00
|
|
|
/* WaEnableFlushTlbInvalidationMode:snb */
|
2016-05-06 14:40:21 +00:00
|
|
|
if (IS_GEN6(dev_priv))
|
2013-01-20 16:33:32 +00:00
|
|
|
I915_WRITE(GFX_MODE,
|
2014-03-21 17:18:54 +00:00
|
|
|
_MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
|
2013-01-20 16:33:32 +00:00
|
|
|
|
2014-03-24 17:30:04 +00:00
|
|
|
/* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
|
2016-05-06 14:40:21 +00:00
|
|
|
if (IS_GEN7(dev_priv))
|
2013-01-20 16:11:20 +00:00
|
|
|
I915_WRITE(GFX_MODE_GEN7,
|
2014-03-24 17:30:04 +00:00
|
|
|
_MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
|
2013-01-20 16:11:20 +00:00
|
|
|
_MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
|
2010-10-27 11:18:21 +00:00
|
|
|
|
2016-05-06 14:40:21 +00:00
|
|
|
if (IS_GEN6(dev_priv)) {
|
2012-04-27 19:44:41 +00:00
|
|
|
/* From the Sandybridge PRM, volume 1 part 3, page 24:
|
|
|
|
* "If this bit is set, STCunit will have LRA as replacement
|
|
|
|
* policy. [...] This bit must be reset. LRA replacement
|
|
|
|
* policy is not supported."
|
|
|
|
*/
|
|
|
|
I915_WRITE(CACHE_MODE_0,
|
2012-05-08 11:39:59 +00:00
|
|
|
_MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
|
2011-12-13 03:21:58 +00:00
|
|
|
}
|
|
|
|
|
2016-05-10 09:57:08 +00:00
|
|
|
if (IS_GEN(dev_priv, 6, 7))
|
2012-04-24 12:04:12 +00:00
|
|
|
I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
|
2011-12-13 03:21:58 +00:00
|
|
|
|
2016-07-12 16:24:47 +00:00
|
|
|
if (INTEL_INFO(dev_priv)->gen >= 6)
|
|
|
|
I915_WRITE_IMR(engine, ~engine->irq_keep_mask);
|
2012-05-25 23:56:23 +00:00
|
|
|
|
2016-03-16 11:00:37 +00:00
|
|
|
return init_workarounds_ring(engine);
|
2010-05-21 01:08:55 +00:00
|
|
|
}
|
|
|
|
|
2016-03-16 11:00:37 +00:00
|
|
|
static void render_ring_cleanup(struct intel_engine_cs *engine)
|
2010-12-15 09:56:50 +00:00
|
|
|
{
|
2016-05-06 14:40:21 +00:00
|
|
|
struct drm_i915_private *dev_priv = engine->i915;
|
2014-06-30 16:53:37 +00:00
|
|
|
|
2016-08-15 09:49:05 +00:00
|
|
|
i915_vma_unpin_and_release(&dev_priv->semaphore);
|
2010-12-15 09:56:50 +00:00
|
|
|
}
|
|
|
|
|
2017-02-14 11:32:42 +00:00
|
|
|
static u32 *gen8_rcs_signal(struct drm_i915_gem_request *req, u32 *cs)
|
2014-06-30 16:53:37 +00:00
|
|
|
{
|
2016-08-02 21:50:40 +00:00
|
|
|
struct drm_i915_private *dev_priv = req->i915;
|
2014-06-30 16:53:37 +00:00
|
|
|
struct intel_engine_cs *waiter;
|
2016-03-23 18:19:53 +00:00
|
|
|
enum intel_engine_id id;
|
2014-06-30 16:53:37 +00:00
|
|
|
|
drm/i915: Allocate intel_engine_cs structure only for the enabled engines
With the possibility of addition of many more number of rings in future,
the drm_i915_private structure could bloat as an array, of type
intel_engine_cs, is embedded inside it.
struct intel_engine_cs engine[I915_NUM_ENGINES];
Though this is still fine as generally there is only a single instance of
drm_i915_private structure used, but not all of the possible rings would be
enabled or active on most of the platforms. Some memory can be saved by
allocating intel_engine_cs structure only for the enabled/active engines.
Currently the engine/ring ID is kept static and dev_priv->engine[] is simply
indexed using the enums defined in intel_engine_id.
To save memory and continue using the static engine/ring IDs, 'engine' is
defined as an array of pointers.
struct intel_engine_cs *engine[I915_NUM_ENGINES];
dev_priv->engine[engine_ID] will be NULL for disabled engine instances.
There is a text size reduction of 928 bytes, from 1028200 to 1027272, for
i915.o file (but for i915.ko file text size remain same as 1193131 bytes).
v2:
- Remove the engine iterator field added in drm_i915_private structure,
instead pass a local iterator variable to the for_each_engine**
macros. (Chris)
- Do away with intel_engine_initialized() and instead directly use the
NULL pointer check on engine pointer. (Chris)
v3:
- Remove for_each_engine_id() macro, as the updated macro for_each_engine()
can be used in place of it. (Chris)
- Protect the access to Render engine Fault register with a NULL check, as
engine specific init is done later in Driver load sequence.
v4:
- Use !!dev_priv->engine[VCS] style for the engine check in getparam. (Chris)
- Kill the superfluous init_engine_lists().
v5:
- Cleanup the intel_engines_init() & intel_engines_setup(), with respect to
allocation of intel_engine_cs structure. (Chris)
v6:
- Rebase.
v7:
- Optimize the for_each_engine_masked() macro. (Chris)
- Change the type of 'iter' local variable to enum intel_engine_id. (Chris)
- Rebase.
v8: Rebase.
v9: Rebase.
v10:
- For index calculation use engine ID instead of pointer based arithmetic in
intel_engine_sync_index() as engine pointers are not contiguous now (Chris)
- For appropriateness, rename local enum variable 'iter' to 'id'. (Joonas)
- Use for_each_engine macro for cleanup in intel_engines_init() and remove
check for NULL engine pointer in cleanup() routines. (Joonas)
v11: Rebase.
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Akash Goel <akash.goel@intel.com>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1476378888-7372-1-git-send-email-akash.goel@intel.com
2016-10-13 17:14:48 +00:00
|
|
|
for_each_engine(waiter, dev_priv, id) {
|
2016-08-02 21:50:40 +00:00
|
|
|
u64 gtt_offset = req->engine->semaphore.signal_ggtt[id];
|
2014-06-30 16:53:37 +00:00
|
|
|
if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
|
|
|
|
continue;
|
|
|
|
|
2017-02-14 11:32:42 +00:00
|
|
|
*cs++ = GFX_OP_PIPE_CONTROL(6);
|
|
|
|
*cs++ = PIPE_CONTROL_GLOBAL_GTT_IVB | PIPE_CONTROL_QW_WRITE |
|
|
|
|
PIPE_CONTROL_CS_STALL;
|
|
|
|
*cs++ = lower_32_bits(gtt_offset);
|
|
|
|
*cs++ = upper_32_bits(gtt_offset);
|
|
|
|
*cs++ = req->global_seqno;
|
|
|
|
*cs++ = 0;
|
|
|
|
*cs++ = MI_SEMAPHORE_SIGNAL |
|
|
|
|
MI_SEMAPHORE_TARGET(waiter->hw_id);
|
|
|
|
*cs++ = 0;
|
2014-06-30 16:53:37 +00:00
|
|
|
}
|
|
|
|
|
2017-02-14 11:32:42 +00:00
|
|
|
return cs;
|
2014-06-30 16:53:37 +00:00
|
|
|
}
|
|
|
|
|
2017-02-14 11:32:42 +00:00
|
|
|
static u32 *gen8_xcs_signal(struct drm_i915_gem_request *req, u32 *cs)
|
2014-06-30 16:53:37 +00:00
|
|
|
{
|
2016-08-02 21:50:40 +00:00
|
|
|
struct drm_i915_private *dev_priv = req->i915;
|
2014-06-30 16:53:37 +00:00
|
|
|
struct intel_engine_cs *waiter;
|
2016-03-23 18:19:53 +00:00
|
|
|
enum intel_engine_id id;
|
2014-06-30 16:53:37 +00:00
|
|
|
|
drm/i915: Allocate intel_engine_cs structure only for the enabled engines
With the possibility of addition of many more number of rings in future,
the drm_i915_private structure could bloat as an array, of type
intel_engine_cs, is embedded inside it.
struct intel_engine_cs engine[I915_NUM_ENGINES];
Though this is still fine as generally there is only a single instance of
drm_i915_private structure used, but not all of the possible rings would be
enabled or active on most of the platforms. Some memory can be saved by
allocating intel_engine_cs structure only for the enabled/active engines.
Currently the engine/ring ID is kept static and dev_priv->engine[] is simply
indexed using the enums defined in intel_engine_id.
To save memory and continue using the static engine/ring IDs, 'engine' is
defined as an array of pointers.
struct intel_engine_cs *engine[I915_NUM_ENGINES];
dev_priv->engine[engine_ID] will be NULL for disabled engine instances.
There is a text size reduction of 928 bytes, from 1028200 to 1027272, for
i915.o file (but for i915.ko file text size remain same as 1193131 bytes).
v2:
- Remove the engine iterator field added in drm_i915_private structure,
instead pass a local iterator variable to the for_each_engine**
macros. (Chris)
- Do away with intel_engine_initialized() and instead directly use the
NULL pointer check on engine pointer. (Chris)
v3:
- Remove for_each_engine_id() macro, as the updated macro for_each_engine()
can be used in place of it. (Chris)
- Protect the access to Render engine Fault register with a NULL check, as
engine specific init is done later in Driver load sequence.
v4:
- Use !!dev_priv->engine[VCS] style for the engine check in getparam. (Chris)
- Kill the superfluous init_engine_lists().
v5:
- Cleanup the intel_engines_init() & intel_engines_setup(), with respect to
allocation of intel_engine_cs structure. (Chris)
v6:
- Rebase.
v7:
- Optimize the for_each_engine_masked() macro. (Chris)
- Change the type of 'iter' local variable to enum intel_engine_id. (Chris)
- Rebase.
v8: Rebase.
v9: Rebase.
v10:
- For index calculation use engine ID instead of pointer based arithmetic in
intel_engine_sync_index() as engine pointers are not contiguous now (Chris)
- For appropriateness, rename local enum variable 'iter' to 'id'. (Joonas)
- Use for_each_engine macro for cleanup in intel_engines_init() and remove
check for NULL engine pointer in cleanup() routines. (Joonas)
v11: Rebase.
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Akash Goel <akash.goel@intel.com>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1476378888-7372-1-git-send-email-akash.goel@intel.com
2016-10-13 17:14:48 +00:00
|
|
|
for_each_engine(waiter, dev_priv, id) {
|
2016-08-02 21:50:40 +00:00
|
|
|
u64 gtt_offset = req->engine->semaphore.signal_ggtt[id];
|
2014-06-30 16:53:37 +00:00
|
|
|
if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
|
|
|
|
continue;
|
|
|
|
|
2017-02-14 11:32:42 +00:00
|
|
|
*cs++ = (MI_FLUSH_DW + 1) | MI_FLUSH_DW_OP_STOREDW;
|
|
|
|
*cs++ = lower_32_bits(gtt_offset) | MI_FLUSH_DW_USE_GTT;
|
|
|
|
*cs++ = upper_32_bits(gtt_offset);
|
|
|
|
*cs++ = req->global_seqno;
|
|
|
|
*cs++ = MI_SEMAPHORE_SIGNAL |
|
|
|
|
MI_SEMAPHORE_TARGET(waiter->hw_id);
|
|
|
|
*cs++ = 0;
|
2014-06-30 16:53:37 +00:00
|
|
|
}
|
|
|
|
|
2017-02-14 11:32:42 +00:00
|
|
|
return cs;
|
2014-06-30 16:53:37 +00:00
|
|
|
}
|
|
|
|
|
2017-02-14 11:32:42 +00:00
|
|
|
static u32 *gen6_signal(struct drm_i915_gem_request *req, u32 *cs)
|
2010-12-04 11:30:53 +00:00
|
|
|
{
|
2016-08-02 21:50:40 +00:00
|
|
|
struct drm_i915_private *dev_priv = req->i915;
|
2016-08-16 16:04:21 +00:00
|
|
|
struct intel_engine_cs *engine;
|
drm/i915: Allocate intel_engine_cs structure only for the enabled engines
With the possibility of addition of many more number of rings in future,
the drm_i915_private structure could bloat as an array, of type
intel_engine_cs, is embedded inside it.
struct intel_engine_cs engine[I915_NUM_ENGINES];
Though this is still fine as generally there is only a single instance of
drm_i915_private structure used, but not all of the possible rings would be
enabled or active on most of the platforms. Some memory can be saved by
allocating intel_engine_cs structure only for the enabled/active engines.
Currently the engine/ring ID is kept static and dev_priv->engine[] is simply
indexed using the enums defined in intel_engine_id.
To save memory and continue using the static engine/ring IDs, 'engine' is
defined as an array of pointers.
struct intel_engine_cs *engine[I915_NUM_ENGINES];
dev_priv->engine[engine_ID] will be NULL for disabled engine instances.
There is a text size reduction of 928 bytes, from 1028200 to 1027272, for
i915.o file (but for i915.ko file text size remain same as 1193131 bytes).
v2:
- Remove the engine iterator field added in drm_i915_private structure,
instead pass a local iterator variable to the for_each_engine**
macros. (Chris)
- Do away with intel_engine_initialized() and instead directly use the
NULL pointer check on engine pointer. (Chris)
v3:
- Remove for_each_engine_id() macro, as the updated macro for_each_engine()
can be used in place of it. (Chris)
- Protect the access to Render engine Fault register with a NULL check, as
engine specific init is done later in Driver load sequence.
v4:
- Use !!dev_priv->engine[VCS] style for the engine check in getparam. (Chris)
- Kill the superfluous init_engine_lists().
v5:
- Cleanup the intel_engines_init() & intel_engines_setup(), with respect to
allocation of intel_engine_cs structure. (Chris)
v6:
- Rebase.
v7:
- Optimize the for_each_engine_masked() macro. (Chris)
- Change the type of 'iter' local variable to enum intel_engine_id. (Chris)
- Rebase.
v8: Rebase.
v9: Rebase.
v10:
- For index calculation use engine ID instead of pointer based arithmetic in
intel_engine_sync_index() as engine pointers are not contiguous now (Chris)
- For appropriateness, rename local enum variable 'iter' to 'id'. (Joonas)
- Use for_each_engine macro for cleanup in intel_engines_init() and remove
check for NULL engine pointer in cleanup() routines. (Joonas)
v11: Rebase.
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Akash Goel <akash.goel@intel.com>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1476378888-7372-1-git-send-email-akash.goel@intel.com
2016-10-13 17:14:48 +00:00
|
|
|
enum intel_engine_id id;
|
2016-10-28 12:58:52 +00:00
|
|
|
int num_rings = 0;
|
2014-04-29 21:52:30 +00:00
|
|
|
|
drm/i915: Allocate intel_engine_cs structure only for the enabled engines
With the possibility of addition of many more number of rings in future,
the drm_i915_private structure could bloat as an array, of type
intel_engine_cs, is embedded inside it.
struct intel_engine_cs engine[I915_NUM_ENGINES];
Though this is still fine as generally there is only a single instance of
drm_i915_private structure used, but not all of the possible rings would be
enabled or active on most of the platforms. Some memory can be saved by
allocating intel_engine_cs structure only for the enabled/active engines.
Currently the engine/ring ID is kept static and dev_priv->engine[] is simply
indexed using the enums defined in intel_engine_id.
To save memory and continue using the static engine/ring IDs, 'engine' is
defined as an array of pointers.
struct intel_engine_cs *engine[I915_NUM_ENGINES];
dev_priv->engine[engine_ID] will be NULL for disabled engine instances.
There is a text size reduction of 928 bytes, from 1028200 to 1027272, for
i915.o file (but for i915.ko file text size remain same as 1193131 bytes).
v2:
- Remove the engine iterator field added in drm_i915_private structure,
instead pass a local iterator variable to the for_each_engine**
macros. (Chris)
- Do away with intel_engine_initialized() and instead directly use the
NULL pointer check on engine pointer. (Chris)
v3:
- Remove for_each_engine_id() macro, as the updated macro for_each_engine()
can be used in place of it. (Chris)
- Protect the access to Render engine Fault register with a NULL check, as
engine specific init is done later in Driver load sequence.
v4:
- Use !!dev_priv->engine[VCS] style for the engine check in getparam. (Chris)
- Kill the superfluous init_engine_lists().
v5:
- Cleanup the intel_engines_init() & intel_engines_setup(), with respect to
allocation of intel_engine_cs structure. (Chris)
v6:
- Rebase.
v7:
- Optimize the for_each_engine_masked() macro. (Chris)
- Change the type of 'iter' local variable to enum intel_engine_id. (Chris)
- Rebase.
v8: Rebase.
v9: Rebase.
v10:
- For index calculation use engine ID instead of pointer based arithmetic in
intel_engine_sync_index() as engine pointers are not contiguous now (Chris)
- For appropriateness, rename local enum variable 'iter' to 'id'. (Joonas)
- Use for_each_engine macro for cleanup in intel_engines_init() and remove
check for NULL engine pointer in cleanup() routines. (Joonas)
v11: Rebase.
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Akash Goel <akash.goel@intel.com>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1476378888-7372-1-git-send-email-akash.goel@intel.com
2016-10-13 17:14:48 +00:00
|
|
|
for_each_engine(engine, dev_priv, id) {
|
2016-08-16 16:04:21 +00:00
|
|
|
i915_reg_t mbox_reg;
|
|
|
|
|
|
|
|
if (!(BIT(engine->hw_id) & GEN6_SEMAPHORES_MASK))
|
|
|
|
continue;
|
drm/i915: Type safe register read/write
Make I915_READ and I915_WRITE more type safe by wrapping the register
offset in a struct. This should eliminate most of the fumbles we've had
with misplaced parens.
This only takes care of normal mmio registers. We could extend the idea
to other register types and define each with its own struct. That way
you wouldn't be able to accidentally pass the wrong thing to a specific
register access function.
The gpio_reg setup is probably the ugliest thing left. But I figure I'd
just leave it for now, and wait for some divine inspiration to strike
before making it nice.
As for the generated code, it's actually a bit better sometimes. Eg.
looking at i915_irq_handler(), we can see the following change:
lea 0x70024(%rdx,%rax,1),%r9d
mov $0x1,%edx
- movslq %r9d,%r9
- mov %r9,%rsi
- mov %r9,-0x58(%rbp)
- callq *0xd8(%rbx)
+ mov %r9d,%esi
+ mov %r9d,-0x48(%rbp)
callq *0xd8(%rbx)
So previously gcc thought the register offset might be signed and
decided to sign extend it, just in case. The rest appears to be
mostly just minor shuffling of instructions.
v2: i915_mmio_reg_{offset,equal,valid}() helpers added
s/_REG/_MMIO/ in the register defines
mo more switch statements left to worry about
ring_emit stuff got sorted in a prep patch
cmd parser, lrc context and w/a batch buildup also in prep patch
vgpu stuff cleaned up and moved to a prep patch
all other unrelated changes split out
v3: Rebased due to BXT DSI/BLC, MOCS, etc.
v4: Rebased due to churn, s/i915_mmio_reg_t/i915_reg_t/
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/1447853606-2751-1-git-send-email-ville.syrjala@linux.intel.com
2015-11-18 13:33:26 +00:00
|
|
|
|
2016-08-16 16:04:21 +00:00
|
|
|
mbox_reg = req->engine->semaphore.mbox.signal[engine->hw_id];
|
drm/i915: Type safe register read/write
Make I915_READ and I915_WRITE more type safe by wrapping the register
offset in a struct. This should eliminate most of the fumbles we've had
with misplaced parens.
This only takes care of normal mmio registers. We could extend the idea
to other register types and define each with its own struct. That way
you wouldn't be able to accidentally pass the wrong thing to a specific
register access function.
The gpio_reg setup is probably the ugliest thing left. But I figure I'd
just leave it for now, and wait for some divine inspiration to strike
before making it nice.
As for the generated code, it's actually a bit better sometimes. Eg.
looking at i915_irq_handler(), we can see the following change:
lea 0x70024(%rdx,%rax,1),%r9d
mov $0x1,%edx
- movslq %r9d,%r9
- mov %r9,%rsi
- mov %r9,-0x58(%rbp)
- callq *0xd8(%rbx)
+ mov %r9d,%esi
+ mov %r9d,-0x48(%rbp)
callq *0xd8(%rbx)
So previously gcc thought the register offset might be signed and
decided to sign extend it, just in case. The rest appears to be
mostly just minor shuffling of instructions.
v2: i915_mmio_reg_{offset,equal,valid}() helpers added
s/_REG/_MMIO/ in the register defines
mo more switch statements left to worry about
ring_emit stuff got sorted in a prep patch
cmd parser, lrc context and w/a batch buildup also in prep patch
vgpu stuff cleaned up and moved to a prep patch
all other unrelated changes split out
v3: Rebased due to BXT DSI/BLC, MOCS, etc.
v4: Rebased due to churn, s/i915_mmio_reg_t/i915_reg_t/
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/1447853606-2751-1-git-send-email-ville.syrjala@linux.intel.com
2015-11-18 13:33:26 +00:00
|
|
|
if (i915_mmio_reg_valid(mbox_reg)) {
|
2017-02-14 11:32:42 +00:00
|
|
|
*cs++ = MI_LOAD_REGISTER_IMM(1);
|
|
|
|
*cs++ = i915_mmio_reg_offset(mbox_reg);
|
|
|
|
*cs++ = req->global_seqno;
|
2016-10-28 12:58:52 +00:00
|
|
|
num_rings++;
|
2014-04-29 21:52:29 +00:00
|
|
|
}
|
|
|
|
}
|
2016-10-28 12:58:52 +00:00
|
|
|
if (num_rings & 1)
|
2017-02-14 11:32:42 +00:00
|
|
|
*cs++ = MI_NOOP;
|
2014-04-29 21:52:30 +00:00
|
|
|
|
2017-02-14 11:32:42 +00:00
|
|
|
return cs;
|
2010-12-04 11:30:53 +00:00
|
|
|
}
|
|
|
|
|
2016-08-02 21:50:34 +00:00
|
|
|
static void i9xx_submit_request(struct drm_i915_gem_request *request)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = request->i915;
|
|
|
|
|
2016-11-14 20:40:59 +00:00
|
|
|
i915_gem_request_submit(request);
|
|
|
|
|
2017-04-25 13:00:49 +00:00
|
|
|
I915_WRITE_TAIL(request->engine,
|
|
|
|
intel_ring_set_tail(request->ring, request->tail));
|
2016-08-02 21:50:34 +00:00
|
|
|
}
|
|
|
|
|
2017-02-14 11:32:42 +00:00
|
|
|
static void i9xx_emit_breadcrumb(struct drm_i915_gem_request *req, u32 *cs)
|
2010-12-04 11:30:53 +00:00
|
|
|
{
|
2017-02-14 11:32:42 +00:00
|
|
|
*cs++ = MI_STORE_DWORD_INDEX;
|
|
|
|
*cs++ = I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT;
|
|
|
|
*cs++ = req->global_seqno;
|
|
|
|
*cs++ = MI_USER_INTERRUPT;
|
2010-12-04 11:30:53 +00:00
|
|
|
|
2017-02-14 11:32:42 +00:00
|
|
|
req->tail = intel_ring_offset(req, cs);
|
2017-03-27 13:14:12 +00:00
|
|
|
assert_ring_tail_valid(req->ring, req->tail);
|
2010-12-04 11:30:53 +00:00
|
|
|
}
|
|
|
|
|
2016-10-28 12:58:51 +00:00
|
|
|
static const int i9xx_emit_breadcrumb_sz = 4;
|
|
|
|
|
2016-08-02 21:50:34 +00:00
|
|
|
/**
|
2016-10-28 12:58:50 +00:00
|
|
|
* gen6_sema_emit_breadcrumb - Update the semaphore mailbox registers
|
2016-08-02 21:50:34 +00:00
|
|
|
*
|
|
|
|
* @request - request to write to the ring
|
|
|
|
*
|
|
|
|
* Update the mailbox registers in the *other* rings with the current seqno.
|
|
|
|
* This acts like a signal in the canonical semaphore.
|
|
|
|
*/
|
2017-02-14 11:32:42 +00:00
|
|
|
static void gen6_sema_emit_breadcrumb(struct drm_i915_gem_request *req, u32 *cs)
|
2016-08-02 21:50:34 +00:00
|
|
|
{
|
2016-10-28 12:58:52 +00:00
|
|
|
return i9xx_emit_breadcrumb(req,
|
2017-02-14 11:32:42 +00:00
|
|
|
req->engine->semaphore.signal(req, cs));
|
2016-08-02 21:50:34 +00:00
|
|
|
}
|
|
|
|
|
2016-10-28 12:58:52 +00:00
|
|
|
static void gen8_render_emit_breadcrumb(struct drm_i915_gem_request *req,
|
2017-02-14 11:32:42 +00:00
|
|
|
u32 *cs)
|
2016-04-29 12:18:21 +00:00
|
|
|
{
|
|
|
|
struct intel_engine_cs *engine = req->engine;
|
2016-08-02 21:50:33 +00:00
|
|
|
|
2016-10-28 12:58:52 +00:00
|
|
|
if (engine->semaphore.signal)
|
2017-02-14 11:32:42 +00:00
|
|
|
cs = engine->semaphore.signal(req, cs);
|
|
|
|
|
|
|
|
*cs++ = GFX_OP_PIPE_CONTROL(6);
|
|
|
|
*cs++ = PIPE_CONTROL_GLOBAL_GTT_IVB | PIPE_CONTROL_CS_STALL |
|
|
|
|
PIPE_CONTROL_QW_WRITE;
|
|
|
|
*cs++ = intel_hws_seqno_address(engine);
|
|
|
|
*cs++ = 0;
|
|
|
|
*cs++ = req->global_seqno;
|
2016-04-29 12:18:21 +00:00
|
|
|
/* We're thrashing one dword of HWS. */
|
2017-02-14 11:32:42 +00:00
|
|
|
*cs++ = 0;
|
|
|
|
*cs++ = MI_USER_INTERRUPT;
|
|
|
|
*cs++ = MI_NOOP;
|
2016-04-29 12:18:21 +00:00
|
|
|
|
2017-02-14 11:32:42 +00:00
|
|
|
req->tail = intel_ring_offset(req, cs);
|
2017-03-27 13:14:12 +00:00
|
|
|
assert_ring_tail_valid(req->ring, req->tail);
|
2016-04-29 12:18:21 +00:00
|
|
|
}
|
|
|
|
|
2016-10-28 12:58:51 +00:00
|
|
|
static const int gen8_render_emit_breadcrumb_sz = 8;
|
|
|
|
|
2011-09-15 03:32:47 +00:00
|
|
|
/**
|
|
|
|
* intel_ring_sync - sync the waiter to the signaller on seqno
|
|
|
|
*
|
|
|
|
* @waiter - ring that is waiting
|
|
|
|
* @signaller - ring which has, or will signal
|
|
|
|
* @seqno - seqno which the waiter will block on
|
|
|
|
*/
|
2014-06-30 16:53:38 +00:00
|
|
|
|
|
|
|
static int
|
2016-08-02 21:50:40 +00:00
|
|
|
gen8_ring_sync_to(struct drm_i915_gem_request *req,
|
|
|
|
struct drm_i915_gem_request *signal)
|
2014-06-30 16:53:38 +00:00
|
|
|
{
|
2016-08-02 21:50:40 +00:00
|
|
|
struct drm_i915_private *dev_priv = req->i915;
|
|
|
|
u64 offset = GEN8_WAIT_OFFSET(req->engine, signal->engine->id);
|
2016-04-29 12:18:25 +00:00
|
|
|
struct i915_hw_ppgtt *ppgtt;
|
2017-02-14 11:32:42 +00:00
|
|
|
u32 *cs;
|
2014-06-30 16:53:38 +00:00
|
|
|
|
2017-02-14 11:32:42 +00:00
|
|
|
cs = intel_ring_begin(req, 4);
|
|
|
|
if (IS_ERR(cs))
|
|
|
|
return PTR_ERR(cs);
|
2014-06-30 16:53:38 +00:00
|
|
|
|
2017-02-14 11:32:42 +00:00
|
|
|
*cs++ = MI_SEMAPHORE_WAIT | MI_SEMAPHORE_GLOBAL_GTT |
|
|
|
|
MI_SEMAPHORE_SAD_GTE_SDD;
|
|
|
|
*cs++ = signal->global_seqno;
|
|
|
|
*cs++ = lower_32_bits(offset);
|
|
|
|
*cs++ = upper_32_bits(offset);
|
|
|
|
intel_ring_advance(req, cs);
|
2016-04-29 12:18:25 +00:00
|
|
|
|
|
|
|
/* When the !RCS engines idle waiting upon a semaphore, they lose their
|
|
|
|
* pagetables and we must reload them before executing the batch.
|
|
|
|
* We do this on the i915_switch_context() following the wait and
|
|
|
|
* before the dispatch.
|
|
|
|
*/
|
2016-08-02 21:50:40 +00:00
|
|
|
ppgtt = req->ctx->ppgtt;
|
|
|
|
if (ppgtt && req->engine->id != RCS)
|
|
|
|
ppgtt->pd_dirty_rings |= intel_engine_flag(req->engine);
|
2014-06-30 16:53:38 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2011-09-15 03:32:47 +00:00
|
|
|
static int
|
2016-08-02 21:50:40 +00:00
|
|
|
gen6_ring_sync_to(struct drm_i915_gem_request *req,
|
|
|
|
struct drm_i915_gem_request *signal)
|
2010-12-04 11:30:53 +00:00
|
|
|
{
|
2011-09-15 03:32:47 +00:00
|
|
|
u32 dw1 = MI_SEMAPHORE_MBOX |
|
|
|
|
MI_SEMAPHORE_COMPARE |
|
|
|
|
MI_SEMAPHORE_REGISTER;
|
2016-08-16 16:04:21 +00:00
|
|
|
u32 wait_mbox = signal->engine->semaphore.mbox.wait[req->engine->hw_id];
|
2017-02-14 11:32:42 +00:00
|
|
|
u32 *cs;
|
2010-12-04 11:30:53 +00:00
|
|
|
|
2014-04-29 21:52:28 +00:00
|
|
|
WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID);
|
2012-04-11 20:12:52 +00:00
|
|
|
|
2017-02-14 11:32:42 +00:00
|
|
|
cs = intel_ring_begin(req, 4);
|
|
|
|
if (IS_ERR(cs))
|
|
|
|
return PTR_ERR(cs);
|
2010-12-04 11:30:53 +00:00
|
|
|
|
2017-02-14 11:32:42 +00:00
|
|
|
*cs++ = dw1 | wait_mbox;
|
2016-08-02 21:50:39 +00:00
|
|
|
/* Throughout all of the GEM code, seqno passed implies our current
|
|
|
|
* seqno is >= the last seqno executed. However for hardware the
|
|
|
|
* comparison is strictly greater than.
|
|
|
|
*/
|
2017-02-14 11:32:42 +00:00
|
|
|
*cs++ = signal->global_seqno - 1;
|
|
|
|
*cs++ = 0;
|
|
|
|
*cs++ = MI_NOOP;
|
|
|
|
intel_ring_advance(req, cs);
|
2010-12-04 11:30:53 +00:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2016-07-01 16:23:21 +00:00
|
|
|
static void
|
2016-07-20 17:16:06 +00:00
|
|
|
gen5_seqno_barrier(struct intel_engine_cs *engine)
|
2010-12-15 09:56:50 +00:00
|
|
|
{
|
2016-07-01 16:23:21 +00:00
|
|
|
/* MI_STORE are internally buffered by the GPU and not flushed
|
|
|
|
* either by MI_FLUSH or SyncFlush or any other combination of
|
|
|
|
* MI commands.
|
2010-12-15 09:56:50 +00:00
|
|
|
*
|
2016-07-01 16:23:21 +00:00
|
|
|
* "Only the submission of the store operation is guaranteed.
|
|
|
|
* The write result will be complete (coherent) some time later
|
|
|
|
* (this is practically a finite period but there is no guaranteed
|
|
|
|
* latency)."
|
|
|
|
*
|
|
|
|
* Empirically, we observe that we need a delay of at least 75us to
|
|
|
|
* be sure that the seqno write is visible by the CPU.
|
2010-12-15 09:56:50 +00:00
|
|
|
*/
|
2016-07-01 16:23:21 +00:00
|
|
|
usleep_range(125, 250);
|
2010-12-15 09:56:50 +00:00
|
|
|
}
|
|
|
|
|
2016-04-09 09:57:54 +00:00
|
|
|
static void
|
|
|
|
gen6_seqno_barrier(struct intel_engine_cs *engine)
|
2012-12-14 15:01:25 +00:00
|
|
|
{
|
2016-05-06 14:40:21 +00:00
|
|
|
struct drm_i915_private *dev_priv = engine->i915;
|
2016-04-27 08:02:01 +00:00
|
|
|
|
2012-12-14 15:01:25 +00:00
|
|
|
/* Workaround to force correct ordering between irq and seqno writes on
|
|
|
|
* ivb (and maybe also on snb) by reading from a CS register (like
|
2016-04-09 09:57:53 +00:00
|
|
|
* ACTHD) before reading the status page.
|
|
|
|
*
|
|
|
|
* Note that this effectively stalls the read by the time it takes to
|
|
|
|
* do a memory transaction, which more or less ensures that the write
|
|
|
|
* from the GPU has sufficient time to invalidate the CPU cacheline.
|
|
|
|
* Alternatively we could delay the interrupt from the CS ring to give
|
|
|
|
* the write time to land, but that would incur a delay after every
|
|
|
|
* batch i.e. much more frequent than a delay when waiting for the
|
|
|
|
* interrupt (with the same net latency).
|
2016-04-27 08:02:01 +00:00
|
|
|
*
|
|
|
|
* Also note that to prevent whole machine hangs on gen7, we have to
|
|
|
|
* take the spinlock to guard against concurrent cacheline access.
|
2016-04-09 09:57:53 +00:00
|
|
|
*/
|
2016-04-27 08:02:01 +00:00
|
|
|
spin_lock_irq(&dev_priv->uncore.lock);
|
2016-04-09 09:57:54 +00:00
|
|
|
POSTING_READ_FW(RING_ACTHD(engine->mmio_base));
|
2016-04-27 08:02:01 +00:00
|
|
|
spin_unlock_irq(&dev_priv->uncore.lock);
|
2012-12-14 15:01:25 +00:00
|
|
|
}
|
|
|
|
|
2016-07-01 16:23:27 +00:00
|
|
|
static void
|
|
|
|
gen5_irq_enable(struct intel_engine_cs *engine)
|
2012-04-11 20:12:54 +00:00
|
|
|
{
|
2016-07-01 16:23:27 +00:00
|
|
|
gen5_enable_gt_irq(engine->i915, engine->irq_enable_mask);
|
2012-04-11 20:12:54 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
2016-07-01 16:23:27 +00:00
|
|
|
gen5_irq_disable(struct intel_engine_cs *engine)
|
2012-04-11 20:12:54 +00:00
|
|
|
{
|
2016-07-01 16:23:27 +00:00
|
|
|
gen5_disable_gt_irq(engine->i915, engine->irq_enable_mask);
|
2012-04-11 20:12:54 +00:00
|
|
|
}
|
|
|
|
|
2016-07-01 16:23:27 +00:00
|
|
|
static void
|
|
|
|
i9xx_irq_enable(struct intel_engine_cs *engine)
|
2010-05-21 20:26:39 +00:00
|
|
|
{
|
2016-05-06 14:40:21 +00:00
|
|
|
struct drm_i915_private *dev_priv = engine->i915;
|
2010-12-13 16:54:50 +00:00
|
|
|
|
2016-07-01 16:23:27 +00:00
|
|
|
dev_priv->irq_mask &= ~engine->irq_enable_mask;
|
|
|
|
I915_WRITE(IMR, dev_priv->irq_mask);
|
|
|
|
POSTING_READ_FW(RING_IMR(engine->mmio_base));
|
2010-05-21 20:26:39 +00:00
|
|
|
}
|
|
|
|
|
2010-05-21 01:08:55 +00:00
|
|
|
static void
|
2016-07-01 16:23:27 +00:00
|
|
|
i9xx_irq_disable(struct intel_engine_cs *engine)
|
2010-05-21 20:26:39 +00:00
|
|
|
{
|
2016-05-06 14:40:21 +00:00
|
|
|
struct drm_i915_private *dev_priv = engine->i915;
|
2010-05-21 20:26:39 +00:00
|
|
|
|
2016-07-01 16:23:27 +00:00
|
|
|
dev_priv->irq_mask |= engine->irq_enable_mask;
|
|
|
|
I915_WRITE(IMR, dev_priv->irq_mask);
|
2010-05-21 20:26:39 +00:00
|
|
|
}
|
|
|
|
|
2016-07-01 16:23:27 +00:00
|
|
|
static void
|
|
|
|
i8xx_irq_enable(struct intel_engine_cs *engine)
|
2012-04-22 20:13:57 +00:00
|
|
|
{
|
2016-05-06 14:40:21 +00:00
|
|
|
struct drm_i915_private *dev_priv = engine->i915;
|
2012-04-22 20:13:57 +00:00
|
|
|
|
2016-07-01 16:23:27 +00:00
|
|
|
dev_priv->irq_mask &= ~engine->irq_enable_mask;
|
|
|
|
I915_WRITE16(IMR, dev_priv->irq_mask);
|
|
|
|
POSTING_READ16(RING_IMR(engine->mmio_base));
|
2012-04-22 20:13:57 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
2016-07-01 16:23:27 +00:00
|
|
|
i8xx_irq_disable(struct intel_engine_cs *engine)
|
2012-04-22 20:13:57 +00:00
|
|
|
{
|
2016-05-06 14:40:21 +00:00
|
|
|
struct drm_i915_private *dev_priv = engine->i915;
|
2012-04-22 20:13:57 +00:00
|
|
|
|
2016-07-01 16:23:27 +00:00
|
|
|
dev_priv->irq_mask |= engine->irq_enable_mask;
|
|
|
|
I915_WRITE16(IMR, dev_priv->irq_mask);
|
2012-04-22 20:13:57 +00:00
|
|
|
}
|
|
|
|
|
2011-01-04 17:34:02 +00:00
|
|
|
static int
|
2016-08-02 21:50:25 +00:00
|
|
|
bsd_ring_flush(struct drm_i915_gem_request *req, u32 mode)
|
2010-05-21 01:08:57 +00:00
|
|
|
{
|
2017-02-14 11:32:42 +00:00
|
|
|
u32 *cs;
|
2011-01-04 17:34:02 +00:00
|
|
|
|
2017-02-14 11:32:42 +00:00
|
|
|
cs = intel_ring_begin(req, 2);
|
|
|
|
if (IS_ERR(cs))
|
|
|
|
return PTR_ERR(cs);
|
2011-01-04 17:34:02 +00:00
|
|
|
|
2017-02-14 11:32:42 +00:00
|
|
|
*cs++ = MI_FLUSH;
|
|
|
|
*cs++ = MI_NOOP;
|
|
|
|
intel_ring_advance(req, cs);
|
2011-01-04 17:34:02 +00:00
|
|
|
return 0;
|
2010-05-21 01:08:57 +00:00
|
|
|
}
|
|
|
|
|
2016-07-01 16:23:27 +00:00
|
|
|
static void
|
|
|
|
gen6_irq_enable(struct intel_engine_cs *engine)
|
2011-01-04 17:35:21 +00:00
|
|
|
{
|
2016-05-06 14:40:21 +00:00
|
|
|
struct drm_i915_private *dev_priv = engine->i915;
|
2011-01-04 17:35:21 +00:00
|
|
|
|
2016-07-01 16:23:28 +00:00
|
|
|
I915_WRITE_IMR(engine,
|
|
|
|
~(engine->irq_enable_mask |
|
|
|
|
engine->irq_keep_mask));
|
2016-07-01 16:23:27 +00:00
|
|
|
gen5_enable_gt_irq(dev_priv, engine->irq_enable_mask);
|
2011-01-04 17:35:21 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
2016-07-01 16:23:27 +00:00
|
|
|
gen6_irq_disable(struct intel_engine_cs *engine)
|
2011-01-04 17:35:21 +00:00
|
|
|
{
|
2016-05-06 14:40:21 +00:00
|
|
|
struct drm_i915_private *dev_priv = engine->i915;
|
2011-01-04 17:35:21 +00:00
|
|
|
|
2016-07-01 16:23:28 +00:00
|
|
|
I915_WRITE_IMR(engine, ~engine->irq_keep_mask);
|
2016-07-01 16:23:27 +00:00
|
|
|
gen5_disable_gt_irq(dev_priv, engine->irq_enable_mask);
|
2010-05-21 01:08:57 +00:00
|
|
|
}
|
|
|
|
|
2016-07-01 16:23:27 +00:00
|
|
|
static void
|
|
|
|
hsw_vebox_irq_enable(struct intel_engine_cs *engine)
|
2013-05-29 02:22:30 +00:00
|
|
|
{
|
2016-05-06 14:40:21 +00:00
|
|
|
struct drm_i915_private *dev_priv = engine->i915;
|
2013-05-29 02:22:30 +00:00
|
|
|
|
2016-07-01 16:23:27 +00:00
|
|
|
I915_WRITE_IMR(engine, ~engine->irq_enable_mask);
|
2016-10-12 16:24:30 +00:00
|
|
|
gen6_unmask_pm_irq(dev_priv, engine->irq_enable_mask);
|
2013-05-29 02:22:30 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
2016-07-01 16:23:27 +00:00
|
|
|
hsw_vebox_irq_disable(struct intel_engine_cs *engine)
|
2013-05-29 02:22:30 +00:00
|
|
|
{
|
2016-05-06 14:40:21 +00:00
|
|
|
struct drm_i915_private *dev_priv = engine->i915;
|
2013-05-29 02:22:30 +00:00
|
|
|
|
2016-07-01 16:23:27 +00:00
|
|
|
I915_WRITE_IMR(engine, ~0);
|
2016-10-12 16:24:30 +00:00
|
|
|
gen6_mask_pm_irq(dev_priv, engine->irq_enable_mask);
|
2013-05-29 02:22:30 +00:00
|
|
|
}
|
|
|
|
|
2016-07-01 16:23:27 +00:00
|
|
|
static void
|
|
|
|
gen8_irq_enable(struct intel_engine_cs *engine)
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 04:07:09 +00:00
|
|
|
{
|
2016-05-06 14:40:21 +00:00
|
|
|
struct drm_i915_private *dev_priv = engine->i915;
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 04:07:09 +00:00
|
|
|
|
2016-07-01 16:23:28 +00:00
|
|
|
I915_WRITE_IMR(engine,
|
|
|
|
~(engine->irq_enable_mask |
|
|
|
|
engine->irq_keep_mask));
|
2016-07-01 16:23:27 +00:00
|
|
|
POSTING_READ_FW(RING_IMR(engine->mmio_base));
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 04:07:09 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
2016-07-01 16:23:27 +00:00
|
|
|
gen8_irq_disable(struct intel_engine_cs *engine)
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 04:07:09 +00:00
|
|
|
{
|
2016-05-06 14:40:21 +00:00
|
|
|
struct drm_i915_private *dev_priv = engine->i915;
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 04:07:09 +00:00
|
|
|
|
2016-07-01 16:23:28 +00:00
|
|
|
I915_WRITE_IMR(engine, ~engine->irq_keep_mask);
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 04:07:09 +00:00
|
|
|
}
|
|
|
|
|
2010-05-21 01:08:57 +00:00
|
|
|
static int
|
2016-08-02 21:50:27 +00:00
|
|
|
i965_emit_bb_start(struct drm_i915_gem_request *req,
|
|
|
|
u64 offset, u32 length,
|
|
|
|
unsigned int dispatch_flags)
|
2010-05-21 01:08:57 +00:00
|
|
|
{
|
2017-02-14 11:32:42 +00:00
|
|
|
u32 *cs;
|
2010-10-27 11:18:21 +00:00
|
|
|
|
2017-02-14 11:32:42 +00:00
|
|
|
cs = intel_ring_begin(req, 2);
|
|
|
|
if (IS_ERR(cs))
|
|
|
|
return PTR_ERR(cs);
|
2010-10-27 11:45:26 +00:00
|
|
|
|
2017-02-14 11:32:42 +00:00
|
|
|
*cs++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT | (dispatch_flags &
|
|
|
|
I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965);
|
|
|
|
*cs++ = offset;
|
|
|
|
intel_ring_advance(req, cs);
|
2010-10-27 11:18:21 +00:00
|
|
|
|
2010-05-21 01:08:57 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2012-12-17 15:21:27 +00:00
|
|
|
/* Just userspace ABI convention to limit the wa batch bo to a resonable size */
|
|
|
|
#define I830_BATCH_LIMIT (256*1024)
|
drm/i915: Evict CS TLBs between batches
Running igt, I was encountering the invalid TLB bug on my 845g, despite
that it was using the CS workaround. Examining the w/a buffer in the
error state, showed that the copy from the user batch into the
workaround itself was suffering from the invalid TLB bug (the first
cacheline was broken with the first two words reversed). Time to try a
fresh approach. This extends the workaround to write into each page of
our scratch buffer in order to overflow the TLB and evict the invalid
entries. This could be refined to only do so after we update the GTT,
but for simplicity, we do it before each batch.
I suspect this supersedes our current workaround, but for safety keep
doing both.
v2: The magic number shall be 2.
This doesn't conclusively prove that it is the mythical TLB bug we've
been trying to workaround for so long, that it requires touching a number
of pages to prevent the corruption indicates to me that it is TLB
related, but the corruption (the reversed cacheline) is more subtle than
a TLB bug, where we would expect it to read the wrong page entirely.
Oh well, it prevents a reliable hang for me and so probably for others
as well.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: stable@vger.kernel.org
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2014-09-08 13:25:41 +00:00
|
|
|
#define I830_TLB_ENTRIES (2)
|
|
|
|
#define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
|
2010-05-21 01:08:55 +00:00
|
|
|
static int
|
2016-08-02 21:50:27 +00:00
|
|
|
i830_emit_bb_start(struct drm_i915_gem_request *req,
|
|
|
|
u64 offset, u32 len,
|
|
|
|
unsigned int dispatch_flags)
|
2010-05-21 20:26:39 +00:00
|
|
|
{
|
2017-02-14 11:32:42 +00:00
|
|
|
u32 *cs, cs_offset = i915_ggtt_offset(req->engine->scratch);
|
2010-05-21 20:26:39 +00:00
|
|
|
|
2017-02-14 11:32:42 +00:00
|
|
|
cs = intel_ring_begin(req, 6);
|
|
|
|
if (IS_ERR(cs))
|
|
|
|
return PTR_ERR(cs);
|
2010-05-21 20:26:39 +00:00
|
|
|
|
drm/i915: Evict CS TLBs between batches
Running igt, I was encountering the invalid TLB bug on my 845g, despite
that it was using the CS workaround. Examining the w/a buffer in the
error state, showed that the copy from the user batch into the
workaround itself was suffering from the invalid TLB bug (the first
cacheline was broken with the first two words reversed). Time to try a
fresh approach. This extends the workaround to write into each page of
our scratch buffer in order to overflow the TLB and evict the invalid
entries. This could be refined to only do so after we update the GTT,
but for simplicity, we do it before each batch.
I suspect this supersedes our current workaround, but for safety keep
doing both.
v2: The magic number shall be 2.
This doesn't conclusively prove that it is the mythical TLB bug we've
been trying to workaround for so long, that it requires touching a number
of pages to prevent the corruption indicates to me that it is TLB
related, but the corruption (the reversed cacheline) is more subtle than
a TLB bug, where we would expect it to read the wrong page entirely.
Oh well, it prevents a reliable hang for me and so probably for others
as well.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: stable@vger.kernel.org
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2014-09-08 13:25:41 +00:00
|
|
|
/* Evict the invalid PTE TLBs */
|
2017-02-14 11:32:42 +00:00
|
|
|
*cs++ = COLOR_BLT_CMD | BLT_WRITE_RGBA;
|
|
|
|
*cs++ = BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096;
|
|
|
|
*cs++ = I830_TLB_ENTRIES << 16 | 4; /* load each page */
|
|
|
|
*cs++ = cs_offset;
|
|
|
|
*cs++ = 0xdeadbeef;
|
|
|
|
*cs++ = MI_NOOP;
|
|
|
|
intel_ring_advance(req, cs);
|
2012-12-17 15:21:27 +00:00
|
|
|
|
2015-02-13 11:48:10 +00:00
|
|
|
if ((dispatch_flags & I915_DISPATCH_PINNED) == 0) {
|
2012-12-17 15:21:27 +00:00
|
|
|
if (len > I830_BATCH_LIMIT)
|
|
|
|
return -ENOSPC;
|
|
|
|
|
2017-02-14 11:32:42 +00:00
|
|
|
cs = intel_ring_begin(req, 6 + 2);
|
|
|
|
if (IS_ERR(cs))
|
|
|
|
return PTR_ERR(cs);
|
drm/i915: Evict CS TLBs between batches
Running igt, I was encountering the invalid TLB bug on my 845g, despite
that it was using the CS workaround. Examining the w/a buffer in the
error state, showed that the copy from the user batch into the
workaround itself was suffering from the invalid TLB bug (the first
cacheline was broken with the first two words reversed). Time to try a
fresh approach. This extends the workaround to write into each page of
our scratch buffer in order to overflow the TLB and evict the invalid
entries. This could be refined to only do so after we update the GTT,
but for simplicity, we do it before each batch.
I suspect this supersedes our current workaround, but for safety keep
doing both.
v2: The magic number shall be 2.
This doesn't conclusively prove that it is the mythical TLB bug we've
been trying to workaround for so long, that it requires touching a number
of pages to prevent the corruption indicates to me that it is TLB
related, but the corruption (the reversed cacheline) is more subtle than
a TLB bug, where we would expect it to read the wrong page entirely.
Oh well, it prevents a reliable hang for me and so probably for others
as well.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: stable@vger.kernel.org
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2014-09-08 13:25:41 +00:00
|
|
|
|
|
|
|
/* Blit the batch (which has now all relocs applied) to the
|
|
|
|
* stable batch scratch bo area (so that the CS never
|
|
|
|
* stumbles over its tlb invalidation bug) ...
|
|
|
|
*/
|
2017-02-14 11:32:42 +00:00
|
|
|
*cs++ = SRC_COPY_BLT_CMD | BLT_WRITE_RGBA;
|
|
|
|
*cs++ = BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096;
|
|
|
|
*cs++ = DIV_ROUND_UP(len, 4096) << 16 | 4096;
|
|
|
|
*cs++ = cs_offset;
|
|
|
|
*cs++ = 4096;
|
|
|
|
*cs++ = offset;
|
|
|
|
|
|
|
|
*cs++ = MI_FLUSH;
|
|
|
|
*cs++ = MI_NOOP;
|
|
|
|
intel_ring_advance(req, cs);
|
2012-12-17 15:21:27 +00:00
|
|
|
|
|
|
|
/* ... and execute it. */
|
drm/i915: Evict CS TLBs between batches
Running igt, I was encountering the invalid TLB bug on my 845g, despite
that it was using the CS workaround. Examining the w/a buffer in the
error state, showed that the copy from the user batch into the
workaround itself was suffering from the invalid TLB bug (the first
cacheline was broken with the first two words reversed). Time to try a
fresh approach. This extends the workaround to write into each page of
our scratch buffer in order to overflow the TLB and evict the invalid
entries. This could be refined to only do so after we update the GTT,
but for simplicity, we do it before each batch.
I suspect this supersedes our current workaround, but for safety keep
doing both.
v2: The magic number shall be 2.
This doesn't conclusively prove that it is the mythical TLB bug we've
been trying to workaround for so long, that it requires touching a number
of pages to prevent the corruption indicates to me that it is TLB
related, but the corruption (the reversed cacheline) is more subtle than
a TLB bug, where we would expect it to read the wrong page entirely.
Oh well, it prevents a reliable hang for me and so probably for others
as well.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: stable@vger.kernel.org
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2014-09-08 13:25:41 +00:00
|
|
|
offset = cs_offset;
|
2012-12-17 15:21:27 +00:00
|
|
|
}
|
2010-10-27 11:45:26 +00:00
|
|
|
|
2017-02-14 11:32:42 +00:00
|
|
|
cs = intel_ring_begin(req, 2);
|
|
|
|
if (IS_ERR(cs))
|
|
|
|
return PTR_ERR(cs);
|
drm/i915: Evict CS TLBs between batches
Running igt, I was encountering the invalid TLB bug on my 845g, despite
that it was using the CS workaround. Examining the w/a buffer in the
error state, showed that the copy from the user batch into the
workaround itself was suffering from the invalid TLB bug (the first
cacheline was broken with the first two words reversed). Time to try a
fresh approach. This extends the workaround to write into each page of
our scratch buffer in order to overflow the TLB and evict the invalid
entries. This could be refined to only do so after we update the GTT,
but for simplicity, we do it before each batch.
I suspect this supersedes our current workaround, but for safety keep
doing both.
v2: The magic number shall be 2.
This doesn't conclusively prove that it is the mythical TLB bug we've
been trying to workaround for so long, that it requires touching a number
of pages to prevent the corruption indicates to me that it is TLB
related, but the corruption (the reversed cacheline) is more subtle than
a TLB bug, where we would expect it to read the wrong page entirely.
Oh well, it prevents a reliable hang for me and so probably for others
as well.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: stable@vger.kernel.org
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2014-09-08 13:25:41 +00:00
|
|
|
|
2017-02-14 11:32:42 +00:00
|
|
|
*cs++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT;
|
|
|
|
*cs++ = offset | (dispatch_flags & I915_DISPATCH_SECURE ? 0 :
|
|
|
|
MI_BATCH_NON_SECURE);
|
|
|
|
intel_ring_advance(req, cs);
|
drm/i915: Evict CS TLBs between batches
Running igt, I was encountering the invalid TLB bug on my 845g, despite
that it was using the CS workaround. Examining the w/a buffer in the
error state, showed that the copy from the user batch into the
workaround itself was suffering from the invalid TLB bug (the first
cacheline was broken with the first two words reversed). Time to try a
fresh approach. This extends the workaround to write into each page of
our scratch buffer in order to overflow the TLB and evict the invalid
entries. This could be refined to only do so after we update the GTT,
but for simplicity, we do it before each batch.
I suspect this supersedes our current workaround, but for safety keep
doing both.
v2: The magic number shall be 2.
This doesn't conclusively prove that it is the mythical TLB bug we've
been trying to workaround for so long, that it requires touching a number
of pages to prevent the corruption indicates to me that it is TLB
related, but the corruption (the reversed cacheline) is more subtle than
a TLB bug, where we would expect it to read the wrong page entirely.
Oh well, it prevents a reliable hang for me and so probably for others
as well.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: stable@vger.kernel.org
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2014-09-08 13:25:41 +00:00
|
|
|
|
2012-04-11 20:12:56 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
2016-08-02 21:50:27 +00:00
|
|
|
i915_emit_bb_start(struct drm_i915_gem_request *req,
|
|
|
|
u64 offset, u32 len,
|
|
|
|
unsigned int dispatch_flags)
|
2012-04-11 20:12:56 +00:00
|
|
|
{
|
2017-02-14 11:32:42 +00:00
|
|
|
u32 *cs;
|
2012-04-11 20:12:56 +00:00
|
|
|
|
2017-02-14 11:32:42 +00:00
|
|
|
cs = intel_ring_begin(req, 2);
|
|
|
|
if (IS_ERR(cs))
|
|
|
|
return PTR_ERR(cs);
|
2012-04-11 20:12:56 +00:00
|
|
|
|
2017-02-14 11:32:42 +00:00
|
|
|
*cs++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT;
|
|
|
|
*cs++ = offset | (dispatch_flags & I915_DISPATCH_SECURE ? 0 :
|
|
|
|
MI_BATCH_NON_SECURE);
|
|
|
|
intel_ring_advance(req, cs);
|
2010-05-21 20:26:39 +00:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2016-03-16 11:00:37 +00:00
|
|
|
static void cleanup_phys_status_page(struct intel_engine_cs *engine)
|
2016-01-11 18:48:32 +00:00
|
|
|
{
|
2016-05-06 14:40:21 +00:00
|
|
|
struct drm_i915_private *dev_priv = engine->i915;
|
2016-01-11 18:48:32 +00:00
|
|
|
|
|
|
|
if (!dev_priv->status_page_dmah)
|
|
|
|
return;
|
|
|
|
|
2016-07-05 09:40:23 +00:00
|
|
|
drm_pci_free(&dev_priv->drm, dev_priv->status_page_dmah);
|
2016-03-16 11:00:37 +00:00
|
|
|
engine->status_page.page_addr = NULL;
|
2016-01-11 18:48:32 +00:00
|
|
|
}
|
|
|
|
|
2016-03-16 11:00:37 +00:00
|
|
|
static void cleanup_status_page(struct intel_engine_cs *engine)
|
2010-05-21 20:26:39 +00:00
|
|
|
{
|
2016-08-15 09:48:57 +00:00
|
|
|
struct i915_vma *vma;
|
2016-10-28 12:58:29 +00:00
|
|
|
struct drm_i915_gem_object *obj;
|
2010-05-21 20:26:39 +00:00
|
|
|
|
2016-08-15 09:48:57 +00:00
|
|
|
vma = fetch_and_zero(&engine->status_page.vma);
|
|
|
|
if (!vma)
|
2010-05-21 20:26:39 +00:00
|
|
|
return;
|
|
|
|
|
2016-10-28 12:58:29 +00:00
|
|
|
obj = vma->obj;
|
|
|
|
|
2016-08-15 09:48:57 +00:00
|
|
|
i915_vma_unpin(vma);
|
2016-10-28 12:58:29 +00:00
|
|
|
i915_vma_close(vma);
|
|
|
|
|
|
|
|
i915_gem_object_unpin_map(obj);
|
|
|
|
__i915_gem_object_release_unless_active(obj);
|
2010-05-21 20:26:39 +00:00
|
|
|
}
|
|
|
|
|
2016-03-16 11:00:37 +00:00
|
|
|
static int init_status_page(struct intel_engine_cs *engine)
|
2010-05-21 20:26:39 +00:00
|
|
|
{
|
2016-08-15 09:48:57 +00:00
|
|
|
struct drm_i915_gem_object *obj;
|
|
|
|
struct i915_vma *vma;
|
|
|
|
unsigned int flags;
|
2016-10-28 12:58:30 +00:00
|
|
|
void *vaddr;
|
2016-08-15 09:48:57 +00:00
|
|
|
int ret;
|
2011-04-04 08:44:39 +00:00
|
|
|
|
2017-01-10 14:47:34 +00:00
|
|
|
obj = i915_gem_object_create_internal(engine->i915, PAGE_SIZE);
|
2016-08-15 09:48:57 +00:00
|
|
|
if (IS_ERR(obj)) {
|
|
|
|
DRM_ERROR("Failed to allocate status page\n");
|
|
|
|
return PTR_ERR(obj);
|
|
|
|
}
|
2010-05-21 20:26:39 +00:00
|
|
|
|
2016-08-15 09:48:57 +00:00
|
|
|
ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
|
|
|
|
if (ret)
|
|
|
|
goto err;
|
2014-04-09 08:19:41 +00:00
|
|
|
|
2017-01-16 15:21:30 +00:00
|
|
|
vma = i915_vma_instance(obj, &engine->i915->ggtt.base, NULL);
|
2016-08-15 09:48:57 +00:00
|
|
|
if (IS_ERR(vma)) {
|
|
|
|
ret = PTR_ERR(vma);
|
|
|
|
goto err;
|
2014-04-09 08:19:41 +00:00
|
|
|
}
|
2010-05-21 20:26:39 +00:00
|
|
|
|
2016-08-15 09:48:57 +00:00
|
|
|
flags = PIN_GLOBAL;
|
|
|
|
if (!HAS_LLC(engine->i915))
|
|
|
|
/* On g33, we cannot place HWS above 256MiB, so
|
|
|
|
* restrict its pinning to the low mappable arena.
|
|
|
|
* Though this restriction is not documented for
|
|
|
|
* gen4, gen5, or byt, they also behave similarly
|
|
|
|
* and hang if the HWS is placed at the top of the
|
|
|
|
* GTT. To generalise, it appears that all !llc
|
|
|
|
* platforms have issues with us placing the HWS
|
|
|
|
* above the mappable region (even though we never
|
|
|
|
* actualy map it).
|
|
|
|
*/
|
|
|
|
flags |= PIN_MAPPABLE;
|
|
|
|
ret = i915_vma_pin(vma, 0, 4096, flags);
|
|
|
|
if (ret)
|
|
|
|
goto err;
|
2010-05-21 20:26:39 +00:00
|
|
|
|
2016-10-28 12:58:30 +00:00
|
|
|
vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB);
|
|
|
|
if (IS_ERR(vaddr)) {
|
|
|
|
ret = PTR_ERR(vaddr);
|
|
|
|
goto err_unpin;
|
|
|
|
}
|
|
|
|
|
2016-08-15 09:48:57 +00:00
|
|
|
engine->status_page.vma = vma;
|
2016-08-15 09:49:07 +00:00
|
|
|
engine->status_page.ggtt_offset = i915_ggtt_offset(vma);
|
2017-01-10 14:47:34 +00:00
|
|
|
engine->status_page.page_addr = memset(vaddr, 0, PAGE_SIZE);
|
2010-05-21 20:26:39 +00:00
|
|
|
|
2016-08-15 09:49:07 +00:00
|
|
|
DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
|
|
|
|
engine->name, i915_ggtt_offset(vma));
|
2010-05-21 20:26:39 +00:00
|
|
|
return 0;
|
2016-08-15 09:48:57 +00:00
|
|
|
|
2016-10-28 12:58:30 +00:00
|
|
|
err_unpin:
|
|
|
|
i915_vma_unpin(vma);
|
2016-08-15 09:48:57 +00:00
|
|
|
err:
|
|
|
|
i915_gem_object_put(obj);
|
|
|
|
return ret;
|
2010-05-21 20:26:39 +00:00
|
|
|
}
|
|
|
|
|
2016-03-16 11:00:37 +00:00
|
|
|
static int init_phys_status_page(struct intel_engine_cs *engine)
|
2012-11-16 11:43:20 +00:00
|
|
|
{
|
2016-05-06 14:40:21 +00:00
|
|
|
struct drm_i915_private *dev_priv = engine->i915;
|
2012-11-16 11:43:20 +00:00
|
|
|
|
2017-04-03 11:34:26 +00:00
|
|
|
GEM_BUG_ON(engine->id != RCS);
|
|
|
|
|
2016-08-15 09:48:57 +00:00
|
|
|
dev_priv->status_page_dmah =
|
|
|
|
drm_pci_alloc(&dev_priv->drm, PAGE_SIZE, PAGE_SIZE);
|
|
|
|
if (!dev_priv->status_page_dmah)
|
|
|
|
return -ENOMEM;
|
2012-11-16 11:43:20 +00:00
|
|
|
|
2016-03-16 11:00:37 +00:00
|
|
|
engine->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
|
|
|
|
memset(engine->status_page.page_addr, 0, PAGE_SIZE);
|
2012-11-16 11:43:20 +00:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2017-04-03 11:34:25 +00:00
|
|
|
int intel_ring_pin(struct intel_ring *ring,
|
|
|
|
struct drm_i915_private *i915,
|
|
|
|
unsigned int offset_bias)
|
2014-11-13 10:28:56 +00:00
|
|
|
{
|
2017-04-03 11:34:25 +00:00
|
|
|
enum i915_map_type map = HAS_LLC(i915) ? I915_MAP_WB : I915_MAP_WC;
|
2016-08-15 09:48:57 +00:00
|
|
|
struct i915_vma *vma = ring->vma;
|
2017-04-03 11:34:25 +00:00
|
|
|
unsigned int flags;
|
2016-04-12 13:46:16 +00:00
|
|
|
void *addr;
|
2014-11-13 10:28:56 +00:00
|
|
|
int ret;
|
|
|
|
|
2016-08-15 09:48:57 +00:00
|
|
|
GEM_BUG_ON(ring->vaddr);
|
2014-11-13 10:28:56 +00:00
|
|
|
|
2016-08-18 16:16:56 +00:00
|
|
|
|
2016-12-23 23:56:21 +00:00
|
|
|
flags = PIN_GLOBAL;
|
|
|
|
if (offset_bias)
|
|
|
|
flags |= PIN_OFFSET_BIAS | offset_bias;
|
2016-08-18 16:16:56 +00:00
|
|
|
if (vma->obj->stolen)
|
2016-08-15 09:48:57 +00:00
|
|
|
flags |= PIN_MAPPABLE;
|
2015-10-08 12:39:54 +00:00
|
|
|
|
2016-08-15 09:48:57 +00:00
|
|
|
if (!(vma->flags & I915_VMA_GLOBAL_BIND)) {
|
2016-08-18 16:16:56 +00:00
|
|
|
if (flags & PIN_MAPPABLE || map == I915_MAP_WC)
|
2016-08-15 09:48:57 +00:00
|
|
|
ret = i915_gem_object_set_to_gtt_domain(vma->obj, true);
|
|
|
|
else
|
|
|
|
ret = i915_gem_object_set_to_cpu_domain(vma->obj, true);
|
|
|
|
if (unlikely(ret))
|
2015-10-08 12:39:54 +00:00
|
|
|
return ret;
|
2016-08-15 09:48:57 +00:00
|
|
|
}
|
2014-11-13 10:28:56 +00:00
|
|
|
|
2016-08-15 09:48:57 +00:00
|
|
|
ret = i915_vma_pin(vma, 0, PAGE_SIZE, flags);
|
|
|
|
if (unlikely(ret))
|
|
|
|
return ret;
|
2015-10-08 12:39:54 +00:00
|
|
|
|
2016-08-18 16:16:56 +00:00
|
|
|
if (i915_vma_is_map_and_fenceable(vma))
|
2016-08-15 09:48:57 +00:00
|
|
|
addr = (void __force *)i915_vma_pin_iomap(vma);
|
|
|
|
else
|
2016-08-18 16:16:56 +00:00
|
|
|
addr = i915_gem_object_pin_map(vma->obj, map);
|
2016-08-15 09:48:57 +00:00
|
|
|
if (IS_ERR(addr))
|
|
|
|
goto err;
|
2014-11-13 10:28:56 +00:00
|
|
|
|
2016-08-02 21:50:22 +00:00
|
|
|
ring->vaddr = addr;
|
2014-11-13 10:28:56 +00:00
|
|
|
return 0;
|
2016-04-08 11:11:10 +00:00
|
|
|
|
2016-08-15 09:48:57 +00:00
|
|
|
err:
|
|
|
|
i915_vma_unpin(vma);
|
|
|
|
return PTR_ERR(addr);
|
2014-11-13 10:28:56 +00:00
|
|
|
}
|
|
|
|
|
2017-04-25 13:00:49 +00:00
|
|
|
void intel_ring_reset(struct intel_ring *ring, u32 tail)
|
|
|
|
{
|
|
|
|
GEM_BUG_ON(!list_empty(&ring->request_list));
|
|
|
|
ring->tail = tail;
|
|
|
|
ring->head = tail;
|
|
|
|
ring->emit = tail;
|
|
|
|
intel_ring_update_space(ring);
|
|
|
|
}
|
|
|
|
|
2016-08-02 21:50:23 +00:00
|
|
|
void intel_ring_unpin(struct intel_ring *ring)
|
|
|
|
{
|
|
|
|
GEM_BUG_ON(!ring->vma);
|
|
|
|
GEM_BUG_ON(!ring->vaddr);
|
|
|
|
|
2017-04-25 13:00:49 +00:00
|
|
|
/* Discard any unused bytes beyond that submitted to hw. */
|
|
|
|
intel_ring_reset(ring, ring->tail);
|
|
|
|
|
2016-08-18 16:16:56 +00:00
|
|
|
if (i915_vma_is_map_and_fenceable(ring->vma))
|
2016-08-02 21:50:23 +00:00
|
|
|
i915_vma_unpin_iomap(ring->vma);
|
2016-08-15 09:48:57 +00:00
|
|
|
else
|
|
|
|
i915_gem_object_unpin_map(ring->vma->obj);
|
2016-08-02 21:50:23 +00:00
|
|
|
ring->vaddr = NULL;
|
|
|
|
|
2016-08-15 09:48:57 +00:00
|
|
|
i915_vma_unpin(ring->vma);
|
2014-07-03 15:28:02 +00:00
|
|
|
}
|
|
|
|
|
2016-08-15 09:48:57 +00:00
|
|
|
static struct i915_vma *
|
|
|
|
intel_ring_create_vma(struct drm_i915_private *dev_priv, int size)
|
2010-05-21 20:26:39 +00:00
|
|
|
{
|
2010-11-08 19:18:58 +00:00
|
|
|
struct drm_i915_gem_object *obj;
|
2016-08-15 09:48:57 +00:00
|
|
|
struct i915_vma *vma;
|
2010-05-21 20:26:39 +00:00
|
|
|
|
2016-12-01 14:16:36 +00:00
|
|
|
obj = i915_gem_object_create_stolen(dev_priv, size);
|
2016-08-18 16:16:57 +00:00
|
|
|
if (!obj)
|
2017-04-20 10:17:09 +00:00
|
|
|
obj = i915_gem_object_create_internal(dev_priv, size);
|
2016-08-15 09:48:57 +00:00
|
|
|
if (IS_ERR(obj))
|
|
|
|
return ERR_CAST(obj);
|
2010-05-21 01:08:55 +00:00
|
|
|
|
2014-06-17 05:29:42 +00:00
|
|
|
/* mark ring buffers as read-only from GPU side by default */
|
|
|
|
obj->gt_ro = 1;
|
|
|
|
|
2017-01-16 15:21:30 +00:00
|
|
|
vma = i915_vma_instance(obj, &dev_priv->ggtt.base, NULL);
|
2016-08-15 09:48:57 +00:00
|
|
|
if (IS_ERR(vma))
|
|
|
|
goto err;
|
|
|
|
|
|
|
|
return vma;
|
2014-04-09 08:19:41 +00:00
|
|
|
|
2016-08-15 09:48:57 +00:00
|
|
|
err:
|
|
|
|
i915_gem_object_put(obj);
|
|
|
|
return vma;
|
2014-04-09 08:19:41 +00:00
|
|
|
}
|
|
|
|
|
2016-08-02 21:50:21 +00:00
|
|
|
struct intel_ring *
|
|
|
|
intel_engine_create_ring(struct intel_engine_cs *engine, int size)
|
2015-09-03 12:01:39 +00:00
|
|
|
{
|
2016-08-02 21:50:21 +00:00
|
|
|
struct intel_ring *ring;
|
2016-08-15 09:48:57 +00:00
|
|
|
struct i915_vma *vma;
|
2015-09-03 12:01:39 +00:00
|
|
|
|
2016-08-02 21:50:30 +00:00
|
|
|
GEM_BUG_ON(!is_power_of_2(size));
|
2016-10-04 20:11:25 +00:00
|
|
|
GEM_BUG_ON(RING_CTL_SIZE(size) & ~RING_NR_PAGES);
|
2016-08-02 21:50:30 +00:00
|
|
|
|
2015-09-03 12:01:39 +00:00
|
|
|
ring = kzalloc(sizeof(*ring), GFP_KERNEL);
|
2016-08-15 09:48:57 +00:00
|
|
|
if (!ring)
|
2015-09-03 12:01:39 +00:00
|
|
|
return ERR_PTR(-ENOMEM);
|
|
|
|
|
2016-08-04 06:52:36 +00:00
|
|
|
INIT_LIST_HEAD(&ring->request_list);
|
|
|
|
|
2015-09-03 12:01:39 +00:00
|
|
|
ring->size = size;
|
|
|
|
/* Workaround an erratum on the i830 which causes a hang if
|
|
|
|
* the TAIL pointer points to within the last 2 cachelines
|
|
|
|
* of the buffer.
|
|
|
|
*/
|
|
|
|
ring->effective_size = size;
|
2016-11-30 15:43:04 +00:00
|
|
|
if (IS_I830(engine->i915) || IS_I845G(engine->i915))
|
2015-09-03 12:01:39 +00:00
|
|
|
ring->effective_size -= 2 * CACHELINE_BYTES;
|
|
|
|
|
|
|
|
intel_ring_update_space(ring);
|
|
|
|
|
2016-08-15 09:48:57 +00:00
|
|
|
vma = intel_ring_create_vma(engine->i915, size);
|
|
|
|
if (IS_ERR(vma)) {
|
2015-09-03 12:01:39 +00:00
|
|
|
kfree(ring);
|
2016-08-15 09:48:57 +00:00
|
|
|
return ERR_CAST(vma);
|
2015-09-03 12:01:39 +00:00
|
|
|
}
|
2016-08-15 09:48:57 +00:00
|
|
|
ring->vma = vma;
|
2015-09-03 12:01:39 +00:00
|
|
|
|
|
|
|
return ring;
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
2016-08-02 21:50:21 +00:00
|
|
|
intel_ring_free(struct intel_ring *ring)
|
2015-09-03 12:01:39 +00:00
|
|
|
{
|
2016-10-28 12:58:29 +00:00
|
|
|
struct drm_i915_gem_object *obj = ring->vma->obj;
|
|
|
|
|
|
|
|
i915_vma_close(ring->vma);
|
|
|
|
__i915_gem_object_release_unless_active(obj);
|
|
|
|
|
2015-09-03 12:01:39 +00:00
|
|
|
kfree(ring);
|
|
|
|
}
|
|
|
|
|
2017-02-10 10:14:22 +00:00
|
|
|
static int context_pin(struct i915_gem_context *ctx)
|
drm/i915: Unify active context tracking between legacy/execlists/guc
The requests conversion introduced a nasty bug where we could generate a
new request in the middle of constructing a request if we needed to idle
the system in order to evict space for a context. The request to idle
would be executed (and waited upon) before the current one, creating a
minor havoc in the seqno accounting, as we will consider the current
request to already be completed (prior to deferred seqno assignment) but
ring->last_retired_head would have been updated and still could allow
us to overwrite the current request before execution.
We also employed two different mechanisms to track the active context
until it was switched out. The legacy method allowed for waiting upon an
active context (it could forcibly evict any vma, including context's),
but the execlists method took a step backwards by pinning the vma for
the entire active lifespan of the context (the only way to evict was to
idle the entire GPU, not individual contexts). However, to circumvent
the tricky issue of locking (i.e. we cannot take struct_mutex at the
time of i915_gem_request_submit(), where we would want to move the
previous context onto the active tracker and unpin it), we take the
execlists approach and keep the contexts pinned until retirement.
The benefit of the execlists approach, more important for execlists than
legacy, was the reduction in work in pinning the context for each
request - as the context was kept pinned until idle, it could short
circuit the pinning for all active contexts.
We introduce new engine vfuncs to pin and unpin the context
respectively. The context is pinned at the start of the request, and
only unpinned when the following request is retired (this ensures that
the context is idle and coherent in main memory before we unpin it). We
move the engine->last_context tracking into the retirement itself
(rather than during request submission) in order to allow the submission
to be reordered or unwound without undue difficultly.
And finally an ulterior motive for unifying context handling was to
prepare for mock requests.
v2: Rename to last_retired_context, split out legacy_context tracking
for MI_SET_CONTEXT.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20161218153724.8439-3-chris@chris-wilson.co.uk
2016-12-18 15:37:20 +00:00
|
|
|
{
|
|
|
|
struct i915_vma *vma = ctx->engine[RCS].state;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
/* Clear this page out of any CPU caches for coherent swap-in/out.
|
|
|
|
* We only want to do this on the first bind so that we do not stall
|
|
|
|
* on an active context (which by nature is already on the GPU).
|
|
|
|
*/
|
|
|
|
if (!(vma->flags & I915_VMA_GLOBAL_BIND)) {
|
|
|
|
ret = i915_gem_object_set_to_gtt_domain(vma->obj, false);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2017-02-27 13:59:13 +00:00
|
|
|
return i915_vma_pin(vma, 0, I915_GTT_MIN_ALIGNMENT,
|
|
|
|
PIN_GLOBAL | PIN_HIGH);
|
drm/i915: Unify active context tracking between legacy/execlists/guc
The requests conversion introduced a nasty bug where we could generate a
new request in the middle of constructing a request if we needed to idle
the system in order to evict space for a context. The request to idle
would be executed (and waited upon) before the current one, creating a
minor havoc in the seqno accounting, as we will consider the current
request to already be completed (prior to deferred seqno assignment) but
ring->last_retired_head would have been updated and still could allow
us to overwrite the current request before execution.
We also employed two different mechanisms to track the active context
until it was switched out. The legacy method allowed for waiting upon an
active context (it could forcibly evict any vma, including context's),
but the execlists method took a step backwards by pinning the vma for
the entire active lifespan of the context (the only way to evict was to
idle the entire GPU, not individual contexts). However, to circumvent
the tricky issue of locking (i.e. we cannot take struct_mutex at the
time of i915_gem_request_submit(), where we would want to move the
previous context onto the active tracker and unpin it), we take the
execlists approach and keep the contexts pinned until retirement.
The benefit of the execlists approach, more important for execlists than
legacy, was the reduction in work in pinning the context for each
request - as the context was kept pinned until idle, it could short
circuit the pinning for all active contexts.
We introduce new engine vfuncs to pin and unpin the context
respectively. The context is pinned at the start of the request, and
only unpinned when the following request is retired (this ensures that
the context is idle and coherent in main memory before we unpin it). We
move the engine->last_context tracking into the retirement itself
(rather than during request submission) in order to allow the submission
to be reordered or unwound without undue difficultly.
And finally an ulterior motive for unifying context handling was to
prepare for mock requests.
v2: Rename to last_retired_context, split out legacy_context tracking
for MI_SET_CONTEXT.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20161218153724.8439-3-chris@chris-wilson.co.uk
2016-12-18 15:37:20 +00:00
|
|
|
}
|
|
|
|
|
2017-04-27 10:46:51 +00:00
|
|
|
static struct i915_vma *
|
|
|
|
alloc_context_vma(struct intel_engine_cs *engine)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *i915 = engine->i915;
|
|
|
|
struct drm_i915_gem_object *obj;
|
|
|
|
struct i915_vma *vma;
|
|
|
|
|
2017-04-28 07:53:36 +00:00
|
|
|
obj = i915_gem_object_create(i915, engine->context_size);
|
2017-04-27 10:46:51 +00:00
|
|
|
if (IS_ERR(obj))
|
|
|
|
return ERR_CAST(obj);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Try to make the context utilize L3 as well as LLC.
|
|
|
|
*
|
|
|
|
* On VLV we don't have L3 controls in the PTEs so we
|
|
|
|
* shouldn't touch the cache level, especially as that
|
|
|
|
* would make the object snooped which might have a
|
|
|
|
* negative performance impact.
|
|
|
|
*
|
|
|
|
* Snooping is required on non-llc platforms in execlist
|
|
|
|
* mode, but since all GGTT accesses use PAT entry 0 we
|
|
|
|
* get snooping anyway regardless of cache_level.
|
|
|
|
*
|
|
|
|
* This is only applicable for Ivy Bridge devices since
|
|
|
|
* later platforms don't have L3 control bits in the PTE.
|
|
|
|
*/
|
|
|
|
if (IS_IVYBRIDGE(i915)) {
|
|
|
|
/* Ignore any error, regard it as a simple optimisation */
|
|
|
|
i915_gem_object_set_cache_level(obj, I915_CACHE_L3_LLC);
|
|
|
|
}
|
|
|
|
|
|
|
|
vma = i915_vma_instance(obj, &i915->ggtt.base, NULL);
|
|
|
|
if (IS_ERR(vma))
|
|
|
|
i915_gem_object_put(obj);
|
|
|
|
|
|
|
|
return vma;
|
|
|
|
}
|
|
|
|
|
2017-05-04 09:33:08 +00:00
|
|
|
static struct intel_ring *
|
|
|
|
intel_ring_context_pin(struct intel_engine_cs *engine,
|
|
|
|
struct i915_gem_context *ctx)
|
2016-06-24 13:55:53 +00:00
|
|
|
{
|
|
|
|
struct intel_context *ce = &ctx->engine[engine->id];
|
|
|
|
int ret;
|
|
|
|
|
2016-07-05 09:40:23 +00:00
|
|
|
lockdep_assert_held(&ctx->i915->drm.struct_mutex);
|
2016-06-24 13:55:53 +00:00
|
|
|
|
2017-05-04 09:33:08 +00:00
|
|
|
if (likely(ce->pin_count++))
|
|
|
|
goto out;
|
2017-03-16 17:16:28 +00:00
|
|
|
GEM_BUG_ON(!ce->pin_count); /* no overflow please! */
|
2016-06-24 13:55:53 +00:00
|
|
|
|
2017-04-28 07:53:36 +00:00
|
|
|
if (!ce->state && engine->context_size) {
|
2017-04-27 10:46:51 +00:00
|
|
|
struct i915_vma *vma;
|
|
|
|
|
|
|
|
vma = alloc_context_vma(engine);
|
|
|
|
if (IS_ERR(vma)) {
|
|
|
|
ret = PTR_ERR(vma);
|
2017-05-04 09:33:08 +00:00
|
|
|
goto err;
|
2017-04-27 10:46:51 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
ce->state = vma;
|
|
|
|
}
|
|
|
|
|
2016-06-24 13:55:53 +00:00
|
|
|
if (ce->state) {
|
2017-02-10 10:14:22 +00:00
|
|
|
ret = context_pin(ctx);
|
drm/i915: Unify active context tracking between legacy/execlists/guc
The requests conversion introduced a nasty bug where we could generate a
new request in the middle of constructing a request if we needed to idle
the system in order to evict space for a context. The request to idle
would be executed (and waited upon) before the current one, creating a
minor havoc in the seqno accounting, as we will consider the current
request to already be completed (prior to deferred seqno assignment) but
ring->last_retired_head would have been updated and still could allow
us to overwrite the current request before execution.
We also employed two different mechanisms to track the active context
until it was switched out. The legacy method allowed for waiting upon an
active context (it could forcibly evict any vma, including context's),
but the execlists method took a step backwards by pinning the vma for
the entire active lifespan of the context (the only way to evict was to
idle the entire GPU, not individual contexts). However, to circumvent
the tricky issue of locking (i.e. we cannot take struct_mutex at the
time of i915_gem_request_submit(), where we would want to move the
previous context onto the active tracker and unpin it), we take the
execlists approach and keep the contexts pinned until retirement.
The benefit of the execlists approach, more important for execlists than
legacy, was the reduction in work in pinning the context for each
request - as the context was kept pinned until idle, it could short
circuit the pinning for all active contexts.
We introduce new engine vfuncs to pin and unpin the context
respectively. The context is pinned at the start of the request, and
only unpinned when the following request is retired (this ensures that
the context is idle and coherent in main memory before we unpin it). We
move the engine->last_context tracking into the retirement itself
(rather than during request submission) in order to allow the submission
to be reordered or unwound without undue difficultly.
And finally an ulterior motive for unifying context handling was to
prepare for mock requests.
v2: Rename to last_retired_context, split out legacy_context tracking
for MI_SET_CONTEXT.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20161218153724.8439-3-chris@chris-wilson.co.uk
2016-12-18 15:37:20 +00:00
|
|
|
if (ret)
|
2017-05-04 09:33:08 +00:00
|
|
|
goto err;
|
2017-03-22 20:59:30 +00:00
|
|
|
|
|
|
|
ce->state->obj->mm.dirty = true;
|
2016-06-24 13:55:53 +00:00
|
|
|
}
|
|
|
|
|
2016-06-24 13:55:54 +00:00
|
|
|
/* The kernel context is only used as a placeholder for flushing the
|
|
|
|
* active context. It is never used for submitting user rendering and
|
|
|
|
* as such never requires the golden render context, and so we can skip
|
|
|
|
* emitting it when we switch to the kernel context. This is required
|
|
|
|
* as during eviction we cannot allocate and pin the renderstate in
|
|
|
|
* order to initialise the context.
|
|
|
|
*/
|
2017-01-06 15:20:13 +00:00
|
|
|
if (i915_gem_context_is_kernel(ctx))
|
2016-06-24 13:55:54 +00:00
|
|
|
ce->initialised = true;
|
|
|
|
|
2016-07-20 12:31:50 +00:00
|
|
|
i915_gem_context_get(ctx);
|
2016-06-24 13:55:53 +00:00
|
|
|
|
2017-05-04 09:33:08 +00:00
|
|
|
out:
|
|
|
|
/* One ringbuffer to rule them all */
|
|
|
|
return engine->buffer;
|
|
|
|
|
|
|
|
err:
|
2016-06-24 13:55:53 +00:00
|
|
|
ce->pin_count = 0;
|
2017-05-04 09:33:08 +00:00
|
|
|
return ERR_PTR(ret);
|
2016-06-24 13:55:53 +00:00
|
|
|
}
|
|
|
|
|
drm/i915: Unify active context tracking between legacy/execlists/guc
The requests conversion introduced a nasty bug where we could generate a
new request in the middle of constructing a request if we needed to idle
the system in order to evict space for a context. The request to idle
would be executed (and waited upon) before the current one, creating a
minor havoc in the seqno accounting, as we will consider the current
request to already be completed (prior to deferred seqno assignment) but
ring->last_retired_head would have been updated and still could allow
us to overwrite the current request before execution.
We also employed two different mechanisms to track the active context
until it was switched out. The legacy method allowed for waiting upon an
active context (it could forcibly evict any vma, including context's),
but the execlists method took a step backwards by pinning the vma for
the entire active lifespan of the context (the only way to evict was to
idle the entire GPU, not individual contexts). However, to circumvent
the tricky issue of locking (i.e. we cannot take struct_mutex at the
time of i915_gem_request_submit(), where we would want to move the
previous context onto the active tracker and unpin it), we take the
execlists approach and keep the contexts pinned until retirement.
The benefit of the execlists approach, more important for execlists than
legacy, was the reduction in work in pinning the context for each
request - as the context was kept pinned until idle, it could short
circuit the pinning for all active contexts.
We introduce new engine vfuncs to pin and unpin the context
respectively. The context is pinned at the start of the request, and
only unpinned when the following request is retired (this ensures that
the context is idle and coherent in main memory before we unpin it). We
move the engine->last_context tracking into the retirement itself
(rather than during request submission) in order to allow the submission
to be reordered or unwound without undue difficultly.
And finally an ulterior motive for unifying context handling was to
prepare for mock requests.
v2: Rename to last_retired_context, split out legacy_context tracking
for MI_SET_CONTEXT.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20161218153724.8439-3-chris@chris-wilson.co.uk
2016-12-18 15:37:20 +00:00
|
|
|
static void intel_ring_context_unpin(struct intel_engine_cs *engine,
|
|
|
|
struct i915_gem_context *ctx)
|
2016-06-24 13:55:53 +00:00
|
|
|
{
|
|
|
|
struct intel_context *ce = &ctx->engine[engine->id];
|
|
|
|
|
2016-07-05 09:40:23 +00:00
|
|
|
lockdep_assert_held(&ctx->i915->drm.struct_mutex);
|
drm/i915: Unify active context tracking between legacy/execlists/guc
The requests conversion introduced a nasty bug where we could generate a
new request in the middle of constructing a request if we needed to idle
the system in order to evict space for a context. The request to idle
would be executed (and waited upon) before the current one, creating a
minor havoc in the seqno accounting, as we will consider the current
request to already be completed (prior to deferred seqno assignment) but
ring->last_retired_head would have been updated and still could allow
us to overwrite the current request before execution.
We also employed two different mechanisms to track the active context
until it was switched out. The legacy method allowed for waiting upon an
active context (it could forcibly evict any vma, including context's),
but the execlists method took a step backwards by pinning the vma for
the entire active lifespan of the context (the only way to evict was to
idle the entire GPU, not individual contexts). However, to circumvent
the tricky issue of locking (i.e. we cannot take struct_mutex at the
time of i915_gem_request_submit(), where we would want to move the
previous context onto the active tracker and unpin it), we take the
execlists approach and keep the contexts pinned until retirement.
The benefit of the execlists approach, more important for execlists than
legacy, was the reduction in work in pinning the context for each
request - as the context was kept pinned until idle, it could short
circuit the pinning for all active contexts.
We introduce new engine vfuncs to pin and unpin the context
respectively. The context is pinned at the start of the request, and
only unpinned when the following request is retired (this ensures that
the context is idle and coherent in main memory before we unpin it). We
move the engine->last_context tracking into the retirement itself
(rather than during request submission) in order to allow the submission
to be reordered or unwound without undue difficultly.
And finally an ulterior motive for unifying context handling was to
prepare for mock requests.
v2: Rename to last_retired_context, split out legacy_context tracking
for MI_SET_CONTEXT.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20161218153724.8439-3-chris@chris-wilson.co.uk
2016-12-18 15:37:20 +00:00
|
|
|
GEM_BUG_ON(ce->pin_count == 0);
|
2016-06-24 13:55:53 +00:00
|
|
|
|
|
|
|
if (--ce->pin_count)
|
|
|
|
return;
|
|
|
|
|
|
|
|
if (ce->state)
|
2016-08-15 09:48:54 +00:00
|
|
|
i915_vma_unpin(ce->state);
|
2016-06-24 13:55:53 +00:00
|
|
|
|
2016-07-20 12:31:50 +00:00
|
|
|
i915_gem_context_put(ctx);
|
2016-06-24 13:55:53 +00:00
|
|
|
}
|
|
|
|
|
2016-07-13 15:03:39 +00:00
|
|
|
static int intel_init_ring_buffer(struct intel_engine_cs *engine)
|
2014-04-09 08:19:41 +00:00
|
|
|
{
|
2016-08-02 21:50:22 +00:00
|
|
|
struct intel_ring *ring;
|
2017-04-03 11:34:26 +00:00
|
|
|
int err;
|
2014-11-19 23:33:08 +00:00
|
|
|
|
2016-07-13 15:03:41 +00:00
|
|
|
intel_engine_setup_common(engine);
|
|
|
|
|
2017-04-03 11:34:26 +00:00
|
|
|
err = intel_engine_init_common(engine);
|
|
|
|
if (err)
|
|
|
|
goto err;
|
2014-04-09 08:19:41 +00:00
|
|
|
|
2017-04-03 11:34:26 +00:00
|
|
|
if (HWS_NEEDS_PHYSICAL(engine->i915))
|
|
|
|
err = init_phys_status_page(engine);
|
|
|
|
else
|
|
|
|
err = init_status_page(engine);
|
|
|
|
if (err)
|
|
|
|
goto err;
|
2014-04-09 08:19:41 +00:00
|
|
|
|
2017-04-03 11:34:25 +00:00
|
|
|
ring = intel_engine_create_ring(engine, 32 * PAGE_SIZE);
|
|
|
|
if (IS_ERR(ring)) {
|
2017-04-03 11:34:26 +00:00
|
|
|
err = PTR_ERR(ring);
|
|
|
|
goto err_hws;
|
2017-04-03 11:34:25 +00:00
|
|
|
}
|
|
|
|
|
2016-12-23 23:56:21 +00:00
|
|
|
/* Ring wraparound at offset 0 sometimes hangs. No idea why. */
|
2017-04-03 11:34:26 +00:00
|
|
|
err = intel_ring_pin(ring, engine->i915, I915_GTT_PAGE_SIZE);
|
|
|
|
if (err)
|
|
|
|
goto err_ring;
|
|
|
|
|
|
|
|
GEM_BUG_ON(engine->buffer);
|
2016-08-15 09:48:57 +00:00
|
|
|
engine->buffer = ring;
|
2010-05-21 20:26:39 +00:00
|
|
|
|
2014-05-22 13:13:34 +00:00
|
|
|
return 0;
|
2014-02-18 18:15:46 +00:00
|
|
|
|
2017-04-03 11:34:26 +00:00
|
|
|
err_ring:
|
|
|
|
intel_ring_free(ring);
|
|
|
|
err_hws:
|
|
|
|
if (HWS_NEEDS_PHYSICAL(engine->i915))
|
|
|
|
cleanup_phys_status_page(engine);
|
|
|
|
else
|
|
|
|
cleanup_status_page(engine);
|
|
|
|
err:
|
|
|
|
intel_engine_cleanup_common(engine);
|
|
|
|
return err;
|
2010-05-21 20:26:39 +00:00
|
|
|
}
|
|
|
|
|
2016-08-02 21:50:21 +00:00
|
|
|
void intel_engine_cleanup(struct intel_engine_cs *engine)
|
2010-05-21 20:26:39 +00:00
|
|
|
{
|
2017-04-03 11:34:26 +00:00
|
|
|
struct drm_i915_private *dev_priv = engine->i915;
|
2014-10-31 12:00:26 +00:00
|
|
|
|
2017-04-03 11:34:26 +00:00
|
|
|
WARN_ON(INTEL_GEN(dev_priv) > 2 &&
|
|
|
|
(I915_READ_MODE(engine) & MODE_IDLE) == 0);
|
2010-10-29 15:18:36 +00:00
|
|
|
|
2017-04-03 11:34:26 +00:00
|
|
|
intel_ring_unpin(engine->buffer);
|
|
|
|
intel_ring_free(engine->buffer);
|
2010-10-27 11:18:21 +00:00
|
|
|
|
2016-03-16 11:00:37 +00:00
|
|
|
if (engine->cleanup)
|
|
|
|
engine->cleanup(engine);
|
2010-11-02 08:31:01 +00:00
|
|
|
|
2017-04-03 11:34:26 +00:00
|
|
|
if (HWS_NEEDS_PHYSICAL(dev_priv))
|
2016-03-16 11:00:37 +00:00
|
|
|
cleanup_phys_status_page(engine);
|
2017-04-03 11:34:26 +00:00
|
|
|
else
|
2016-08-17 19:30:56 +00:00
|
|
|
cleanup_status_page(engine);
|
2014-05-10 21:10:43 +00:00
|
|
|
|
2016-08-03 12:19:16 +00:00
|
|
|
intel_engine_cleanup_common(engine);
|
2016-06-24 13:55:53 +00:00
|
|
|
|
drm/i915: Allocate intel_engine_cs structure only for the enabled engines
With the possibility of addition of many more number of rings in future,
the drm_i915_private structure could bloat as an array, of type
intel_engine_cs, is embedded inside it.
struct intel_engine_cs engine[I915_NUM_ENGINES];
Though this is still fine as generally there is only a single instance of
drm_i915_private structure used, but not all of the possible rings would be
enabled or active on most of the platforms. Some memory can be saved by
allocating intel_engine_cs structure only for the enabled/active engines.
Currently the engine/ring ID is kept static and dev_priv->engine[] is simply
indexed using the enums defined in intel_engine_id.
To save memory and continue using the static engine/ring IDs, 'engine' is
defined as an array of pointers.
struct intel_engine_cs *engine[I915_NUM_ENGINES];
dev_priv->engine[engine_ID] will be NULL for disabled engine instances.
There is a text size reduction of 928 bytes, from 1028200 to 1027272, for
i915.o file (but for i915.ko file text size remain same as 1193131 bytes).
v2:
- Remove the engine iterator field added in drm_i915_private structure,
instead pass a local iterator variable to the for_each_engine**
macros. (Chris)
- Do away with intel_engine_initialized() and instead directly use the
NULL pointer check on engine pointer. (Chris)
v3:
- Remove for_each_engine_id() macro, as the updated macro for_each_engine()
can be used in place of it. (Chris)
- Protect the access to Render engine Fault register with a NULL check, as
engine specific init is done later in Driver load sequence.
v4:
- Use !!dev_priv->engine[VCS] style for the engine check in getparam. (Chris)
- Kill the superfluous init_engine_lists().
v5:
- Cleanup the intel_engines_init() & intel_engines_setup(), with respect to
allocation of intel_engine_cs structure. (Chris)
v6:
- Rebase.
v7:
- Optimize the for_each_engine_masked() macro. (Chris)
- Change the type of 'iter' local variable to enum intel_engine_id. (Chris)
- Rebase.
v8: Rebase.
v9: Rebase.
v10:
- For index calculation use engine ID instead of pointer based arithmetic in
intel_engine_sync_index() as engine pointers are not contiguous now (Chris)
- For appropriateness, rename local enum variable 'iter' to 'id'. (Joonas)
- Use for_each_engine macro for cleanup in intel_engines_init() and remove
check for NULL engine pointer in cleanup() routines. (Joonas)
v11: Rebase.
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Akash Goel <akash.goel@intel.com>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1476378888-7372-1-git-send-email-akash.goel@intel.com
2016-10-13 17:14:48 +00:00
|
|
|
dev_priv->engine[engine->id] = NULL;
|
|
|
|
kfree(engine);
|
2010-05-21 20:26:39 +00:00
|
|
|
}
|
|
|
|
|
2016-09-09 13:11:53 +00:00
|
|
|
void intel_legacy_submission_resume(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
|
|
|
struct intel_engine_cs *engine;
|
drm/i915: Allocate intel_engine_cs structure only for the enabled engines
With the possibility of addition of many more number of rings in future,
the drm_i915_private structure could bloat as an array, of type
intel_engine_cs, is embedded inside it.
struct intel_engine_cs engine[I915_NUM_ENGINES];
Though this is still fine as generally there is only a single instance of
drm_i915_private structure used, but not all of the possible rings would be
enabled or active on most of the platforms. Some memory can be saved by
allocating intel_engine_cs structure only for the enabled/active engines.
Currently the engine/ring ID is kept static and dev_priv->engine[] is simply
indexed using the enums defined in intel_engine_id.
To save memory and continue using the static engine/ring IDs, 'engine' is
defined as an array of pointers.
struct intel_engine_cs *engine[I915_NUM_ENGINES];
dev_priv->engine[engine_ID] will be NULL for disabled engine instances.
There is a text size reduction of 928 bytes, from 1028200 to 1027272, for
i915.o file (but for i915.ko file text size remain same as 1193131 bytes).
v2:
- Remove the engine iterator field added in drm_i915_private structure,
instead pass a local iterator variable to the for_each_engine**
macros. (Chris)
- Do away with intel_engine_initialized() and instead directly use the
NULL pointer check on engine pointer. (Chris)
v3:
- Remove for_each_engine_id() macro, as the updated macro for_each_engine()
can be used in place of it. (Chris)
- Protect the access to Render engine Fault register with a NULL check, as
engine specific init is done later in Driver load sequence.
v4:
- Use !!dev_priv->engine[VCS] style for the engine check in getparam. (Chris)
- Kill the superfluous init_engine_lists().
v5:
- Cleanup the intel_engines_init() & intel_engines_setup(), with respect to
allocation of intel_engine_cs structure. (Chris)
v6:
- Rebase.
v7:
- Optimize the for_each_engine_masked() macro. (Chris)
- Change the type of 'iter' local variable to enum intel_engine_id. (Chris)
- Rebase.
v8: Rebase.
v9: Rebase.
v10:
- For index calculation use engine ID instead of pointer based arithmetic in
intel_engine_sync_index() as engine pointers are not contiguous now (Chris)
- For appropriateness, rename local enum variable 'iter' to 'id'. (Joonas)
- Use for_each_engine macro for cleanup in intel_engines_init() and remove
check for NULL engine pointer in cleanup() routines. (Joonas)
v11: Rebase.
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Akash Goel <akash.goel@intel.com>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1476378888-7372-1-git-send-email-akash.goel@intel.com
2016-10-13 17:14:48 +00:00
|
|
|
enum intel_engine_id id;
|
2016-09-09 13:11:53 +00:00
|
|
|
|
2017-04-25 13:00:49 +00:00
|
|
|
/* Restart from the beginning of the rings for convenience */
|
2017-03-21 10:25:52 +00:00
|
|
|
for_each_engine(engine, dev_priv, id)
|
2017-04-25 13:00:49 +00:00
|
|
|
intel_ring_reset(engine->buffer, 0);
|
2016-09-09 13:11:53 +00:00
|
|
|
}
|
|
|
|
|
2016-12-18 15:37:24 +00:00
|
|
|
static int ring_request_alloc(struct drm_i915_gem_request *request)
|
2012-11-27 16:22:52 +00:00
|
|
|
{
|
2017-02-14 11:32:42 +00:00
|
|
|
u32 *cs;
|
2016-04-28 08:56:49 +00:00
|
|
|
|
drm/i915: Unify active context tracking between legacy/execlists/guc
The requests conversion introduced a nasty bug where we could generate a
new request in the middle of constructing a request if we needed to idle
the system in order to evict space for a context. The request to idle
would be executed (and waited upon) before the current one, creating a
minor havoc in the seqno accounting, as we will consider the current
request to already be completed (prior to deferred seqno assignment) but
ring->last_retired_head would have been updated and still could allow
us to overwrite the current request before execution.
We also employed two different mechanisms to track the active context
until it was switched out. The legacy method allowed for waiting upon an
active context (it could forcibly evict any vma, including context's),
but the execlists method took a step backwards by pinning the vma for
the entire active lifespan of the context (the only way to evict was to
idle the entire GPU, not individual contexts). However, to circumvent
the tricky issue of locking (i.e. we cannot take struct_mutex at the
time of i915_gem_request_submit(), where we would want to move the
previous context onto the active tracker and unpin it), we take the
execlists approach and keep the contexts pinned until retirement.
The benefit of the execlists approach, more important for execlists than
legacy, was the reduction in work in pinning the context for each
request - as the context was kept pinned until idle, it could short
circuit the pinning for all active contexts.
We introduce new engine vfuncs to pin and unpin the context
respectively. The context is pinned at the start of the request, and
only unpinned when the following request is retired (this ensures that
the context is idle and coherent in main memory before we unpin it). We
move the engine->last_context tracking into the retirement itself
(rather than during request submission) in order to allow the submission
to be reordered or unwound without undue difficultly.
And finally an ulterior motive for unifying context handling was to
prepare for mock requests.
v2: Rename to last_retired_context, split out legacy_context tracking
for MI_SET_CONTEXT.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20161218153724.8439-3-chris@chris-wilson.co.uk
2016-12-18 15:37:20 +00:00
|
|
|
GEM_BUG_ON(!request->ctx->engine[request->engine->id].pin_count);
|
|
|
|
|
2016-04-28 08:56:49 +00:00
|
|
|
/* Flush enough space to reduce the likelihood of waiting after
|
|
|
|
* we start building the request - in which case we will just
|
|
|
|
* have to repeat work.
|
|
|
|
*/
|
2016-04-29 08:07:05 +00:00
|
|
|
request->reserved_space += LEGACY_REQUEST_SIZE;
|
2016-04-28 08:56:49 +00:00
|
|
|
|
2017-02-14 11:32:42 +00:00
|
|
|
cs = intel_ring_begin(request, 0);
|
|
|
|
if (IS_ERR(cs))
|
|
|
|
return PTR_ERR(cs);
|
2016-04-28 08:56:49 +00:00
|
|
|
|
2016-04-29 08:07:05 +00:00
|
|
|
request->reserved_space -= LEGACY_REQUEST_SIZE;
|
2016-04-28 08:56:49 +00:00
|
|
|
return 0;
|
2012-11-27 16:22:52 +00:00
|
|
|
}
|
|
|
|
|
2016-04-28 08:56:46 +00:00
|
|
|
static int wait_for_space(struct drm_i915_gem_request *req, int bytes)
|
|
|
|
{
|
2016-08-02 21:50:21 +00:00
|
|
|
struct intel_ring *ring = req->ring;
|
2016-04-28 08:56:46 +00:00
|
|
|
struct drm_i915_gem_request *target;
|
2016-10-28 12:58:27 +00:00
|
|
|
long timeout;
|
|
|
|
|
|
|
|
lockdep_assert_held(&req->i915->drm.struct_mutex);
|
2016-04-28 08:56:46 +00:00
|
|
|
|
2016-08-02 21:50:19 +00:00
|
|
|
intel_ring_update_space(ring);
|
|
|
|
if (ring->space >= bytes)
|
2016-04-28 08:56:46 +00:00
|
|
|
return 0;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Space is reserved in the ringbuffer for finalising the request,
|
|
|
|
* as that cannot be allowed to fail. During request finalisation,
|
|
|
|
* reserved_space is set to 0 to stop the overallocation and the
|
|
|
|
* assumption is that then we never need to wait (which has the
|
|
|
|
* risk of failing with EINTR).
|
|
|
|
*
|
|
|
|
* See also i915_gem_request_alloc() and i915_add_request().
|
|
|
|
*/
|
2016-04-28 08:56:47 +00:00
|
|
|
GEM_BUG_ON(!req->reserved_space);
|
2016-04-28 08:56:46 +00:00
|
|
|
|
2016-08-04 06:52:36 +00:00
|
|
|
list_for_each_entry(target, &ring->request_list, ring_link) {
|
2016-04-28 08:56:46 +00:00
|
|
|
/* Would completion of this request free enough space? */
|
2017-05-04 13:08:44 +00:00
|
|
|
if (bytes <= __intel_ring_space(target->postfix,
|
|
|
|
ring->emit, ring->size))
|
2016-04-28 08:56:46 +00:00
|
|
|
break;
|
2015-06-30 11:40:55 +00:00
|
|
|
}
|
drm/i915: Reserve ring buffer space for i915_add_request() commands
It is a bad idea for i915_add_request() to fail. The work will already have been
send to the ring and will be processed, but there will not be any tracking or
management of that work.
The only way the add request call can fail is if it can't write its epilogue
commands to the ring (cache flushing, seqno updates, interrupt signalling). The
reasons for that are mostly down to running out of ring buffer space and the
problems associated with trying to get some more. This patch prevents that
situation from happening in the first place.
When a request is created, it marks sufficient space as reserved for the
epilogue commands. Thus guaranteeing that by the time the epilogue is written,
there will be plenty of space for it. Note that a ring_begin() call is required
to actually reserve the space (and do any potential waiting). However, that is
not currently done at request creation time. This is because the ring_begin()
code can allocate a request. Hence calling begin() from the request allocation
code would lead to infinite recursion! Later patches in this series remove the
need for begin() to do the allocate. At that point, it becomes safe for the
allocate to call begin() and really reserve the space.
Until then, there is a potential for insufficient space to be available at the
point of calling i915_add_request(). However, that would only be in the case
where the request was created and immediately submitted without ever calling
ring_begin() and adding any work to that request. Which should never happen. And
even if it does, and if that request happens to fall down the tiny window of
opportunity for failing due to being out of ring space then does it really
matter because the request wasn't doing anything in the first place?
v2: Updated the 'reserved space too small' warning to include the offending
sizes. Added a 'cancel' operation to clean up when a request is abandoned. Added
re-initialisation of tracking state after a buffer wrap to keep the sanity
checks accurate.
v3: Incremented the reserved size to accommodate Ironlake (after finally
managing to run on an ILK system). Also fixed missing wrap code in LRC mode.
v4: Added extra comment and removed duplicate WARN (feedback from Tomas).
For: VIZ-5115
CC: Tomas Elf <tomas.elf@intel.com>
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-06-18 12:10:09 +00:00
|
|
|
|
2016-08-04 06:52:36 +00:00
|
|
|
if (WARN_ON(&target->ring_link == &ring->request_list))
|
2016-04-28 08:56:46 +00:00
|
|
|
return -ENOSPC;
|
|
|
|
|
2016-10-28 12:58:27 +00:00
|
|
|
timeout = i915_wait_request(target,
|
|
|
|
I915_WAIT_INTERRUPTIBLE | I915_WAIT_LOCKED,
|
|
|
|
MAX_SCHEDULE_TIMEOUT);
|
|
|
|
if (timeout < 0)
|
|
|
|
return timeout;
|
2016-08-04 06:52:38 +00:00
|
|
|
|
|
|
|
i915_gem_request_retire_upto(target);
|
|
|
|
|
|
|
|
intel_ring_update_space(ring);
|
|
|
|
GEM_BUG_ON(ring->space < bytes);
|
|
|
|
return 0;
|
drm/i915: Reserve ring buffer space for i915_add_request() commands
It is a bad idea for i915_add_request() to fail. The work will already have been
send to the ring and will be processed, but there will not be any tracking or
management of that work.
The only way the add request call can fail is if it can't write its epilogue
commands to the ring (cache flushing, seqno updates, interrupt signalling). The
reasons for that are mostly down to running out of ring buffer space and the
problems associated with trying to get some more. This patch prevents that
situation from happening in the first place.
When a request is created, it marks sufficient space as reserved for the
epilogue commands. Thus guaranteeing that by the time the epilogue is written,
there will be plenty of space for it. Note that a ring_begin() call is required
to actually reserve the space (and do any potential waiting). However, that is
not currently done at request creation time. This is because the ring_begin()
code can allocate a request. Hence calling begin() from the request allocation
code would lead to infinite recursion! Later patches in this series remove the
need for begin() to do the allocate. At that point, it becomes safe for the
allocate to call begin() and really reserve the space.
Until then, there is a potential for insufficient space to be available at the
point of calling i915_add_request(). However, that would only be in the case
where the request was created and immediately submitted without ever calling
ring_begin() and adding any work to that request. Which should never happen. And
even if it does, and if that request happens to fall down the tiny window of
opportunity for failing due to being out of ring space then does it really
matter because the request wasn't doing anything in the first place?
v2: Updated the 'reserved space too small' warning to include the offending
sizes. Added a 'cancel' operation to clean up when a request is abandoned. Added
re-initialisation of tracking state after a buffer wrap to keep the sanity
checks accurate.
v3: Incremented the reserved size to accommodate Ironlake (after finally
managing to run on an ILK system). Also fixed missing wrap code in LRC mode.
v4: Added extra comment and removed duplicate WARN (feedback from Tomas).
For: VIZ-5115
CC: Tomas Elf <tomas.elf@intel.com>
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-06-18 12:10:09 +00:00
|
|
|
}
|
|
|
|
|
2017-02-14 11:32:42 +00:00
|
|
|
u32 *intel_ring_begin(struct drm_i915_gem_request *req, int num_dwords)
|
2012-12-04 13:12:03 +00:00
|
|
|
{
|
2016-08-02 21:50:21 +00:00
|
|
|
struct intel_ring *ring = req->ring;
|
2017-04-25 13:00:49 +00:00
|
|
|
int remain_actual = ring->size - ring->emit;
|
|
|
|
int remain_usable = ring->effective_size - ring->emit;
|
2016-04-28 08:56:46 +00:00
|
|
|
int bytes = num_dwords * sizeof(u32);
|
|
|
|
int total_bytes, wait_bytes;
|
2015-06-30 11:40:55 +00:00
|
|
|
bool need_wrap = false;
|
2017-02-14 11:32:42 +00:00
|
|
|
u32 *cs;
|
drm/i915: Reserve ring buffer space for i915_add_request() commands
It is a bad idea for i915_add_request() to fail. The work will already have been
send to the ring and will be processed, but there will not be any tracking or
management of that work.
The only way the add request call can fail is if it can't write its epilogue
commands to the ring (cache flushing, seqno updates, interrupt signalling). The
reasons for that are mostly down to running out of ring buffer space and the
problems associated with trying to get some more. This patch prevents that
situation from happening in the first place.
When a request is created, it marks sufficient space as reserved for the
epilogue commands. Thus guaranteeing that by the time the epilogue is written,
there will be plenty of space for it. Note that a ring_begin() call is required
to actually reserve the space (and do any potential waiting). However, that is
not currently done at request creation time. This is because the ring_begin()
code can allocate a request. Hence calling begin() from the request allocation
code would lead to infinite recursion! Later patches in this series remove the
need for begin() to do the allocate. At that point, it becomes safe for the
allocate to call begin() and really reserve the space.
Until then, there is a potential for insufficient space to be available at the
point of calling i915_add_request(). However, that would only be in the case
where the request was created and immediately submitted without ever calling
ring_begin() and adding any work to that request. Which should never happen. And
even if it does, and if that request happens to fall down the tiny window of
opportunity for failing due to being out of ring space then does it really
matter because the request wasn't doing anything in the first place?
v2: Updated the 'reserved space too small' warning to include the offending
sizes. Added a 'cancel' operation to clean up when a request is abandoned. Added
re-initialisation of tracking state after a buffer wrap to keep the sanity
checks accurate.
v3: Incremented the reserved size to accommodate Ironlake (after finally
managing to run on an ILK system). Also fixed missing wrap code in LRC mode.
v4: Added extra comment and removed duplicate WARN (feedback from Tomas).
For: VIZ-5115
CC: Tomas Elf <tomas.elf@intel.com>
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-06-18 12:10:09 +00:00
|
|
|
|
2016-04-28 08:56:47 +00:00
|
|
|
total_bytes = bytes + req->reserved_space;
|
drm/i915: Reserve ring buffer space for i915_add_request() commands
It is a bad idea for i915_add_request() to fail. The work will already have been
send to the ring and will be processed, but there will not be any tracking or
management of that work.
The only way the add request call can fail is if it can't write its epilogue
commands to the ring (cache flushing, seqno updates, interrupt signalling). The
reasons for that are mostly down to running out of ring buffer space and the
problems associated with trying to get some more. This patch prevents that
situation from happening in the first place.
When a request is created, it marks sufficient space as reserved for the
epilogue commands. Thus guaranteeing that by the time the epilogue is written,
there will be plenty of space for it. Note that a ring_begin() call is required
to actually reserve the space (and do any potential waiting). However, that is
not currently done at request creation time. This is because the ring_begin()
code can allocate a request. Hence calling begin() from the request allocation
code would lead to infinite recursion! Later patches in this series remove the
need for begin() to do the allocate. At that point, it becomes safe for the
allocate to call begin() and really reserve the space.
Until then, there is a potential for insufficient space to be available at the
point of calling i915_add_request(). However, that would only be in the case
where the request was created and immediately submitted without ever calling
ring_begin() and adding any work to that request. Which should never happen. And
even if it does, and if that request happens to fall down the tiny window of
opportunity for failing due to being out of ring space then does it really
matter because the request wasn't doing anything in the first place?
v2: Updated the 'reserved space too small' warning to include the offending
sizes. Added a 'cancel' operation to clean up when a request is abandoned. Added
re-initialisation of tracking state after a buffer wrap to keep the sanity
checks accurate.
v3: Incremented the reserved size to accommodate Ironlake (after finally
managing to run on an ILK system). Also fixed missing wrap code in LRC mode.
v4: Added extra comment and removed duplicate WARN (feedback from Tomas).
For: VIZ-5115
CC: Tomas Elf <tomas.elf@intel.com>
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-06-18 12:10:09 +00:00
|
|
|
|
2015-06-30 11:40:55 +00:00
|
|
|
if (unlikely(bytes > remain_usable)) {
|
|
|
|
/*
|
|
|
|
* Not enough space for the basic request. So need to flush
|
|
|
|
* out the remainder and then wait for base + reserved.
|
|
|
|
*/
|
|
|
|
wait_bytes = remain_actual + total_bytes;
|
|
|
|
need_wrap = true;
|
2016-04-28 08:56:46 +00:00
|
|
|
} else if (unlikely(total_bytes > remain_usable)) {
|
|
|
|
/*
|
|
|
|
* The base request will fit but the reserved space
|
|
|
|
* falls off the end. So we don't need an immediate wrap
|
|
|
|
* and only need to effectively wait for the reserved
|
|
|
|
* size space from the start of ringbuffer.
|
|
|
|
*/
|
2016-04-28 08:56:47 +00:00
|
|
|
wait_bytes = remain_actual + req->reserved_space;
|
2015-06-30 11:40:55 +00:00
|
|
|
} else {
|
2016-04-28 08:56:46 +00:00
|
|
|
/* No wrapping required, just waiting. */
|
|
|
|
wait_bytes = total_bytes;
|
2012-12-04 13:12:03 +00:00
|
|
|
}
|
|
|
|
|
2016-08-02 21:50:19 +00:00
|
|
|
if (wait_bytes > ring->space) {
|
2016-04-28 08:56:46 +00:00
|
|
|
int ret = wait_for_space(req, wait_bytes);
|
2012-12-04 13:12:03 +00:00
|
|
|
if (unlikely(ret))
|
2017-02-14 11:32:42 +00:00
|
|
|
return ERR_PTR(ret);
|
2012-12-04 13:12:03 +00:00
|
|
|
}
|
|
|
|
|
2016-04-28 08:56:46 +00:00
|
|
|
if (unlikely(need_wrap)) {
|
2016-08-02 21:50:19 +00:00
|
|
|
GEM_BUG_ON(remain_actual > ring->space);
|
2017-04-25 13:00:49 +00:00
|
|
|
GEM_BUG_ON(ring->emit + remain_actual > ring->size);
|
2010-10-27 11:18:21 +00:00
|
|
|
|
2016-04-28 08:56:46 +00:00
|
|
|
/* Fill the tail with MI_NOOP */
|
2017-04-25 13:00:49 +00:00
|
|
|
memset(ring->vaddr + ring->emit, 0, remain_actual);
|
|
|
|
ring->emit = 0;
|
2016-08-02 21:50:19 +00:00
|
|
|
ring->space -= remain_actual;
|
2016-04-28 08:56:46 +00:00
|
|
|
}
|
2014-01-02 14:32:35 +00:00
|
|
|
|
2017-04-25 13:00:49 +00:00
|
|
|
GEM_BUG_ON(ring->emit > ring->size - bytes);
|
2017-05-04 13:08:44 +00:00
|
|
|
GEM_BUG_ON(ring->space < bytes);
|
2017-04-25 13:00:49 +00:00
|
|
|
cs = ring->vaddr + ring->emit;
|
2017-04-23 17:06:17 +00:00
|
|
|
GEM_DEBUG_EXEC(memset(cs, POISON_INUSE, bytes));
|
2017-04-25 13:00:49 +00:00
|
|
|
ring->emit += bytes;
|
2016-08-02 21:50:19 +00:00
|
|
|
ring->space -= bytes;
|
2017-02-14 11:32:42 +00:00
|
|
|
|
|
|
|
return cs;
|
2010-05-21 01:08:55 +00:00
|
|
|
}
|
2010-10-27 11:18:21 +00:00
|
|
|
|
2014-02-11 17:52:05 +00:00
|
|
|
/* Align the ring tail to a cacheline boundary */
|
2015-05-29 16:44:06 +00:00
|
|
|
int intel_ring_cacheline_align(struct drm_i915_gem_request *req)
|
2014-02-11 17:52:05 +00:00
|
|
|
{
|
2016-08-02 21:50:18 +00:00
|
|
|
int num_dwords =
|
2017-04-25 13:00:49 +00:00
|
|
|
(req->ring->emit & (CACHELINE_BYTES - 1)) / sizeof(uint32_t);
|
2017-02-14 11:32:42 +00:00
|
|
|
u32 *cs;
|
2014-02-11 17:52:05 +00:00
|
|
|
|
|
|
|
if (num_dwords == 0)
|
|
|
|
return 0;
|
|
|
|
|
2014-04-09 08:19:40 +00:00
|
|
|
num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords;
|
2017-02-14 11:32:42 +00:00
|
|
|
cs = intel_ring_begin(req, num_dwords);
|
|
|
|
if (IS_ERR(cs))
|
|
|
|
return PTR_ERR(cs);
|
2014-02-11 17:52:05 +00:00
|
|
|
|
|
|
|
while (num_dwords--)
|
2017-02-14 11:32:42 +00:00
|
|
|
*cs++ = MI_NOOP;
|
2014-02-11 17:52:05 +00:00
|
|
|
|
2017-02-14 11:32:42 +00:00
|
|
|
intel_ring_advance(req, cs);
|
2014-02-11 17:52:05 +00:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2016-08-02 21:50:29 +00:00
|
|
|
static void gen6_bsd_submit_request(struct drm_i915_gem_request *request)
|
2010-09-19 13:40:43 +00:00
|
|
|
{
|
2016-08-02 21:50:29 +00:00
|
|
|
struct drm_i915_private *dev_priv = request->i915;
|
2010-09-19 13:40:43 +00:00
|
|
|
|
2016-06-30 14:33:45 +00:00
|
|
|
intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
|
|
|
|
|
2010-09-19 13:40:43 +00:00
|
|
|
/* Every tail move must follow the sequence below */
|
2012-07-05 16:14:01 +00:00
|
|
|
|
|
|
|
/* Disable notification that the ring is IDLE. The GT
|
|
|
|
* will then assume that it is busy and bring it out of rc6.
|
|
|
|
*/
|
2016-06-30 14:33:45 +00:00
|
|
|
I915_WRITE_FW(GEN6_BSD_SLEEP_PSMI_CONTROL,
|
|
|
|
_MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
|
2012-07-05 16:14:01 +00:00
|
|
|
|
|
|
|
/* Clear the context id. Here be magic! */
|
2016-06-30 14:33:45 +00:00
|
|
|
I915_WRITE64_FW(GEN6_BSD_RNCID, 0x0);
|
2011-08-16 19:34:10 +00:00
|
|
|
|
2012-07-05 16:14:01 +00:00
|
|
|
/* Wait for the ring not to be idle, i.e. for it to wake up. */
|
2017-04-11 10:13:37 +00:00
|
|
|
if (__intel_wait_for_register_fw(dev_priv,
|
|
|
|
GEN6_BSD_SLEEP_PSMI_CONTROL,
|
|
|
|
GEN6_BSD_SLEEP_INDICATOR,
|
|
|
|
0,
|
|
|
|
1000, 0, NULL))
|
2012-07-05 16:14:01 +00:00
|
|
|
DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
|
2011-08-16 19:34:10 +00:00
|
|
|
|
2012-07-05 16:14:01 +00:00
|
|
|
/* Now that the ring is fully powered up, update the tail */
|
2016-08-02 21:50:34 +00:00
|
|
|
i9xx_submit_request(request);
|
2012-07-05 16:14:01 +00:00
|
|
|
|
|
|
|
/* Let the ring send IDLE messages to the GT again,
|
|
|
|
* and so let it sleep to conserve power when idle.
|
|
|
|
*/
|
2016-06-30 14:33:45 +00:00
|
|
|
I915_WRITE_FW(GEN6_BSD_SLEEP_PSMI_CONTROL,
|
|
|
|
_MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
|
|
|
|
|
|
|
|
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
|
2010-09-19 13:40:43 +00:00
|
|
|
}
|
|
|
|
|
2016-08-02 21:50:25 +00:00
|
|
|
static int gen6_bsd_ring_flush(struct drm_i915_gem_request *req, u32 mode)
|
2010-09-19 13:40:43 +00:00
|
|
|
{
|
2017-02-14 11:32:42 +00:00
|
|
|
u32 cmd, *cs;
|
2011-01-04 17:34:02 +00:00
|
|
|
|
2017-02-14 11:32:42 +00:00
|
|
|
cs = intel_ring_begin(req, 4);
|
|
|
|
if (IS_ERR(cs))
|
|
|
|
return PTR_ERR(cs);
|
2011-01-04 17:34:02 +00:00
|
|
|
|
2011-02-02 12:13:49 +00:00
|
|
|
cmd = MI_FLUSH_DW;
|
2016-05-06 14:40:21 +00:00
|
|
|
if (INTEL_GEN(req->i915) >= 8)
|
2013-11-03 04:07:13 +00:00
|
|
|
cmd += 1;
|
2015-01-22 13:42:00 +00:00
|
|
|
|
|
|
|
/* We always require a command barrier so that subsequent
|
|
|
|
* commands, such as breadcrumb interrupts, are strictly ordered
|
|
|
|
* wrt the contents of the write cache being flushed to memory
|
|
|
|
* (and thus being coherent from the CPU).
|
|
|
|
*/
|
|
|
|
cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
|
|
|
|
|
2012-10-26 16:42:42 +00:00
|
|
|
/*
|
|
|
|
* Bspec vol 1c.5 - video engine command streamer:
|
|
|
|
* "If ENABLED, all TLBs will be invalidated once the flush
|
|
|
|
* operation is complete. This bit is only valid when the
|
|
|
|
* Post-Sync Operation field is a value of 1h or 3h."
|
|
|
|
*/
|
2016-08-02 21:50:25 +00:00
|
|
|
if (mode & EMIT_INVALIDATE)
|
2015-01-22 13:42:00 +00:00
|
|
|
cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
|
|
|
|
|
2017-02-14 11:32:42 +00:00
|
|
|
*cs++ = cmd;
|
|
|
|
*cs++ = I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT;
|
2016-05-06 14:40:21 +00:00
|
|
|
if (INTEL_GEN(req->i915) >= 8) {
|
2017-02-14 11:32:42 +00:00
|
|
|
*cs++ = 0; /* upper addr */
|
|
|
|
*cs++ = 0; /* value */
|
2013-11-03 04:07:13 +00:00
|
|
|
} else {
|
2017-02-14 11:32:42 +00:00
|
|
|
*cs++ = 0;
|
|
|
|
*cs++ = MI_NOOP;
|
2013-11-03 04:07:13 +00:00
|
|
|
}
|
2017-02-14 11:32:42 +00:00
|
|
|
intel_ring_advance(req, cs);
|
2011-01-04 17:34:02 +00:00
|
|
|
return 0;
|
2010-09-19 13:40:43 +00:00
|
|
|
}
|
|
|
|
|
2013-11-03 04:07:12 +00:00
|
|
|
static int
|
2016-08-02 21:50:27 +00:00
|
|
|
gen8_emit_bb_start(struct drm_i915_gem_request *req,
|
|
|
|
u64 offset, u32 len,
|
|
|
|
unsigned int dispatch_flags)
|
2013-11-03 04:07:12 +00:00
|
|
|
{
|
2016-08-02 21:50:18 +00:00
|
|
|
bool ppgtt = USES_PPGTT(req->i915) &&
|
2015-02-13 11:48:10 +00:00
|
|
|
!(dispatch_flags & I915_DISPATCH_SECURE);
|
2017-02-14 11:32:42 +00:00
|
|
|
u32 *cs;
|
2013-11-03 04:07:12 +00:00
|
|
|
|
2017-02-14 11:32:42 +00:00
|
|
|
cs = intel_ring_begin(req, 4);
|
|
|
|
if (IS_ERR(cs))
|
|
|
|
return PTR_ERR(cs);
|
2013-11-03 04:07:12 +00:00
|
|
|
|
|
|
|
/* FIXME(BDW): Address space and security selectors. */
|
2017-02-14 11:32:42 +00:00
|
|
|
*cs++ = MI_BATCH_BUFFER_START_GEN8 | (ppgtt << 8) | (dispatch_flags &
|
|
|
|
I915_DISPATCH_RS ? MI_BATCH_RESOURCE_STREAMER : 0);
|
|
|
|
*cs++ = lower_32_bits(offset);
|
|
|
|
*cs++ = upper_32_bits(offset);
|
|
|
|
*cs++ = MI_NOOP;
|
|
|
|
intel_ring_advance(req, cs);
|
2013-11-03 04:07:12 +00:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2012-10-17 11:09:54 +00:00
|
|
|
static int
|
2016-08-02 21:50:27 +00:00
|
|
|
hsw_emit_bb_start(struct drm_i915_gem_request *req,
|
|
|
|
u64 offset, u32 len,
|
|
|
|
unsigned int dispatch_flags)
|
2012-10-17 11:09:54 +00:00
|
|
|
{
|
2017-02-14 11:32:42 +00:00
|
|
|
u32 *cs;
|
2012-10-17 11:09:54 +00:00
|
|
|
|
2017-02-14 11:32:42 +00:00
|
|
|
cs = intel_ring_begin(req, 2);
|
|
|
|
if (IS_ERR(cs))
|
|
|
|
return PTR_ERR(cs);
|
2012-10-17 11:09:54 +00:00
|
|
|
|
2017-02-14 11:32:42 +00:00
|
|
|
*cs++ = MI_BATCH_BUFFER_START | (dispatch_flags & I915_DISPATCH_SECURE ?
|
|
|
|
0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW) |
|
|
|
|
(dispatch_flags & I915_DISPATCH_RS ?
|
|
|
|
MI_BATCH_RESOURCE_STREAMER : 0);
|
2012-10-17 11:09:54 +00:00
|
|
|
/* bit0-7 is the length on GEN6+ */
|
2017-02-14 11:32:42 +00:00
|
|
|
*cs++ = offset;
|
|
|
|
intel_ring_advance(req, cs);
|
2012-10-17 11:09:54 +00:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2010-09-19 13:40:43 +00:00
|
|
|
static int
|
2016-08-02 21:50:27 +00:00
|
|
|
gen6_emit_bb_start(struct drm_i915_gem_request *req,
|
|
|
|
u64 offset, u32 len,
|
|
|
|
unsigned int dispatch_flags)
|
2010-09-19 13:40:43 +00:00
|
|
|
{
|
2017-02-14 11:32:42 +00:00
|
|
|
u32 *cs;
|
2010-09-19 16:53:44 +00:00
|
|
|
|
2017-02-14 11:32:42 +00:00
|
|
|
cs = intel_ring_begin(req, 2);
|
|
|
|
if (IS_ERR(cs))
|
|
|
|
return PTR_ERR(cs);
|
2010-10-27 11:45:26 +00:00
|
|
|
|
2017-02-14 11:32:42 +00:00
|
|
|
*cs++ = MI_BATCH_BUFFER_START | (dispatch_flags & I915_DISPATCH_SECURE ?
|
|
|
|
0 : MI_BATCH_NON_SECURE_I965);
|
2011-08-16 19:34:10 +00:00
|
|
|
/* bit0-7 is the length on GEN6+ */
|
2017-02-14 11:32:42 +00:00
|
|
|
*cs++ = offset;
|
|
|
|
intel_ring_advance(req, cs);
|
2010-09-19 16:53:44 +00:00
|
|
|
|
2011-08-16 19:34:10 +00:00
|
|
|
return 0;
|
2010-09-19 13:40:43 +00:00
|
|
|
}
|
|
|
|
|
2010-10-19 10:19:32 +00:00
|
|
|
/* Blitter support (SandyBridge+) */
|
|
|
|
|
2016-08-02 21:50:25 +00:00
|
|
|
static int gen6_ring_flush(struct drm_i915_gem_request *req, u32 mode)
|
2010-11-02 08:31:01 +00:00
|
|
|
{
|
2017-02-14 11:32:42 +00:00
|
|
|
u32 cmd, *cs;
|
2011-01-04 17:34:02 +00:00
|
|
|
|
2017-02-14 11:32:42 +00:00
|
|
|
cs = intel_ring_begin(req, 4);
|
|
|
|
if (IS_ERR(cs))
|
|
|
|
return PTR_ERR(cs);
|
2011-01-04 17:34:02 +00:00
|
|
|
|
2011-02-02 12:13:49 +00:00
|
|
|
cmd = MI_FLUSH_DW;
|
2016-05-06 14:40:21 +00:00
|
|
|
if (INTEL_GEN(req->i915) >= 8)
|
2013-11-03 04:07:13 +00:00
|
|
|
cmd += 1;
|
2015-01-22 13:42:00 +00:00
|
|
|
|
|
|
|
/* We always require a command barrier so that subsequent
|
|
|
|
* commands, such as breadcrumb interrupts, are strictly ordered
|
|
|
|
* wrt the contents of the write cache being flushed to memory
|
|
|
|
* (and thus being coherent from the CPU).
|
|
|
|
*/
|
|
|
|
cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
|
|
|
|
|
2012-10-26 16:42:42 +00:00
|
|
|
/*
|
|
|
|
* Bspec vol 1c.3 - blitter engine command streamer:
|
|
|
|
* "If ENABLED, all TLBs will be invalidated once the flush
|
|
|
|
* operation is complete. This bit is only valid when the
|
|
|
|
* Post-Sync Operation field is a value of 1h or 3h."
|
|
|
|
*/
|
2016-08-02 21:50:25 +00:00
|
|
|
if (mode & EMIT_INVALIDATE)
|
2015-01-22 13:42:00 +00:00
|
|
|
cmd |= MI_INVALIDATE_TLB;
|
2017-02-14 11:32:42 +00:00
|
|
|
*cs++ = cmd;
|
|
|
|
*cs++ = I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT;
|
2016-05-06 14:40:21 +00:00
|
|
|
if (INTEL_GEN(req->i915) >= 8) {
|
2017-02-14 11:32:42 +00:00
|
|
|
*cs++ = 0; /* upper addr */
|
|
|
|
*cs++ = 0; /* value */
|
2013-11-03 04:07:13 +00:00
|
|
|
} else {
|
2017-02-14 11:32:42 +00:00
|
|
|
*cs++ = 0;
|
|
|
|
*cs++ = MI_NOOP;
|
2013-11-03 04:07:13 +00:00
|
|
|
}
|
2017-02-14 11:32:42 +00:00
|
|
|
intel_ring_advance(req, cs);
|
2013-06-06 19:58:16 +00:00
|
|
|
|
2011-01-04 17:34:02 +00:00
|
|
|
return 0;
|
2010-11-02 08:31:01 +00:00
|
|
|
}
|
|
|
|
|
2016-06-29 15:09:27 +00:00
|
|
|
static void intel_ring_init_semaphores(struct drm_i915_private *dev_priv,
|
|
|
|
struct intel_engine_cs *engine)
|
|
|
|
{
|
2016-06-29 15:09:28 +00:00
|
|
|
struct drm_i915_gem_object *obj;
|
2016-06-29 15:09:29 +00:00
|
|
|
int ret, i;
|
2016-06-29 15:09:28 +00:00
|
|
|
|
2016-07-20 12:31:57 +00:00
|
|
|
if (!i915.semaphores)
|
2016-06-29 15:09:28 +00:00
|
|
|
return;
|
|
|
|
|
2016-08-15 09:49:02 +00:00
|
|
|
if (INTEL_GEN(dev_priv) >= 8 && !dev_priv->semaphore) {
|
|
|
|
struct i915_vma *vma;
|
|
|
|
|
2017-01-10 14:47:34 +00:00
|
|
|
obj = i915_gem_object_create(dev_priv, PAGE_SIZE);
|
2016-08-15 09:49:02 +00:00
|
|
|
if (IS_ERR(obj))
|
|
|
|
goto err;
|
2016-06-29 15:09:28 +00:00
|
|
|
|
2017-01-16 15:21:30 +00:00
|
|
|
vma = i915_vma_instance(obj, &dev_priv->ggtt.base, NULL);
|
2016-08-15 09:49:02 +00:00
|
|
|
if (IS_ERR(vma))
|
|
|
|
goto err_obj;
|
|
|
|
|
|
|
|
ret = i915_gem_object_set_to_gtt_domain(obj, false);
|
|
|
|
if (ret)
|
|
|
|
goto err_obj;
|
|
|
|
|
|
|
|
ret = i915_vma_pin(vma, 0, 0, PIN_GLOBAL | PIN_HIGH);
|
|
|
|
if (ret)
|
|
|
|
goto err_obj;
|
|
|
|
|
|
|
|
dev_priv->semaphore = vma;
|
|
|
|
}
|
2016-06-29 15:09:27 +00:00
|
|
|
|
|
|
|
if (INTEL_GEN(dev_priv) >= 8) {
|
2016-08-15 09:49:07 +00:00
|
|
|
u32 offset = i915_ggtt_offset(dev_priv->semaphore);
|
2016-06-29 15:09:29 +00:00
|
|
|
|
2016-08-02 21:50:40 +00:00
|
|
|
engine->semaphore.sync_to = gen8_ring_sync_to;
|
2016-06-29 15:09:27 +00:00
|
|
|
engine->semaphore.signal = gen8_xcs_signal;
|
2016-06-29 15:09:29 +00:00
|
|
|
|
|
|
|
for (i = 0; i < I915_NUM_ENGINES; i++) {
|
2016-08-15 09:49:07 +00:00
|
|
|
u32 ring_offset;
|
2016-06-29 15:09:29 +00:00
|
|
|
|
|
|
|
if (i != engine->id)
|
|
|
|
ring_offset = offset + GEN8_SEMAPHORE_OFFSET(engine->id, i);
|
|
|
|
else
|
|
|
|
ring_offset = MI_SEMAPHORE_SYNC_INVALID;
|
|
|
|
|
|
|
|
engine->semaphore.signal_ggtt[i] = ring_offset;
|
|
|
|
}
|
2016-06-29 15:09:27 +00:00
|
|
|
} else if (INTEL_GEN(dev_priv) >= 6) {
|
2016-08-02 21:50:40 +00:00
|
|
|
engine->semaphore.sync_to = gen6_ring_sync_to;
|
2016-06-29 15:09:27 +00:00
|
|
|
engine->semaphore.signal = gen6_signal;
|
2016-06-29 15:09:31 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* The current semaphore is only applied on pre-gen8
|
|
|
|
* platform. And there is no VCS2 ring on the pre-gen8
|
|
|
|
* platform. So the semaphore between RCS and VCS2 is
|
|
|
|
* initialized as INVALID. Gen8 will initialize the
|
|
|
|
* sema between VCS2 and RCS later.
|
|
|
|
*/
|
2016-08-16 16:04:21 +00:00
|
|
|
for (i = 0; i < GEN6_NUM_SEMAPHORES; i++) {
|
2016-06-29 15:09:31 +00:00
|
|
|
static const struct {
|
|
|
|
u32 wait_mbox;
|
|
|
|
i915_reg_t mbox_reg;
|
2016-08-16 16:04:21 +00:00
|
|
|
} sem_data[GEN6_NUM_SEMAPHORES][GEN6_NUM_SEMAPHORES] = {
|
|
|
|
[RCS_HW] = {
|
|
|
|
[VCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_RV, .mbox_reg = GEN6_VRSYNC },
|
|
|
|
[BCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_RB, .mbox_reg = GEN6_BRSYNC },
|
|
|
|
[VECS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_RVE, .mbox_reg = GEN6_VERSYNC },
|
2016-06-29 15:09:31 +00:00
|
|
|
},
|
2016-08-16 16:04:21 +00:00
|
|
|
[VCS_HW] = {
|
|
|
|
[RCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VR, .mbox_reg = GEN6_RVSYNC },
|
|
|
|
[BCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VB, .mbox_reg = GEN6_BVSYNC },
|
|
|
|
[VECS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VVE, .mbox_reg = GEN6_VEVSYNC },
|
2016-06-29 15:09:31 +00:00
|
|
|
},
|
2016-08-16 16:04:21 +00:00
|
|
|
[BCS_HW] = {
|
|
|
|
[RCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_BR, .mbox_reg = GEN6_RBSYNC },
|
|
|
|
[VCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_BV, .mbox_reg = GEN6_VBSYNC },
|
|
|
|
[VECS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_BVE, .mbox_reg = GEN6_VEBSYNC },
|
2016-06-29 15:09:31 +00:00
|
|
|
},
|
2016-08-16 16:04:21 +00:00
|
|
|
[VECS_HW] = {
|
|
|
|
[RCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VER, .mbox_reg = GEN6_RVESYNC },
|
|
|
|
[VCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VEV, .mbox_reg = GEN6_VVESYNC },
|
|
|
|
[BCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VEB, .mbox_reg = GEN6_BVESYNC },
|
2016-06-29 15:09:31 +00:00
|
|
|
},
|
|
|
|
};
|
|
|
|
u32 wait_mbox;
|
|
|
|
i915_reg_t mbox_reg;
|
|
|
|
|
2016-08-16 16:04:21 +00:00
|
|
|
if (i == engine->hw_id) {
|
2016-06-29 15:09:31 +00:00
|
|
|
wait_mbox = MI_SEMAPHORE_SYNC_INVALID;
|
|
|
|
mbox_reg = GEN6_NOSYNC;
|
|
|
|
} else {
|
2016-08-16 16:04:21 +00:00
|
|
|
wait_mbox = sem_data[engine->hw_id][i].wait_mbox;
|
|
|
|
mbox_reg = sem_data[engine->hw_id][i].mbox_reg;
|
2016-06-29 15:09:31 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
engine->semaphore.mbox.wait[i] = wait_mbox;
|
|
|
|
engine->semaphore.mbox.signal[i] = mbox_reg;
|
|
|
|
}
|
2016-06-29 15:09:27 +00:00
|
|
|
}
|
2016-08-15 09:49:02 +00:00
|
|
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
err_obj:
|
|
|
|
i915_gem_object_put(obj);
|
|
|
|
err:
|
|
|
|
DRM_DEBUG_DRIVER("Failed to allocate space for semaphores, disabling\n");
|
|
|
|
i915.semaphores = 0;
|
2016-06-29 15:09:27 +00:00
|
|
|
}
|
|
|
|
|
2016-07-01 08:18:13 +00:00
|
|
|
static void intel_ring_init_irq(struct drm_i915_private *dev_priv,
|
|
|
|
struct intel_engine_cs *engine)
|
|
|
|
{
|
2016-07-13 15:03:38 +00:00
|
|
|
engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << engine->irq_shift;
|
|
|
|
|
2016-07-01 08:18:13 +00:00
|
|
|
if (INTEL_GEN(dev_priv) >= 8) {
|
2016-07-01 16:23:27 +00:00
|
|
|
engine->irq_enable = gen8_irq_enable;
|
|
|
|
engine->irq_disable = gen8_irq_disable;
|
2016-07-01 08:18:13 +00:00
|
|
|
engine->irq_seqno_barrier = gen6_seqno_barrier;
|
|
|
|
} else if (INTEL_GEN(dev_priv) >= 6) {
|
2016-07-01 16:23:27 +00:00
|
|
|
engine->irq_enable = gen6_irq_enable;
|
|
|
|
engine->irq_disable = gen6_irq_disable;
|
2016-07-01 08:18:13 +00:00
|
|
|
engine->irq_seqno_barrier = gen6_seqno_barrier;
|
|
|
|
} else if (INTEL_GEN(dev_priv) >= 5) {
|
2016-07-01 16:23:27 +00:00
|
|
|
engine->irq_enable = gen5_irq_enable;
|
|
|
|
engine->irq_disable = gen5_irq_disable;
|
2016-07-01 16:23:21 +00:00
|
|
|
engine->irq_seqno_barrier = gen5_seqno_barrier;
|
2016-07-01 08:18:13 +00:00
|
|
|
} else if (INTEL_GEN(dev_priv) >= 3) {
|
2016-07-01 16:23:27 +00:00
|
|
|
engine->irq_enable = i9xx_irq_enable;
|
|
|
|
engine->irq_disable = i9xx_irq_disable;
|
2016-07-01 08:18:13 +00:00
|
|
|
} else {
|
2016-07-01 16:23:27 +00:00
|
|
|
engine->irq_enable = i8xx_irq_enable;
|
|
|
|
engine->irq_disable = i8xx_irq_disable;
|
2016-07-01 08:18:13 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2017-03-16 17:13:03 +00:00
|
|
|
static void i9xx_set_default_submission(struct intel_engine_cs *engine)
|
|
|
|
{
|
|
|
|
engine->submit_request = i9xx_submit_request;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void gen6_bsd_set_default_submission(struct intel_engine_cs *engine)
|
|
|
|
{
|
|
|
|
engine->submit_request = gen6_bsd_submit_request;
|
|
|
|
}
|
|
|
|
|
2016-06-29 15:09:20 +00:00
|
|
|
static void intel_ring_default_vfuncs(struct drm_i915_private *dev_priv,
|
|
|
|
struct intel_engine_cs *engine)
|
|
|
|
{
|
2016-08-02 21:50:35 +00:00
|
|
|
intel_ring_init_irq(dev_priv, engine);
|
|
|
|
intel_ring_init_semaphores(dev_priv, engine);
|
|
|
|
|
2016-06-29 15:09:25 +00:00
|
|
|
engine->init_hw = init_ring_common;
|
2016-09-09 13:11:53 +00:00
|
|
|
engine->reset_hw = reset_ring_common;
|
2016-06-29 15:09:21 +00:00
|
|
|
|
drm/i915: Unify active context tracking between legacy/execlists/guc
The requests conversion introduced a nasty bug where we could generate a
new request in the middle of constructing a request if we needed to idle
the system in order to evict space for a context. The request to idle
would be executed (and waited upon) before the current one, creating a
minor havoc in the seqno accounting, as we will consider the current
request to already be completed (prior to deferred seqno assignment) but
ring->last_retired_head would have been updated and still could allow
us to overwrite the current request before execution.
We also employed two different mechanisms to track the active context
until it was switched out. The legacy method allowed for waiting upon an
active context (it could forcibly evict any vma, including context's),
but the execlists method took a step backwards by pinning the vma for
the entire active lifespan of the context (the only way to evict was to
idle the entire GPU, not individual contexts). However, to circumvent
the tricky issue of locking (i.e. we cannot take struct_mutex at the
time of i915_gem_request_submit(), where we would want to move the
previous context onto the active tracker and unpin it), we take the
execlists approach and keep the contexts pinned until retirement.
The benefit of the execlists approach, more important for execlists than
legacy, was the reduction in work in pinning the context for each
request - as the context was kept pinned until idle, it could short
circuit the pinning for all active contexts.
We introduce new engine vfuncs to pin and unpin the context
respectively. The context is pinned at the start of the request, and
only unpinned when the following request is retired (this ensures that
the context is idle and coherent in main memory before we unpin it). We
move the engine->last_context tracking into the retirement itself
(rather than during request submission) in order to allow the submission
to be reordered or unwound without undue difficultly.
And finally an ulterior motive for unifying context handling was to
prepare for mock requests.
v2: Rename to last_retired_context, split out legacy_context tracking
for MI_SET_CONTEXT.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20161218153724.8439-3-chris@chris-wilson.co.uk
2016-12-18 15:37:20 +00:00
|
|
|
engine->context_pin = intel_ring_context_pin;
|
|
|
|
engine->context_unpin = intel_ring_context_unpin;
|
|
|
|
|
2016-12-18 15:37:24 +00:00
|
|
|
engine->request_alloc = ring_request_alloc;
|
|
|
|
|
2016-10-28 12:58:50 +00:00
|
|
|
engine->emit_breadcrumb = i9xx_emit_breadcrumb;
|
2016-10-28 12:58:51 +00:00
|
|
|
engine->emit_breadcrumb_sz = i9xx_emit_breadcrumb_sz;
|
|
|
|
if (i915.semaphores) {
|
|
|
|
int num_rings;
|
|
|
|
|
2016-10-28 12:58:50 +00:00
|
|
|
engine->emit_breadcrumb = gen6_sema_emit_breadcrumb;
|
2016-10-28 12:58:51 +00:00
|
|
|
|
|
|
|
num_rings = hweight32(INTEL_INFO(dev_priv)->ring_mask) - 1;
|
|
|
|
if (INTEL_GEN(dev_priv) >= 8) {
|
|
|
|
engine->emit_breadcrumb_sz += num_rings * 6;
|
|
|
|
} else {
|
|
|
|
engine->emit_breadcrumb_sz += num_rings * 3;
|
|
|
|
if (num_rings & 1)
|
|
|
|
engine->emit_breadcrumb_sz++;
|
|
|
|
}
|
|
|
|
}
|
2017-03-16 17:13:03 +00:00
|
|
|
|
|
|
|
engine->set_default_submission = i9xx_set_default_submission;
|
2016-07-01 08:18:12 +00:00
|
|
|
|
|
|
|
if (INTEL_GEN(dev_priv) >= 8)
|
2016-08-02 21:50:27 +00:00
|
|
|
engine->emit_bb_start = gen8_emit_bb_start;
|
2016-07-01 08:18:12 +00:00
|
|
|
else if (INTEL_GEN(dev_priv) >= 6)
|
2016-08-02 21:50:27 +00:00
|
|
|
engine->emit_bb_start = gen6_emit_bb_start;
|
2016-07-01 08:18:12 +00:00
|
|
|
else if (INTEL_GEN(dev_priv) >= 4)
|
2016-08-02 21:50:27 +00:00
|
|
|
engine->emit_bb_start = i965_emit_bb_start;
|
2016-11-30 15:43:04 +00:00
|
|
|
else if (IS_I830(dev_priv) || IS_I845G(dev_priv))
|
2016-08-02 21:50:27 +00:00
|
|
|
engine->emit_bb_start = i830_emit_bb_start;
|
2016-07-01 08:18:12 +00:00
|
|
|
else
|
2016-08-02 21:50:27 +00:00
|
|
|
engine->emit_bb_start = i915_emit_bb_start;
|
2016-06-29 15:09:20 +00:00
|
|
|
}
|
|
|
|
|
2016-07-13 15:03:37 +00:00
|
|
|
int intel_init_render_ring_buffer(struct intel_engine_cs *engine)
|
2010-09-16 02:43:11 +00:00
|
|
|
{
|
2016-07-13 15:03:37 +00:00
|
|
|
struct drm_i915_private *dev_priv = engine->i915;
|
2014-06-30 16:53:37 +00:00
|
|
|
int ret;
|
2010-09-16 02:43:11 +00:00
|
|
|
|
2016-06-29 15:09:20 +00:00
|
|
|
intel_ring_default_vfuncs(dev_priv, engine);
|
|
|
|
|
2016-07-01 16:23:28 +00:00
|
|
|
if (HAS_L3_DPF(dev_priv))
|
|
|
|
engine->irq_keep_mask = GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
|
2016-07-01 16:23:21 +00:00
|
|
|
|
2016-05-06 14:40:21 +00:00
|
|
|
if (INTEL_GEN(dev_priv) >= 8) {
|
2016-03-16 11:00:36 +00:00
|
|
|
engine->init_context = intel_rcs_ctx_init;
|
2016-10-28 12:58:50 +00:00
|
|
|
engine->emit_breadcrumb = gen8_render_emit_breadcrumb;
|
2016-10-28 12:58:51 +00:00
|
|
|
engine->emit_breadcrumb_sz = gen8_render_emit_breadcrumb_sz;
|
2016-08-02 21:50:24 +00:00
|
|
|
engine->emit_flush = gen8_render_ring_flush;
|
2016-10-28 12:58:51 +00:00
|
|
|
if (i915.semaphores) {
|
|
|
|
int num_rings;
|
|
|
|
|
2016-03-16 11:00:36 +00:00
|
|
|
engine->semaphore.signal = gen8_rcs_signal;
|
2016-10-28 12:58:51 +00:00
|
|
|
|
|
|
|
num_rings =
|
|
|
|
hweight32(INTEL_INFO(dev_priv)->ring_mask) - 1;
|
2017-03-24 15:17:24 +00:00
|
|
|
engine->emit_breadcrumb_sz += num_rings * 8;
|
2016-10-28 12:58:51 +00:00
|
|
|
}
|
2016-05-06 14:40:21 +00:00
|
|
|
} else if (INTEL_GEN(dev_priv) >= 6) {
|
2016-03-16 11:00:36 +00:00
|
|
|
engine->init_context = intel_rcs_ctx_init;
|
2016-08-02 21:50:24 +00:00
|
|
|
engine->emit_flush = gen7_render_ring_flush;
|
2016-05-06 14:40:21 +00:00
|
|
|
if (IS_GEN6(dev_priv))
|
2016-08-02 21:50:24 +00:00
|
|
|
engine->emit_flush = gen6_render_ring_flush;
|
2016-05-06 14:40:21 +00:00
|
|
|
} else if (IS_GEN5(dev_priv)) {
|
2016-08-02 21:50:24 +00:00
|
|
|
engine->emit_flush = gen4_render_ring_flush;
|
2012-04-11 20:12:48 +00:00
|
|
|
} else {
|
2016-05-06 14:40:21 +00:00
|
|
|
if (INTEL_GEN(dev_priv) < 4)
|
2016-08-02 21:50:24 +00:00
|
|
|
engine->emit_flush = gen2_render_ring_flush;
|
2012-04-18 10:12:11 +00:00
|
|
|
else
|
2016-08-02 21:50:24 +00:00
|
|
|
engine->emit_flush = gen4_render_ring_flush;
|
2016-03-16 11:00:36 +00:00
|
|
|
engine->irq_enable_mask = I915_USER_INTERRUPT;
|
2010-12-04 11:30:53 +00:00
|
|
|
}
|
2014-06-30 16:53:36 +00:00
|
|
|
|
2016-05-06 14:40:21 +00:00
|
|
|
if (IS_HASWELL(dev_priv))
|
2016-08-02 21:50:27 +00:00
|
|
|
engine->emit_bb_start = hsw_emit_bb_start;
|
2016-07-01 08:18:12 +00:00
|
|
|
|
2016-03-16 11:00:36 +00:00
|
|
|
engine->init_hw = init_render_ring;
|
|
|
|
engine->cleanup = render_ring_cleanup;
|
2012-04-11 20:12:48 +00:00
|
|
|
|
2016-07-13 15:03:39 +00:00
|
|
|
ret = intel_init_ring_buffer(engine);
|
2014-11-19 23:33:06 +00:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2016-07-01 16:23:21 +00:00
|
|
|
if (INTEL_GEN(dev_priv) >= 6) {
|
2017-01-10 14:47:34 +00:00
|
|
|
ret = intel_engine_create_scratch(engine, PAGE_SIZE);
|
2016-07-01 16:23:20 +00:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
} else if (HAS_BROKEN_CS_TLB(dev_priv)) {
|
2016-08-15 09:48:58 +00:00
|
|
|
ret = intel_engine_create_scratch(engine, I830_WA_SIZE);
|
2014-11-19 23:33:06 +00:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
2010-09-16 02:43:11 +00:00
|
|
|
}
|
|
|
|
|
2016-07-13 15:03:37 +00:00
|
|
|
int intel_init_bsd_ring_buffer(struct intel_engine_cs *engine)
|
2010-09-16 02:43:11 +00:00
|
|
|
{
|
2016-07-13 15:03:37 +00:00
|
|
|
struct drm_i915_private *dev_priv = engine->i915;
|
2012-04-11 20:12:49 +00:00
|
|
|
|
2016-06-29 15:09:20 +00:00
|
|
|
intel_ring_default_vfuncs(dev_priv, engine);
|
|
|
|
|
2016-05-06 14:40:21 +00:00
|
|
|
if (INTEL_GEN(dev_priv) >= 6) {
|
2012-04-11 20:12:55 +00:00
|
|
|
/* gen6 bsd needs a special wa for tail updates */
|
2016-05-06 14:40:21 +00:00
|
|
|
if (IS_GEN6(dev_priv))
|
2017-03-16 17:13:03 +00:00
|
|
|
engine->set_default_submission = gen6_bsd_set_default_submission;
|
2016-08-02 21:50:24 +00:00
|
|
|
engine->emit_flush = gen6_bsd_ring_flush;
|
2016-07-13 15:03:38 +00:00
|
|
|
if (INTEL_GEN(dev_priv) < 8)
|
2016-03-16 11:00:36 +00:00
|
|
|
engine->irq_enable_mask = GT_BSD_USER_INTERRUPT;
|
2012-04-11 20:12:49 +00:00
|
|
|
} else {
|
2016-03-16 11:00:36 +00:00
|
|
|
engine->mmio_base = BSD_RING_BASE;
|
2016-08-02 21:50:24 +00:00
|
|
|
engine->emit_flush = bsd_ring_flush;
|
2016-06-29 15:09:32 +00:00
|
|
|
if (IS_GEN5(dev_priv))
|
2016-03-16 11:00:36 +00:00
|
|
|
engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
|
2016-06-29 15:09:32 +00:00
|
|
|
else
|
2016-03-16 11:00:36 +00:00
|
|
|
engine->irq_enable_mask = I915_BSD_USER_INTERRUPT;
|
2012-04-11 20:12:49 +00:00
|
|
|
}
|
|
|
|
|
2016-07-13 15:03:39 +00:00
|
|
|
return intel_init_ring_buffer(engine);
|
2010-09-16 02:43:11 +00:00
|
|
|
}
|
2010-10-19 10:19:32 +00:00
|
|
|
|
2016-07-13 15:03:37 +00:00
|
|
|
int intel_init_blt_ring_buffer(struct intel_engine_cs *engine)
|
2010-10-19 10:19:32 +00:00
|
|
|
{
|
2016-07-13 15:03:37 +00:00
|
|
|
struct drm_i915_private *dev_priv = engine->i915;
|
2016-06-29 15:09:20 +00:00
|
|
|
|
|
|
|
intel_ring_default_vfuncs(dev_priv, engine);
|
|
|
|
|
2016-08-02 21:50:24 +00:00
|
|
|
engine->emit_flush = gen6_ring_flush;
|
2016-07-13 15:03:38 +00:00
|
|
|
if (INTEL_GEN(dev_priv) < 8)
|
2016-03-16 11:00:36 +00:00
|
|
|
engine->irq_enable_mask = GT_BLT_USER_INTERRUPT;
|
2010-10-19 10:19:32 +00:00
|
|
|
|
2016-07-13 15:03:39 +00:00
|
|
|
return intel_init_ring_buffer(engine);
|
2010-10-19 10:19:32 +00:00
|
|
|
}
|
2012-07-20 11:41:08 +00:00
|
|
|
|
2016-07-13 15:03:37 +00:00
|
|
|
int intel_init_vebox_ring_buffer(struct intel_engine_cs *engine)
|
2013-05-29 02:22:23 +00:00
|
|
|
{
|
2016-07-13 15:03:37 +00:00
|
|
|
struct drm_i915_private *dev_priv = engine->i915;
|
2016-06-29 15:09:20 +00:00
|
|
|
|
|
|
|
intel_ring_default_vfuncs(dev_priv, engine);
|
|
|
|
|
2016-08-02 21:50:24 +00:00
|
|
|
engine->emit_flush = gen6_ring_flush;
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 04:07:09 +00:00
|
|
|
|
2016-07-13 15:03:38 +00:00
|
|
|
if (INTEL_GEN(dev_priv) < 8) {
|
2016-03-16 11:00:36 +00:00
|
|
|
engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
|
2016-07-01 16:23:27 +00:00
|
|
|
engine->irq_enable = hsw_vebox_irq_enable;
|
|
|
|
engine->irq_disable = hsw_vebox_irq_disable;
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 04:07:09 +00:00
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}
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2013-05-29 02:22:23 +00:00
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2016-07-13 15:03:39 +00:00
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return intel_init_ring_buffer(engine);
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2013-05-29 02:22:23 +00:00
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}
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