2016-04-05 14:10:52 +00:00
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/*
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* Copyright © 2015 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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*/
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#include "intel_drv.h"
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static void set_aux_backlight_enable(struct intel_dp *intel_dp, bool enable)
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{
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uint8_t reg_val = 0;
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2017-05-23 22:38:01 +00:00
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/* Early return when display use other mechanism to enable backlight. */
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if (!(intel_dp->edp_dpcd[1] & DP_EDP_BACKLIGHT_AUX_ENABLE_CAP))
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return;
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2016-04-05 14:10:52 +00:00
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if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_DISPLAY_CONTROL_REGISTER,
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®_val) < 0) {
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DRM_DEBUG_KMS("Failed to read DPCD register 0x%x\n",
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DP_EDP_DISPLAY_CONTROL_REGISTER);
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return;
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}
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if (enable)
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reg_val |= DP_EDP_BACKLIGHT_ENABLE;
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else
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reg_val &= ~(DP_EDP_BACKLIGHT_ENABLE);
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if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_DISPLAY_CONTROL_REGISTER,
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reg_val) != 1) {
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DRM_DEBUG_KMS("Failed to %s aux backlight\n",
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enable ? "enable" : "disable");
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}
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}
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/*
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* Read the current backlight value from DPCD register(s) based
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* on if 8-bit(MSB) or 16-bit(MSB and LSB) values are supported
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*/
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static uint32_t intel_dp_aux_get_backlight(struct intel_connector *connector)
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{
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struct intel_dp *intel_dp = enc_to_intel_dp(&connector->encoder->base);
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uint8_t read_val[2] = { 0x0 };
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uint16_t level = 0;
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if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB,
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&read_val, sizeof(read_val)) < 0) {
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DRM_DEBUG_KMS("Failed to read DPCD register 0x%x\n",
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DP_EDP_BACKLIGHT_BRIGHTNESS_MSB);
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return 0;
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}
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level = read_val[0];
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if (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT)
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level = (read_val[0] << 8 | read_val[1]);
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return level;
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}
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/*
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* Sends the current backlight level over the aux channel, checking if its using
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* 8-bit or 16 bit value (MSB and LSB)
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*/
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static void
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2017-06-12 10:21:15 +00:00
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intel_dp_aux_set_backlight(const struct drm_connector_state *conn_state, u32 level)
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2016-04-05 14:10:52 +00:00
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{
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2017-06-12 10:21:15 +00:00
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struct intel_connector *connector = to_intel_connector(conn_state->connector);
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2016-04-05 14:10:52 +00:00
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struct intel_dp *intel_dp = enc_to_intel_dp(&connector->encoder->base);
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uint8_t vals[2] = { 0x0 };
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vals[0] = level;
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/* Write the MSB and/or LSB */
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if (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT) {
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vals[0] = (level & 0xFF00) >> 8;
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vals[1] = (level & 0xFF);
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}
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if (drm_dp_dpcd_write(&intel_dp->aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB,
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vals, sizeof(vals)) < 0) {
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DRM_DEBUG_KMS("Failed to write aux backlight level\n");
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return;
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}
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}
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2017-06-22 19:03:37 +00:00
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/*
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* Set PWM Frequency divider to match desired frequency in vbt.
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* The PWM Frequency is calculated as 27Mhz / (F x P).
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* - Where F = PWM Frequency Pre-Divider value programmed by field 7:0 of the
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* EDP_BACKLIGHT_FREQ_SET register (DPCD Address 00728h)
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* - Where P = 2^Pn, where Pn is the value programmed by field 4:0 of the
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* EDP_PWMGEN_BIT_COUNT register (DPCD Address 00724h)
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*/
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static bool intel_dp_aux_set_pwm_freq(struct intel_connector *connector)
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{
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struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
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struct intel_dp *intel_dp = enc_to_intel_dp(&connector->encoder->base);
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int freq, fxp, fxp_min, fxp_max, fxp_actual, f = 1;
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u8 pn, pn_min, pn_max;
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/* Find desired value of (F x P)
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* Note that, if F x P is out of supported range, the maximum value or
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* minimum value will applied automatically. So no need to check that.
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*/
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freq = dev_priv->vbt.backlight.pwm_freq_hz;
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DRM_DEBUG_KMS("VBT defined backlight frequency %u Hz\n", freq);
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if (!freq) {
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DRM_DEBUG_KMS("Use panel default backlight frequency\n");
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return false;
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}
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fxp = DIV_ROUND_CLOSEST(KHz(DP_EDP_BACKLIGHT_FREQ_BASE_KHZ), freq);
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/* Use highest possible value of Pn for more granularity of brightness
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* adjustment while satifying the conditions below.
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* - Pn is in the range of Pn_min and Pn_max
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* - F is in the range of 1 and 255
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* - FxP is within 25% of desired value.
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* Note: 25% is arbitrary value and may need some tweak.
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*/
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if (drm_dp_dpcd_readb(&intel_dp->aux,
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DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN, &pn_min) != 1) {
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DRM_DEBUG_KMS("Failed to read pwmgen bit count cap min\n");
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return false;
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}
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if (drm_dp_dpcd_readb(&intel_dp->aux,
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DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX, &pn_max) != 1) {
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DRM_DEBUG_KMS("Failed to read pwmgen bit count cap max\n");
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return false;
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}
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pn_min &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
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pn_max &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
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fxp_min = DIV_ROUND_CLOSEST(fxp * 3, 4);
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fxp_max = DIV_ROUND_CLOSEST(fxp * 5, 4);
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if (fxp_min < (1 << pn_min) || (255 << pn_max) < fxp_max) {
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DRM_DEBUG_KMS("VBT defined backlight frequency out of range\n");
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return false;
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}
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for (pn = pn_max; pn >= pn_min; pn--) {
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f = clamp(DIV_ROUND_CLOSEST(fxp, 1 << pn), 1, 255);
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fxp_actual = f << pn;
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if (fxp_min <= fxp_actual && fxp_actual <= fxp_max)
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break;
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}
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if (drm_dp_dpcd_writeb(&intel_dp->aux,
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DP_EDP_PWMGEN_BIT_COUNT, pn) < 0) {
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DRM_DEBUG_KMS("Failed to write aux pwmgen bit count\n");
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return false;
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}
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if (drm_dp_dpcd_writeb(&intel_dp->aux,
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DP_EDP_BACKLIGHT_FREQ_SET, (u8) f) < 0) {
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DRM_DEBUG_KMS("Failed to write aux backlight freq\n");
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return false;
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}
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return true;
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}
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2017-06-12 10:21:15 +00:00
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static void intel_dp_aux_enable_backlight(const struct intel_crtc_state *crtc_state,
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const struct drm_connector_state *conn_state)
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2016-04-05 14:10:52 +00:00
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{
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2017-06-12 10:21:15 +00:00
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struct intel_connector *connector = to_intel_connector(conn_state->connector);
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2016-04-05 14:10:52 +00:00
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struct intel_dp *intel_dp = enc_to_intel_dp(&connector->encoder->base);
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2017-06-22 19:03:37 +00:00
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uint8_t dpcd_buf, new_dpcd_buf, edp_backlight_mode;
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2016-04-05 14:10:52 +00:00
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2017-05-11 23:02:18 +00:00
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if (drm_dp_dpcd_readb(&intel_dp->aux,
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DP_EDP_BACKLIGHT_MODE_SET_REGISTER, &dpcd_buf) != 1) {
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DRM_DEBUG_KMS("Failed to read DPCD register 0x%x\n",
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DP_EDP_BACKLIGHT_MODE_SET_REGISTER);
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return;
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}
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2017-06-22 19:03:37 +00:00
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new_dpcd_buf = dpcd_buf;
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2017-05-11 23:02:18 +00:00
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edp_backlight_mode = dpcd_buf & DP_EDP_BACKLIGHT_CONTROL_MODE_MASK;
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switch (edp_backlight_mode) {
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case DP_EDP_BACKLIGHT_CONTROL_MODE_PWM:
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case DP_EDP_BACKLIGHT_CONTROL_MODE_PRESET:
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case DP_EDP_BACKLIGHT_CONTROL_MODE_PRODUCT:
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2017-06-22 19:03:37 +00:00
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new_dpcd_buf &= ~DP_EDP_BACKLIGHT_CONTROL_MODE_MASK;
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new_dpcd_buf |= DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD;
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2017-05-11 23:02:18 +00:00
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break;
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/* Do nothing when it is already DPCD mode */
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case DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD:
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default:
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break;
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}
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2017-05-11 23:02:21 +00:00
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2017-06-22 19:03:37 +00:00
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if (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP)
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if (intel_dp_aux_set_pwm_freq(connector))
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new_dpcd_buf |= DP_EDP_BACKLIGHT_FREQ_AUX_SET_ENABLE;
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if (new_dpcd_buf != dpcd_buf) {
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if (drm_dp_dpcd_writeb(&intel_dp->aux,
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DP_EDP_BACKLIGHT_MODE_SET_REGISTER, new_dpcd_buf) < 0) {
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DRM_DEBUG_KMS("Failed to write aux backlight mode\n");
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}
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}
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2017-05-11 23:02:21 +00:00
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set_aux_backlight_enable(intel_dp, true);
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2017-06-12 10:21:15 +00:00
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intel_dp_aux_set_backlight(conn_state, connector->panel.backlight.level);
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2016-04-05 14:10:52 +00:00
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}
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2017-06-12 10:21:15 +00:00
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static void intel_dp_aux_disable_backlight(const struct drm_connector_state *old_conn_state)
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2016-04-05 14:10:52 +00:00
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{
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2017-06-12 10:21:15 +00:00
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set_aux_backlight_enable(enc_to_intel_dp(old_conn_state->best_encoder), false);
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2016-04-05 14:10:52 +00:00
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}
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static int intel_dp_aux_setup_backlight(struct intel_connector *connector,
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enum pipe pipe)
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{
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struct intel_dp *intel_dp = enc_to_intel_dp(&connector->encoder->base);
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struct intel_panel *panel = &connector->panel;
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if (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT)
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panel->backlight.max = 0xFFFF;
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else
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panel->backlight.max = 0xFF;
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panel->backlight.min = 0;
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panel->backlight.level = intel_dp_aux_get_backlight(connector);
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panel->backlight.enabled = panel->backlight.level != 0;
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return 0;
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}
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static bool
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intel_dp_aux_display_control_capable(struct intel_connector *connector)
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{
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struct intel_dp *intel_dp = enc_to_intel_dp(&connector->encoder->base);
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2017-06-12 10:21:15 +00:00
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/* Check the eDP Display control capabilities registers to determine if
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2016-04-05 14:10:52 +00:00
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* the panel can support backlight control over the aux channel
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*/
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2017-07-20 09:25:17 +00:00
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if (intel_dp->edp_dpcd[1] & DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP &&
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(intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP) &&
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!(intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_PWM_PIN_CAP)) {
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2016-04-05 14:10:52 +00:00
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DRM_DEBUG_KMS("AUX Backlight Control Supported!\n");
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return true;
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}
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return false;
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}
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int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector)
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{
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struct intel_panel *panel = &intel_connector->panel;
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2017-09-19 19:38:44 +00:00
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if (!i915_modparams.enable_dpcd_backlight)
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2016-04-05 14:10:52 +00:00
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return -ENODEV;
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if (!intel_dp_aux_display_control_capable(intel_connector))
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return -ENODEV;
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panel->backlight.setup = intel_dp_aux_setup_backlight;
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panel->backlight.enable = intel_dp_aux_enable_backlight;
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panel->backlight.disable = intel_dp_aux_disable_backlight;
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panel->backlight.set = intel_dp_aux_set_backlight;
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panel->backlight.get = intel_dp_aux_get_backlight;
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return 0;
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}
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