2011-11-10 21:45:17 +00:00
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/*
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* Header for code common to all OMAP2+ machines.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#ifndef __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H
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#define __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H
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2010-06-16 16:49:48 +00:00
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#ifndef __ASSEMBLER__
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2011-11-10 21:45:17 +00:00
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2012-08-28 00:43:01 +00:00
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#include <linux/irq.h>
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2011-11-10 21:45:17 +00:00
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#include <linux/delay.h>
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2012-10-08 16:11:22 +00:00
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#include <linux/i2c.h>
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2012-04-25 11:57:46 +00:00
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#include <linux/i2c/twl.h>
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2012-10-08 16:11:22 +00:00
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#include <linux/i2c-omap.h>
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2012-08-31 17:59:07 +00:00
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2010-06-16 16:49:48 +00:00
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#include <asm/proc-fns.h>
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2011-11-10 21:45:17 +00:00
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2012-10-08 16:11:22 +00:00
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#include "i2c.h"
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2012-10-15 19:50:46 +00:00
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#include "serial.h"
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2012-10-08 16:11:22 +00:00
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2012-10-24 21:26:18 +00:00
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#include "usb.h"
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2012-08-31 17:59:07 +00:00
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2012-08-28 00:43:01 +00:00
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#define OMAP_INTC_START NR_IRQS
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2012-08-28 00:43:01 +00:00
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2012-04-26 08:06:50 +00:00
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#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP2)
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int omap2_pm_init(void);
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#else
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static inline int omap2_pm_init(void)
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{
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return 0;
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}
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#endif
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#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
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int omap3_pm_init(void);
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#else
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static inline int omap3_pm_init(void)
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{
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return 0;
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}
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#endif
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#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP4)
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int omap4_pm_init(void);
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#else
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static inline int omap4_pm_init(void)
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{
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return 0;
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}
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#endif
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#ifdef CONFIG_OMAP_MUX
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int omap_mux_late_init(void);
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#else
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static inline int omap_mux_late_init(void)
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{
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return 0;
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}
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#endif
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2011-11-10 21:45:17 +00:00
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extern void omap2_init_common_infrastructure(void);
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2012-11-08 19:40:59 +00:00
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extern void omap2_sync32k_timer_init(void);
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extern void omap3_sync32k_timer_init(void);
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extern void omap3_secure_sync32k_timer_init(void);
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extern void omap3_gp_gptimer_timer_init(void);
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extern void omap3_am33xx_gptimer_timer_init(void);
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extern void omap4_local_timer_init(void);
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extern void omap5_realtime_timer_init(void);
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2011-11-10 21:45:17 +00:00
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void omap2420_init_early(void);
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void omap2430_init_early(void);
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void omap3430_init_early(void);
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void omap35xx_init_early(void);
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void omap3630_init_early(void);
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void omap3_init_early(void); /* Do not use this one */
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2012-06-18 06:47:26 +00:00
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void am33xx_init_early(void);
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2011-11-10 21:45:17 +00:00
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void am35xx_init_early(void);
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2011-12-13 18:46:44 +00:00
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void ti81xx_init_early(void);
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2012-05-10 19:08:49 +00:00
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void am33xx_init_early(void);
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2011-11-10 21:45:17 +00:00
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void omap4430_init_early(void);
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2012-06-05 10:51:32 +00:00
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void omap5_init_early(void);
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2012-04-26 08:06:50 +00:00
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void omap3_init_late(void); /* Do not use this one */
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void omap4430_init_late(void);
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void omap2420_init_late(void);
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void omap2430_init_late(void);
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void omap3430_init_late(void);
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void omap35xx_init_late(void);
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void omap3630_init_late(void);
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void am35xx_init_late(void);
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void ti81xx_init_late(void);
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int omap2_common_pm_late_init(void);
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2011-11-10 21:45:17 +00:00
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2012-10-30 02:56:07 +00:00
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#if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430)
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void omap2xxx_restart(char mode, const char *cmd);
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2012-07-05 15:05:15 +00:00
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#else
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2012-10-30 02:56:07 +00:00
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static inline void omap2xxx_restart(char mode, const char *cmd)
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{
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}
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2012-07-05 15:05:15 +00:00
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#endif
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2012-10-30 02:56:07 +00:00
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2013-01-23 21:02:40 +00:00
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#ifdef CONFIG_SOC_AM33XX
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void am33xx_restart(char mode, const char *cmd);
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#else
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static inline void am33xx_restart(char mode, const char *cmd)
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{
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}
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#endif
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2012-10-30 02:56:07 +00:00
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#ifdef CONFIG_ARCH_OMAP3
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void omap3xxx_restart(char mode, const char *cmd);
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#else
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static inline void omap3xxx_restart(char mode, const char *cmd)
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{
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}
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#endif
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#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5)
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void omap44xx_restart(char mode, const char *cmd);
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#else
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static inline void omap44xx_restart(char mode, const char *cmd)
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{
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}
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#endif
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2012-10-30 02:50:21 +00:00
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/* This gets called from mach-omap2/io.c, do not call this */
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void __init omap2_set_globals_tap(u32 class, void __iomem *tap);
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void __init omap242x_map_io(void);
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void __init omap243x_map_io(void);
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void __init omap3_map_io(void);
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void __init am33xx_map_io(void);
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void __init omap4_map_io(void);
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void __init omap5_map_io(void);
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void __init ti81xx_map_io(void);
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/* omap_barriers_init() is OMAP4 only */
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2012-02-02 14:03:55 +00:00
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void omap_barriers_init(void);
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2011-11-10 21:45:17 +00:00
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/**
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* omap_test_timeout - busy-loop, testing a condition
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* @cond: condition to test until it evaluates to true
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* @timeout: maximum number of microseconds in the timeout
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* @index: loop index (integer)
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*
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* Loop waiting for @cond to become true or until at least @timeout
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* microseconds have passed. To use, define some integer @index in the
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* calling code. After running, if @index == @timeout, then the loop has
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* timed out.
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*/
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#define omap_test_timeout(cond, timeout, index) \
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({ \
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for (index = 0; index < timeout; index++) { \
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if (cond) \
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break; \
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udelay(1); \
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} \
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})
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extern struct device *omap2_get_mpuss_device(void);
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extern struct device *omap2_get_iva_device(void);
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extern struct device *omap2_get_l3_device(void);
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extern struct device *omap4_get_dsp_device(void);
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void omap2_init_irq(void);
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void omap3_init_irq(void);
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2011-12-13 18:46:44 +00:00
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void ti81xx_init_irq(void);
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2011-11-10 21:45:17 +00:00
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extern int omap_irq_pending(void);
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void omap_intc_save_context(void);
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void omap_intc_restore_context(void);
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void omap3_intc_suspend(void);
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void omap3_intc_prepare_idle(void);
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void omap3_intc_resume_idle(void);
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2011-12-05 08:44:58 +00:00
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void omap2_intc_handle_irq(struct pt_regs *regs);
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void omap3_intc_handle_irq(struct pt_regs *regs);
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2012-06-05 11:01:06 +00:00
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void omap_intc_of_init(void);
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void omap_gic_of_init(void);
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2011-11-10 21:45:17 +00:00
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#ifdef CONFIG_CACHE_L2X0
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2011-03-03 12:33:25 +00:00
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extern void __iomem *omap4_get_l2cache_base(void);
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2011-11-10 21:45:17 +00:00
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#endif
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2011-11-30 18:21:07 +00:00
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struct device_node;
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#ifdef CONFIG_OF
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2012-06-05 11:01:06 +00:00
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int __init intc_of_init(struct device_node *node,
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2011-11-30 18:21:07 +00:00
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struct device_node *parent);
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#else
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2012-06-05 11:01:06 +00:00
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int __init intc_of_init(struct device_node *node,
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2011-11-30 18:21:07 +00:00
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struct device_node *parent)
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{
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return 0;
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}
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#endif
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2011-03-03 12:33:25 +00:00
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#ifdef CONFIG_SMP
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extern void __iomem *omap4_get_scu_base(void);
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#else
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static inline void __iomem *omap4_get_scu_base(void)
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{
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return NULL;
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}
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2011-11-10 21:45:17 +00:00
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#endif
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extern void __init gic_init_irq(void);
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ARM: OMAP4460: Workaround for ROM bug because of CA9 r2pX GIC control register change.
On OMAP4+ devices, GIC register context is lost when MPUSS hits
the OSWR(Open Switch Retention). On the CPU wakeup path, ROM code
gets executed and one of the steps in it is to restore the
saved context of the GIC. The ROM Code GIC distributor restoration
is split in two parts: CPU specific register done by each CPU and
common register done by only one CPU.
Below is the abstract flow.
...............................................................
- MPUSS in OSWR state.
- CPU0 wakes up on the event(interrupt) and start executing ROM code.
[..]
- CPU0 executes "GIC Restoration:"
[...]
- CPU0 swicthes to non-secure mode and jumps to OS resume code.
[...]
- CPU0 is online in OS
- CPU0 enables the GIC distributor. GICD.Enable Non-secure = 1
- CPU0 wakes up CPU1 with clock-domain force wakeup method.
- CPU0 continues it's execution.
[..]
- CPU1 wakes up and start executing ROM code.
[..]
- CPU1 executes "GIC Restoration:"
[..]
- CPU1 swicthes to non-secure mode and jumps to OS resume code.
[...]
- CPU1 is online in OS and start executing.
[...] -
GIC Restoration: /* Common routine for HS and GP devices */
{
if (GICD != 1) { /* This will be true in OSWR state */
if (GIC_SAR_BACKUP_STATE == SAVED)
- CPU restores GIC distributor
else
- reconfigure GIC distributor to boot values.
GICD.Enable secure = 1
}
if (GIC_SAR_BACKUP_STATE == SAVED)
- CPU restore its GIC CPU interface registers if saved.
else
- reconfigure its GIC CPU interface registers to boot
values.
}
...............................................................
So as mentioned in the flow, GICD != 1 condition decides how
the GIC registers are handled in ROM code wakeup path from
OSWR. As evident from the flow, ROM code relies on the entire
GICD register value and not specific register bits.
The assumption was valid till CortexA9 r1pX version since there
was only one banked bit to control secure and non-secure GICD.
Secure view which ROM code sees:
bit 0 == Enable Non-secure
Non-secure view which HLOS sees:
bit 0 == Enable secure
But GICD register has changed between CortexA9 r1pX and r2pX.
On r2pX GICD register is composed of 2 bits.
Secure view which ROM code sees:
bit 1 == Enable Non-secure
bit 0 == Enable secure
Non-secure view which HLOS sees:
bit 0 == Enable Non-secure
Hence on OMAP4460(r2pX) devices, if you go through the
above flow again during CPU1 wakeup, GICD == 3 and hence
ROM code fails to understand the real wakeup power state
and reconfigures GIC distributor to boot values. This is
nasty since you loose the entire interrupt controller
context in a live system.
The ROM code fix done on next OMAP4 device (OMAP4470 - r2px) is to
check "GICD.Enable secure != 1" for GIC restoration in OSWR wakeup path.
Since ROM code can't be fixed on OMAP4460 devices, a work around
needs to be implemented. As evident from the flow, as long as
CPU1 sees GICD == 1 in it's wakeup path from OSWR, the issue
won't happen. Below is the flow with the work-around.
...............................................................
- MPUSS in OSWR state.
- CPU0 wakes up on the event(interrupt) and start executing ROM code.
[..]
- CPU0 executes "GIC Restoration:"
[..]
- CPU0 swicthes to non-secure mode and jumps to OS resume code.
[..]
- CPU0 is online in OS.
- CPU0 does GICD.Enable Non-secure = 0
- CPU0 wakes up CPU1 with clock domain force wakeup method.
- CPU0 waits for GICD.Enable Non-secure = 1
- CPU0 coninues it's execution.
[..]
- CPU1 wakes up and start executing ROM code.
[..]
- CPU1 executes "GIC Restoration:"
[..]
- CPU1 swicthes to non-secure mode and jumps to OS resume code.
[..]
- CPU1 is online in OS
- CPU1 does GICD.Enable Non-secure = 1
- CPU1 start executing
[...]
...............................................................
With this procedure, the GIC configuration done between the
CPU0 wakeup and CPU1 wakeup will not be lost but during this
short windows, the CPU0 will not receive interrupts.
The BUG is applicable to only OMAP4460(r2pX) devices.
OMAP4470 (also r2pX) is not affected by this bug because
ROM code has been fixed.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Kevin Hilman <khilman@ti.com>
2012-10-18 09:20:05 +00:00
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extern void gic_dist_disable(void);
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2012-10-18 09:20:08 +00:00
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extern bool gic_dist_disabled(void);
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extern void gic_timer_retrigger(void);
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2011-11-10 21:45:17 +00:00
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extern void omap_smc1(u32 fn, u32 arg);
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2011-01-01 14:26:04 +00:00
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extern void __iomem *omap4_get_sar_ram_base(void);
|
2010-06-16 16:49:48 +00:00
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extern void omap_do_wfi(void);
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2011-11-10 21:45:17 +00:00
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#ifdef CONFIG_SMP
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/* Needed for secondary core boot */
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extern void omap_secondary_startup(void);
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ARM: OMAP4460: Workaround for ROM bug because of CA9 r2pX GIC control register change.
On OMAP4+ devices, GIC register context is lost when MPUSS hits
the OSWR(Open Switch Retention). On the CPU wakeup path, ROM code
gets executed and one of the steps in it is to restore the
saved context of the GIC. The ROM Code GIC distributor restoration
is split in two parts: CPU specific register done by each CPU and
common register done by only one CPU.
Below is the abstract flow.
...............................................................
- MPUSS in OSWR state.
- CPU0 wakes up on the event(interrupt) and start executing ROM code.
[..]
- CPU0 executes "GIC Restoration:"
[...]
- CPU0 swicthes to non-secure mode and jumps to OS resume code.
[...]
- CPU0 is online in OS
- CPU0 enables the GIC distributor. GICD.Enable Non-secure = 1
- CPU0 wakes up CPU1 with clock-domain force wakeup method.
- CPU0 continues it's execution.
[..]
- CPU1 wakes up and start executing ROM code.
[..]
- CPU1 executes "GIC Restoration:"
[..]
- CPU1 swicthes to non-secure mode and jumps to OS resume code.
[...]
- CPU1 is online in OS and start executing.
[...] -
GIC Restoration: /* Common routine for HS and GP devices */
{
if (GICD != 1) { /* This will be true in OSWR state */
if (GIC_SAR_BACKUP_STATE == SAVED)
- CPU restores GIC distributor
else
- reconfigure GIC distributor to boot values.
GICD.Enable secure = 1
}
if (GIC_SAR_BACKUP_STATE == SAVED)
- CPU restore its GIC CPU interface registers if saved.
else
- reconfigure its GIC CPU interface registers to boot
values.
}
...............................................................
So as mentioned in the flow, GICD != 1 condition decides how
the GIC registers are handled in ROM code wakeup path from
OSWR. As evident from the flow, ROM code relies on the entire
GICD register value and not specific register bits.
The assumption was valid till CortexA9 r1pX version since there
was only one banked bit to control secure and non-secure GICD.
Secure view which ROM code sees:
bit 0 == Enable Non-secure
Non-secure view which HLOS sees:
bit 0 == Enable secure
But GICD register has changed between CortexA9 r1pX and r2pX.
On r2pX GICD register is composed of 2 bits.
Secure view which ROM code sees:
bit 1 == Enable Non-secure
bit 0 == Enable secure
Non-secure view which HLOS sees:
bit 0 == Enable Non-secure
Hence on OMAP4460(r2pX) devices, if you go through the
above flow again during CPU1 wakeup, GICD == 3 and hence
ROM code fails to understand the real wakeup power state
and reconfigures GIC distributor to boot values. This is
nasty since you loose the entire interrupt controller
context in a live system.
The ROM code fix done on next OMAP4 device (OMAP4470 - r2px) is to
check "GICD.Enable secure != 1" for GIC restoration in OSWR wakeup path.
Since ROM code can't be fixed on OMAP4460 devices, a work around
needs to be implemented. As evident from the flow, as long as
CPU1 sees GICD == 1 in it's wakeup path from OSWR, the issue
won't happen. Below is the flow with the work-around.
...............................................................
- MPUSS in OSWR state.
- CPU0 wakes up on the event(interrupt) and start executing ROM code.
[..]
- CPU0 executes "GIC Restoration:"
[..]
- CPU0 swicthes to non-secure mode and jumps to OS resume code.
[..]
- CPU0 is online in OS.
- CPU0 does GICD.Enable Non-secure = 0
- CPU0 wakes up CPU1 with clock domain force wakeup method.
- CPU0 waits for GICD.Enable Non-secure = 1
- CPU0 coninues it's execution.
[..]
- CPU1 wakes up and start executing ROM code.
[..]
- CPU1 executes "GIC Restoration:"
[..]
- CPU1 swicthes to non-secure mode and jumps to OS resume code.
[..]
- CPU1 is online in OS
- CPU1 does GICD.Enable Non-secure = 1
- CPU1 start executing
[...]
...............................................................
With this procedure, the GIC configuration done between the
CPU0 wakeup and CPU1 wakeup will not be lost but during this
short windows, the CPU0 will not receive interrupts.
The BUG is applicable to only OMAP4460(r2pX) devices.
OMAP4470 (also r2pX) is not affected by this bug because
ROM code has been fixed.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Kevin Hilman <khilman@ti.com>
2012-10-18 09:20:05 +00:00
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extern void omap_secondary_startup_4460(void);
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2011-11-10 21:45:17 +00:00
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extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask);
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extern void omap_auxcoreboot_addr(u32 cpu_addr);
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extern u32 omap_read_auxcoreboot0(void);
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2011-09-08 12:15:22 +00:00
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extern void omap4_cpu_die(unsigned int cpu);
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extern struct smp_operations omap4_smp_ops;
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2012-03-19 13:59:41 +00:00
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extern void omap5_secondary_startup(void);
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2011-11-10 21:45:17 +00:00
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#endif
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2010-06-16 16:49:48 +00:00
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#if defined(CONFIG_SMP) && defined(CONFIG_PM)
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extern int omap4_mpuss_init(void);
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extern int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state);
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extern int omap4_finish_suspend(unsigned long cpu_state);
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extern void omap4_cpu_resume(void);
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2010-06-16 16:49:48 +00:00
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extern int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state);
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2011-06-06 09:03:29 +00:00
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extern u32 omap4_mpuss_read_prev_context_state(void);
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2010-06-16 16:49:48 +00:00
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#else
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static inline int omap4_enter_lowpower(unsigned int cpu,
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unsigned int power_state)
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{
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cpu_do_idle();
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return 0;
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}
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2010-06-16 16:49:48 +00:00
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static inline int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state)
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{
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cpu_do_idle();
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return 0;
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}
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2010-06-16 16:49:48 +00:00
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static inline int omap4_mpuss_init(void)
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{
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return 0;
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}
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static inline int omap4_finish_suspend(unsigned long cpu_state)
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{
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return 0;
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}
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static inline void omap4_cpu_resume(void)
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{}
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2011-06-06 09:03:29 +00:00
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static inline u32 omap4_mpuss_read_prev_context_state(void)
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{
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return 0;
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}
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2010-06-16 16:49:48 +00:00
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#endif
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2012-02-24 18:34:33 +00:00
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struct omap_sdrc_params;
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extern void omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
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struct omap_sdrc_params *sdrc_cs1);
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2012-04-25 11:57:46 +00:00
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struct omap2_hsmmc_info;
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extern int omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers);
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2012-10-01 18:47:05 +00:00
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extern void omap_reserve(void);
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2012-02-24 18:34:33 +00:00
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2012-10-29 23:45:47 +00:00
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struct omap_hwmod;
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extern int omap_dss_reset(struct omap_hwmod *);
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2012-02-24 18:34:33 +00:00
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2010-06-16 16:49:48 +00:00
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#endif /* __ASSEMBLER__ */
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2011-11-10 21:45:17 +00:00
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#endif /* __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H */
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