2005-07-25 20:10:36 +00:00
|
|
|
####
|
|
|
|
|
# kbuild: Generic definitions
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|
|
|
2007-02-08 21:48:51 +00:00
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|
|
# Convenient variables
|
2005-07-25 20:10:36 +00:00
|
|
|
comma := ,
|
2014-03-20 02:08:20 +00:00
|
|
|
quote := "
|
2006-01-06 21:35:59 +00:00
|
|
|
squote := '
|
2005-07-25 20:10:36 +00:00
|
|
|
empty :=
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|
|
|
|
space := $(empty) $(empty)
|
kbuild: fix if_change and friends to consider argument order
Currently, arg-check is implemented as follows:
arg-check = $(strip $(filter-out $(cmd_$(1)), $(cmd_$@)) \
$(filter-out $(cmd_$@), $(cmd_$(1))) )
This does not care about the order of arguments that appear in
$(cmd_$(1)) and $(cmd_$@). So, if_changed and friends never rebuild
the target if only the argument order is changed. This is a problem
when the link order is changed.
Apparently,
obj-y += foo.o
obj-y += bar.o
and
obj-y += bar.o
obj-y += foo.o
should be distinguished because the link order determines the probe
order of drivers. So, built-in.o should be rebuilt when the order
of objects is changed.
This commit fixes arg-check to compare the old/current commands
including the argument order.
Of course, this change has a side effect; Kbuild will react to the
change of compile option order. For example, "-DFOO -DBAR" and
"-DBAR -DFOO" should give no difference to the build result, but
false positive should be better than false negative.
I am moving space_escape to the top of Kbuild.include just for a
matter of preference. In practical terms, space_escape can be
defined after arg-check because arg-check uses "=" flavor, not ":=".
Having said that, collecting convenient variables in one place makes
sense from the point of readability.
Chaining "%%%SPACE%%%" to "_-_SPACE_-_" is also a matter of taste
at this point. Actually, it can be arbitrary as long as it is an
unlikely used string. The only problem I see in "%%%SPACE%%%" is
that "%" is a special character in "$(patsubst ...)" context. This
commit just uses "$(subst ...)" for arg-check, but I am fixing it now
in case we might want to use it in $(patsubst ...) context in the
future.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Michal Marek <mmarek@suse.com>
2016-05-07 06:48:26 +00:00
|
|
|
space_escape := _-_SPACE_-_
|
kbuild: Add a cache for generated variables
While timing a "no-op" build of the kernel (incrementally building the
kernel even though nothing changed) in the Chrome OS build system I
found that it was much slower than I expected.
Digging into things a bit, I found that quite a bit of the time was
spent invoking the C compiler even though we weren't actually building
anything. Currently in the Chrome OS build system the C compiler is
called through a number of wrappers (one of which is written in
python!) and can take upwards of 100 ms to invoke even if we're not
doing anything difficult, so these invocations of the compiler were
taking a lot of time. Worse the invocations couldn't seem to take
advantage of the multiple cores on my system.
Certainly it seems like we could make the compiler invocations in the
Chrome OS build system faster, but only to a point. Inherently
invoking a program as big as a C compiler is a fairly heavy
operation. Thus even if we can speed the compiler calls it made sense
to track down what was happening.
It turned out that all the compiler invocations were coming from
usages like this in the kernel's Makefile:
KBUILD_CFLAGS += $(call cc-option,-fno-delete-null-pointer-checks,)
Due to the way cc-option and similar statements work the above
contains an implicit call to the C compiler. ...and due to the fact
that we're storing the result in KBUILD_CFLAGS, a simply expanded
variable, the call will happen every time the Makefile is parsed, even
if there are no users of KBUILD_CFLAGS.
Rather than redoing this computation every time, it makes a lot of
sense to cache the result of all of the Makefile's compiler calls just
like we do when we compile a ".c" file to a ".o" file. Conceptually
this is quite a simple idea. ...and since the calls to invoke the
compiler and similar tools are centrally located in the Kbuild.include
file this doesn't even need to be super invasive.
Implementing the cache in a simple-to-use and efficient way is not
quite as simple as it first sounds, though. To get maximum speed we
really want the cache in a format that make can natively understand
and make doesn't really have an ability to load/parse files. ...but
make _can_ import other Makefiles, so the solution is to store the
cache in Makefile format. This requires coming up with a valid/unique
Makefile variable name for each value to be cached, but that's
solvable with some cleverness.
After this change, we'll automatically create a ".cache.mk" file that
will contain our cached variables. We'll load this on each invocation
of make and will avoid recomputing anything that's already in our
cache. The cache is stored in a format that it shouldn't need any
invalidation since anything that might change should affect the "key"
and any old cached value won't be used.
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Tested-by: Ingo Molnar <mingo@kernel.org>
Tested-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-16 17:12:45 +00:00
|
|
|
right_paren := )
|
|
|
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|
left_paren := (
|
Kbuild: fix # escaping in .cmd files for future Make
I tried building using a freshly built Make (4.2.1-69-g8a731d1), but
already the objtool build broke with
orc_dump.c: In function ‘orc_dump’:
orc_dump.c:106:2: error: ‘elf_getshnum’ is deprecated [-Werror=deprecated-declarations]
if (elf_getshdrnum(elf, &nr_sections)) {
Turns out that with that new Make, the backslash was not removed, so cpp
didn't see a #include directive, grep found nothing, and
-DLIBELF_USE_DEPRECATED was wrongly put in CFLAGS.
Now, that new Make behaviour is documented in their NEWS file:
* WARNING: Backward-incompatibility!
Number signs (#) appearing inside a macro reference or function invocation
no longer introduce comments and should not be escaped with backslashes:
thus a call such as:
foo := $(shell echo '#')
is legal. Previously the number sign needed to be escaped, for example:
foo := $(shell echo '\#')
Now this latter will resolve to "\#". If you want to write makefiles
portable to both versions, assign the number sign to a variable:
C := \#
foo := $(shell echo '$C')
This was claimed to be fixed in 3.81, but wasn't, for some reason.
To detect this change search for 'nocomment' in the .FEATURES variable.
This also fixes up the two make-cmd instances to replace # with $(pound)
rather than with \#. There might very well be other places that need
similar fixup in preparation for whatever future Make release contains
the above change, but at least this builds an x86_64 defconfig with the
new make.
Link: https://bugzilla.kernel.org/show_bug.cgi?id=197847
Cc: Randy Dunlap <rdunlap@infradead.org>
Signed-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-04-08 21:35:28 +00:00
|
|
|
pound := \#
|
2005-07-25 20:10:36 +00:00
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|
2006-07-23 17:37:44 +00:00
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|
###
|
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|
# Name of target with a '.' as filename prefix. foo/bar.o => foo/.bar.o
|
|
|
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|
dot-target = $(dir $@).$(notdir $@)
|
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|
|
|
|
2005-07-25 20:10:36 +00:00
|
|
|
###
|
|
|
|
|
# The temporary file to save gcc -MD generated dependencies must not
|
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|
# contain a comma
|
2006-07-23 17:37:44 +00:00
|
|
|
depfile = $(subst $(comma),_,$(dot-target).d)
|
2005-07-25 20:10:36 +00:00
|
|
|
|
2006-07-01 07:58:02 +00:00
|
|
|
###
|
|
|
|
|
# filename of target with directory and extension stripped
|
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|
|
|
basetarget = $(basename $(notdir $@))
|
|
|
|
|
|
2011-06-01 21:50:25 +00:00
|
|
|
###
|
|
|
|
|
# filename of first prerequisite with directory and extension stripped
|
|
|
|
|
baseprereq = $(basename $(notdir $<))
|
|
|
|
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|
2006-01-06 21:35:59 +00:00
|
|
|
###
|
|
|
|
|
# Escape single quote for use in echo statements
|
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|
|
escsq = $(subst $(squote),'\$(squote)',$1)
|
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|
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|
2008-11-06 08:31:34 +00:00
|
|
|
###
|
|
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|
|
# Easy method for doing a status message
|
|
|
|
|
kecho := :
|
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|
|
quiet_kecho := echo
|
|
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|
silent_kecho := :
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|
kecho := $($(quiet)kecho)
|
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|
2005-07-25 20:10:36 +00:00
|
|
|
###
|
|
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|
|
# filechk is used to check if the content of a generated file is updated.
|
|
|
|
|
# Sample usage:
|
|
|
|
|
# define filechk_sample
|
|
|
|
|
# echo $KERNELRELEASE
|
|
|
|
|
# endef
|
|
|
|
|
# version.h : Makefile
|
|
|
|
|
# $(call filechk,sample)
|
|
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|
|
# The rule defined shall write to stdout the content of the new file.
|
|
|
|
|
# The existing file will be compared with the new one.
|
|
|
|
|
# - If no file exist it is created
|
|
|
|
|
# - If the content differ the new file is used
|
|
|
|
|
# - If they are equal no change, and no timestamp update
|
|
|
|
|
# - stdin is piped in from the first prerequisite ($<) so one has
|
|
|
|
|
# to specify a valid file as first prerequisite (often the kbuild file)
|
|
|
|
|
define filechk
|
|
|
|
|
$(Q)set -e; \
|
2008-11-06 08:31:35 +00:00
|
|
|
$(kecho) ' CHK $@'; \
|
2005-07-25 20:10:36 +00:00
|
|
|
mkdir -p $(dir $@); \
|
|
|
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|
$(filechk_$(1)) < $< > $@.tmp; \
|
|
|
|
|
if [ -r $@ ] && cmp -s $@ $@.tmp; then \
|
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|
|
rm -f $@.tmp; \
|
|
|
|
|
else \
|
2008-11-06 08:31:35 +00:00
|
|
|
$(kecho) ' UPD $@'; \
|
2005-07-25 20:10:36 +00:00
|
|
|
mv -f $@.tmp $@; \
|
|
|
|
|
fi
|
|
|
|
|
endef
|
|
|
|
|
|
2006-01-22 12:34:15 +00:00
|
|
|
######
|
2006-02-18 09:03:40 +00:00
|
|
|
# gcc support functions
|
2006-01-22 12:34:15 +00:00
|
|
|
# See documentation in Documentation/kbuild/makefiles.txt
|
|
|
|
|
|
2007-10-19 19:46:01 +00:00
|
|
|
# cc-cross-prefix
|
|
|
|
|
# Usage: CROSS_COMPILE := $(call cc-cross-prefix, m68k-linux-gnu- m68k-linux-)
|
|
|
|
|
# Return first prefix where a prefix$(CC) is found in PATH.
|
|
|
|
|
# If no $(CC) found in PATH with listed prefixes return nothing
|
|
|
|
|
cc-cross-prefix = \
|
|
|
|
|
$(word 1, $(foreach c,$(1), \
|
|
|
|
|
$(shell set -e; \
|
|
|
|
|
if (which $(strip $(c))$(CC)) > /dev/null 2>&1 ; then \
|
|
|
|
|
echo $(c); \
|
|
|
|
|
fi)))
|
|
|
|
|
|
kbuild: Add a cache for generated variables
While timing a "no-op" build of the kernel (incrementally building the
kernel even though nothing changed) in the Chrome OS build system I
found that it was much slower than I expected.
Digging into things a bit, I found that quite a bit of the time was
spent invoking the C compiler even though we weren't actually building
anything. Currently in the Chrome OS build system the C compiler is
called through a number of wrappers (one of which is written in
python!) and can take upwards of 100 ms to invoke even if we're not
doing anything difficult, so these invocations of the compiler were
taking a lot of time. Worse the invocations couldn't seem to take
advantage of the multiple cores on my system.
Certainly it seems like we could make the compiler invocations in the
Chrome OS build system faster, but only to a point. Inherently
invoking a program as big as a C compiler is a fairly heavy
operation. Thus even if we can speed the compiler calls it made sense
to track down what was happening.
It turned out that all the compiler invocations were coming from
usages like this in the kernel's Makefile:
KBUILD_CFLAGS += $(call cc-option,-fno-delete-null-pointer-checks,)
Due to the way cc-option and similar statements work the above
contains an implicit call to the C compiler. ...and due to the fact
that we're storing the result in KBUILD_CFLAGS, a simply expanded
variable, the call will happen every time the Makefile is parsed, even
if there are no users of KBUILD_CFLAGS.
Rather than redoing this computation every time, it makes a lot of
sense to cache the result of all of the Makefile's compiler calls just
like we do when we compile a ".c" file to a ".o" file. Conceptually
this is quite a simple idea. ...and since the calls to invoke the
compiler and similar tools are centrally located in the Kbuild.include
file this doesn't even need to be super invasive.
Implementing the cache in a simple-to-use and efficient way is not
quite as simple as it first sounds, though. To get maximum speed we
really want the cache in a format that make can natively understand
and make doesn't really have an ability to load/parse files. ...but
make _can_ import other Makefiles, so the solution is to store the
cache in Makefile format. This requires coming up with a valid/unique
Makefile variable name for each value to be cached, but that's
solvable with some cleverness.
After this change, we'll automatically create a ".cache.mk" file that
will contain our cached variables. We'll load this on each invocation
of make and will avoid recomputing anything that's already in our
cache. The cache is stored in a format that it shouldn't need any
invalidation since anything that might change should affect the "key"
and any old cached value won't be used.
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Tested-by: Ingo Molnar <mingo@kernel.org>
Tested-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-16 17:12:45 +00:00
|
|
|
# Tools for caching Makefile variables that are "expensive" to compute.
|
|
|
|
|
#
|
|
|
|
|
# Here we want to help deal with variables that take a long time to compute
|
|
|
|
|
# by making it easy to store these variables in a cache.
|
|
|
|
|
#
|
|
|
|
|
# The canonical example here is testing for compiler flags. On a simple system
|
|
|
|
|
# each call to the compiler takes 10 ms, but on a system with a compiler that's
|
|
|
|
|
# called through various wrappers it can take upwards of 100 ms. If we have
|
|
|
|
|
# 100 calls to the compiler this can take 1 second (on a simple system) or 10
|
|
|
|
|
# seconds (on a complicated system).
|
|
|
|
|
#
|
|
|
|
|
# The "cache" will be in Makefile syntax and can be directly included.
|
|
|
|
|
# Any time we try to reference a variable that's not in the cache we'll
|
|
|
|
|
# calculate it and store it in the cache for next time.
|
|
|
|
|
|
|
|
|
|
# Include values from last time
|
|
|
|
|
make-cache := $(if $(KBUILD_EXTMOD),$(KBUILD_EXTMOD)/,$(if $(obj),$(obj)/)).cache.mk
|
|
|
|
|
$(make-cache): ;
|
|
|
|
|
-include $(make-cache)
|
|
|
|
|
|
2017-11-13 10:29:34 +00:00
|
|
|
cached-data := $(filter __cached_%, $(.VARIABLES))
|
|
|
|
|
|
2017-10-13 11:25:29 +00:00
|
|
|
# If cache exceeds 1000 lines, shrink it down to 500.
|
2017-11-13 10:29:34 +00:00
|
|
|
ifneq ($(word 1000,$(cached-data)),)
|
2017-10-13 11:25:29 +00:00
|
|
|
$(shell tail -n 500 $(make-cache) > $(make-cache).tmp; \
|
|
|
|
|
mv $(make-cache).tmp $(make-cache))
|
|
|
|
|
endif
|
|
|
|
|
|
2017-11-13 10:29:34 +00:00
|
|
|
create-cache-dir := $(if $(KBUILD_SRC),$(if $(cache-data),,1))
|
|
|
|
|
|
kbuild: Add a cache for generated variables
While timing a "no-op" build of the kernel (incrementally building the
kernel even though nothing changed) in the Chrome OS build system I
found that it was much slower than I expected.
Digging into things a bit, I found that quite a bit of the time was
spent invoking the C compiler even though we weren't actually building
anything. Currently in the Chrome OS build system the C compiler is
called through a number of wrappers (one of which is written in
python!) and can take upwards of 100 ms to invoke even if we're not
doing anything difficult, so these invocations of the compiler were
taking a lot of time. Worse the invocations couldn't seem to take
advantage of the multiple cores on my system.
Certainly it seems like we could make the compiler invocations in the
Chrome OS build system faster, but only to a point. Inherently
invoking a program as big as a C compiler is a fairly heavy
operation. Thus even if we can speed the compiler calls it made sense
to track down what was happening.
It turned out that all the compiler invocations were coming from
usages like this in the kernel's Makefile:
KBUILD_CFLAGS += $(call cc-option,-fno-delete-null-pointer-checks,)
Due to the way cc-option and similar statements work the above
contains an implicit call to the C compiler. ...and due to the fact
that we're storing the result in KBUILD_CFLAGS, a simply expanded
variable, the call will happen every time the Makefile is parsed, even
if there are no users of KBUILD_CFLAGS.
Rather than redoing this computation every time, it makes a lot of
sense to cache the result of all of the Makefile's compiler calls just
like we do when we compile a ".c" file to a ".o" file. Conceptually
this is quite a simple idea. ...and since the calls to invoke the
compiler and similar tools are centrally located in the Kbuild.include
file this doesn't even need to be super invasive.
Implementing the cache in a simple-to-use and efficient way is not
quite as simple as it first sounds, though. To get maximum speed we
really want the cache in a format that make can natively understand
and make doesn't really have an ability to load/parse files. ...but
make _can_ import other Makefiles, so the solution is to store the
cache in Makefile format. This requires coming up with a valid/unique
Makefile variable name for each value to be cached, but that's
solvable with some cleverness.
After this change, we'll automatically create a ".cache.mk" file that
will contain our cached variables. We'll load this on each invocation
of make and will avoid recomputing anything that's already in our
cache. The cache is stored in a format that it shouldn't need any
invalidation since anything that might change should affect the "key"
and any old cached value won't be used.
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Tested-by: Ingo Molnar <mingo@kernel.org>
Tested-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-16 17:12:45 +00:00
|
|
|
# Usage: $(call __sanitize-opt,Hello=Hola$(comma)Goodbye Adios)
|
|
|
|
|
#
|
|
|
|
|
# Convert all '$', ')', '(', '\', '=', ' ', ',', ':' to '_'
|
|
|
|
|
__sanitize-opt = $(subst $$,_,$(subst $(right_paren),_,$(subst $(left_paren),_,$(subst \,_,$(subst =,_,$(subst $(space),_,$(subst $(comma),_,$(subst :,_,$(1)))))))))
|
|
|
|
|
|
|
|
|
|
# Usage: $(call shell-cached,shell_command)
|
|
|
|
|
# Example: $(call shell-cached,md5sum /usr/bin/gcc)
|
|
|
|
|
#
|
|
|
|
|
# If we've already seen a call to this exact shell command (even in a
|
|
|
|
|
# previous invocation of make!) we'll return the value. If not, we'll
|
|
|
|
|
# compute it and store the result for future runs.
|
|
|
|
|
#
|
|
|
|
|
# This is a bit of voodoo, but basic explanation is that if the variable
|
|
|
|
|
# was undefined then we'll evaluate the shell command and store the result
|
|
|
|
|
# into the variable. We'll then store that value in the cache and finally
|
|
|
|
|
# output the value.
|
|
|
|
|
#
|
|
|
|
|
# NOTE: The $$(2) here isn't actually a parameter to __run-and-store. We
|
|
|
|
|
# happen to know that the caller will have their shell command in $(2) so the
|
|
|
|
|
# result of "call"ing this will produce a reference to that $(2). The reason
|
|
|
|
|
# for this strangeness is to avoid an extra level of eval (and escaping) of
|
|
|
|
|
# $(2).
|
|
|
|
|
define __run-and-store
|
|
|
|
|
ifeq ($(origin $(1)),undefined)
|
|
|
|
|
$$(eval $(1) := $$(shell $$(2)))
|
2017-11-13 10:29:34 +00:00
|
|
|
ifeq ($(create-cache-dir),1)
|
|
|
|
|
$$(shell mkdir -p $(dir $(make-cache)))
|
|
|
|
|
$$(eval create-cache-dir :=)
|
|
|
|
|
endif
|
kbuild: Add a cache for generated variables
While timing a "no-op" build of the kernel (incrementally building the
kernel even though nothing changed) in the Chrome OS build system I
found that it was much slower than I expected.
Digging into things a bit, I found that quite a bit of the time was
spent invoking the C compiler even though we weren't actually building
anything. Currently in the Chrome OS build system the C compiler is
called through a number of wrappers (one of which is written in
python!) and can take upwards of 100 ms to invoke even if we're not
doing anything difficult, so these invocations of the compiler were
taking a lot of time. Worse the invocations couldn't seem to take
advantage of the multiple cores on my system.
Certainly it seems like we could make the compiler invocations in the
Chrome OS build system faster, but only to a point. Inherently
invoking a program as big as a C compiler is a fairly heavy
operation. Thus even if we can speed the compiler calls it made sense
to track down what was happening.
It turned out that all the compiler invocations were coming from
usages like this in the kernel's Makefile:
KBUILD_CFLAGS += $(call cc-option,-fno-delete-null-pointer-checks,)
Due to the way cc-option and similar statements work the above
contains an implicit call to the C compiler. ...and due to the fact
that we're storing the result in KBUILD_CFLAGS, a simply expanded
variable, the call will happen every time the Makefile is parsed, even
if there are no users of KBUILD_CFLAGS.
Rather than redoing this computation every time, it makes a lot of
sense to cache the result of all of the Makefile's compiler calls just
like we do when we compile a ".c" file to a ".o" file. Conceptually
this is quite a simple idea. ...and since the calls to invoke the
compiler and similar tools are centrally located in the Kbuild.include
file this doesn't even need to be super invasive.
Implementing the cache in a simple-to-use and efficient way is not
quite as simple as it first sounds, though. To get maximum speed we
really want the cache in a format that make can natively understand
and make doesn't really have an ability to load/parse files. ...but
make _can_ import other Makefiles, so the solution is to store the
cache in Makefile format. This requires coming up with a valid/unique
Makefile variable name for each value to be cached, but that's
solvable with some cleverness.
After this change, we'll automatically create a ".cache.mk" file that
will contain our cached variables. We'll load this on each invocation
of make and will avoid recomputing anything that's already in our
cache. The cache is stored in a format that it shouldn't need any
invalidation since anything that might change should affect the "key"
and any old cached value won't be used.
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Tested-by: Ingo Molnar <mingo@kernel.org>
Tested-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-16 17:12:45 +00:00
|
|
|
$$(shell echo '$(1) := $$($(1))' >> $(make-cache))
|
|
|
|
|
endif
|
|
|
|
|
endef
|
|
|
|
|
__shell-cached = $(eval $(call __run-and-store,$(1)))$($(1))
|
|
|
|
|
shell-cached = $(call __shell-cached,__cached_$(call __sanitize-opt,$(1)),$(1))
|
|
|
|
|
|
2007-02-08 21:48:51 +00:00
|
|
|
# output directory for tests below
|
|
|
|
|
TMPOUT := $(if $(KBUILD_EXTMOD),$(firstword $(KBUILD_EXTMOD))/)
|
|
|
|
|
|
|
|
|
|
# try-run
|
|
|
|
|
# Usage: option = $(call try-run, $(CC)...-o "$$TMP",option-ok,otherwise)
|
2017-08-02 02:31:06 +00:00
|
|
|
# Exit code chooses option. "$$TMP" serves as a temporary file and is
|
|
|
|
|
# automatically cleaned up.
|
kbuild: Add a cache for generated variables
While timing a "no-op" build of the kernel (incrementally building the
kernel even though nothing changed) in the Chrome OS build system I
found that it was much slower than I expected.
Digging into things a bit, I found that quite a bit of the time was
spent invoking the C compiler even though we weren't actually building
anything. Currently in the Chrome OS build system the C compiler is
called through a number of wrappers (one of which is written in
python!) and can take upwards of 100 ms to invoke even if we're not
doing anything difficult, so these invocations of the compiler were
taking a lot of time. Worse the invocations couldn't seem to take
advantage of the multiple cores on my system.
Certainly it seems like we could make the compiler invocations in the
Chrome OS build system faster, but only to a point. Inherently
invoking a program as big as a C compiler is a fairly heavy
operation. Thus even if we can speed the compiler calls it made sense
to track down what was happening.
It turned out that all the compiler invocations were coming from
usages like this in the kernel's Makefile:
KBUILD_CFLAGS += $(call cc-option,-fno-delete-null-pointer-checks,)
Due to the way cc-option and similar statements work the above
contains an implicit call to the C compiler. ...and due to the fact
that we're storing the result in KBUILD_CFLAGS, a simply expanded
variable, the call will happen every time the Makefile is parsed, even
if there are no users of KBUILD_CFLAGS.
Rather than redoing this computation every time, it makes a lot of
sense to cache the result of all of the Makefile's compiler calls just
like we do when we compile a ".c" file to a ".o" file. Conceptually
this is quite a simple idea. ...and since the calls to invoke the
compiler and similar tools are centrally located in the Kbuild.include
file this doesn't even need to be super invasive.
Implementing the cache in a simple-to-use and efficient way is not
quite as simple as it first sounds, though. To get maximum speed we
really want the cache in a format that make can natively understand
and make doesn't really have an ability to load/parse files. ...but
make _can_ import other Makefiles, so the solution is to store the
cache in Makefile format. This requires coming up with a valid/unique
Makefile variable name for each value to be cached, but that's
solvable with some cleverness.
After this change, we'll automatically create a ".cache.mk" file that
will contain our cached variables. We'll load this on each invocation
of make and will avoid recomputing anything that's already in our
cache. The cache is stored in a format that it shouldn't need any
invalidation since anything that might change should affect the "key"
and any old cached value won't be used.
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Tested-by: Ingo Molnar <mingo@kernel.org>
Tested-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-16 17:12:45 +00:00
|
|
|
__try-run = set -e; \
|
2007-02-08 21:48:51 +00:00
|
|
|
TMP="$(TMPOUT).$$$$.tmp"; \
|
2009-09-19 08:31:45 +00:00
|
|
|
TMPO="$(TMPOUT).$$$$.o"; \
|
2007-02-08 21:48:51 +00:00
|
|
|
if ($(1)) >/dev/null 2>&1; \
|
|
|
|
|
then echo "$(2)"; \
|
|
|
|
|
else echo "$(3)"; \
|
|
|
|
|
fi; \
|
kbuild: Add a cache for generated variables
While timing a "no-op" build of the kernel (incrementally building the
kernel even though nothing changed) in the Chrome OS build system I
found that it was much slower than I expected.
Digging into things a bit, I found that quite a bit of the time was
spent invoking the C compiler even though we weren't actually building
anything. Currently in the Chrome OS build system the C compiler is
called through a number of wrappers (one of which is written in
python!) and can take upwards of 100 ms to invoke even if we're not
doing anything difficult, so these invocations of the compiler were
taking a lot of time. Worse the invocations couldn't seem to take
advantage of the multiple cores on my system.
Certainly it seems like we could make the compiler invocations in the
Chrome OS build system faster, but only to a point. Inherently
invoking a program as big as a C compiler is a fairly heavy
operation. Thus even if we can speed the compiler calls it made sense
to track down what was happening.
It turned out that all the compiler invocations were coming from
usages like this in the kernel's Makefile:
KBUILD_CFLAGS += $(call cc-option,-fno-delete-null-pointer-checks,)
Due to the way cc-option and similar statements work the above
contains an implicit call to the C compiler. ...and due to the fact
that we're storing the result in KBUILD_CFLAGS, a simply expanded
variable, the call will happen every time the Makefile is parsed, even
if there are no users of KBUILD_CFLAGS.
Rather than redoing this computation every time, it makes a lot of
sense to cache the result of all of the Makefile's compiler calls just
like we do when we compile a ".c" file to a ".o" file. Conceptually
this is quite a simple idea. ...and since the calls to invoke the
compiler and similar tools are centrally located in the Kbuild.include
file this doesn't even need to be super invasive.
Implementing the cache in a simple-to-use and efficient way is not
quite as simple as it first sounds, though. To get maximum speed we
really want the cache in a format that make can natively understand
and make doesn't really have an ability to load/parse files. ...but
make _can_ import other Makefiles, so the solution is to store the
cache in Makefile format. This requires coming up with a valid/unique
Makefile variable name for each value to be cached, but that's
solvable with some cleverness.
After this change, we'll automatically create a ".cache.mk" file that
will contain our cached variables. We'll load this on each invocation
of make and will avoid recomputing anything that's already in our
cache. The cache is stored in a format that it shouldn't need any
invalidation since anything that might change should affect the "key"
and any old cached value won't be used.
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Tested-by: Ingo Molnar <mingo@kernel.org>
Tested-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-16 17:12:45 +00:00
|
|
|
rm -f "$$TMP" "$$TMPO"
|
|
|
|
|
|
|
|
|
|
try-run = $(shell $(__try-run))
|
|
|
|
|
|
|
|
|
|
# try-run-cached
|
|
|
|
|
# This works like try-run, but the result is cached.
|
|
|
|
|
try-run-cached = $(call shell-cached,$(__try-run))
|
2006-12-10 10:18:41 +00:00
|
|
|
|
2006-01-22 12:34:15 +00:00
|
|
|
# as-option
|
2007-02-07 22:04:35 +00:00
|
|
|
# Usage: cflags-y += $(call as-option,-Wa$(comma)-isa=foo,)
|
2007-02-08 21:48:51 +00:00
|
|
|
|
kbuild: Add a cache for generated variables
While timing a "no-op" build of the kernel (incrementally building the
kernel even though nothing changed) in the Chrome OS build system I
found that it was much slower than I expected.
Digging into things a bit, I found that quite a bit of the time was
spent invoking the C compiler even though we weren't actually building
anything. Currently in the Chrome OS build system the C compiler is
called through a number of wrappers (one of which is written in
python!) and can take upwards of 100 ms to invoke even if we're not
doing anything difficult, so these invocations of the compiler were
taking a lot of time. Worse the invocations couldn't seem to take
advantage of the multiple cores on my system.
Certainly it seems like we could make the compiler invocations in the
Chrome OS build system faster, but only to a point. Inherently
invoking a program as big as a C compiler is a fairly heavy
operation. Thus even if we can speed the compiler calls it made sense
to track down what was happening.
It turned out that all the compiler invocations were coming from
usages like this in the kernel's Makefile:
KBUILD_CFLAGS += $(call cc-option,-fno-delete-null-pointer-checks,)
Due to the way cc-option and similar statements work the above
contains an implicit call to the C compiler. ...and due to the fact
that we're storing the result in KBUILD_CFLAGS, a simply expanded
variable, the call will happen every time the Makefile is parsed, even
if there are no users of KBUILD_CFLAGS.
Rather than redoing this computation every time, it makes a lot of
sense to cache the result of all of the Makefile's compiler calls just
like we do when we compile a ".c" file to a ".o" file. Conceptually
this is quite a simple idea. ...and since the calls to invoke the
compiler and similar tools are centrally located in the Kbuild.include
file this doesn't even need to be super invasive.
Implementing the cache in a simple-to-use and efficient way is not
quite as simple as it first sounds, though. To get maximum speed we
really want the cache in a format that make can natively understand
and make doesn't really have an ability to load/parse files. ...but
make _can_ import other Makefiles, so the solution is to store the
cache in Makefile format. This requires coming up with a valid/unique
Makefile variable name for each value to be cached, but that's
solvable with some cleverness.
After this change, we'll automatically create a ".cache.mk" file that
will contain our cached variables. We'll load this on each invocation
of make and will avoid recomputing anything that's already in our
cache. The cache is stored in a format that it shouldn't need any
invalidation since anything that might change should affect the "key"
and any old cached value won't be used.
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Tested-by: Ingo Molnar <mingo@kernel.org>
Tested-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-16 17:12:45 +00:00
|
|
|
as-option = $(call try-run-cached,\
|
2012-10-02 14:42:36 +00:00
|
|
|
$(CC) $(KBUILD_CFLAGS) $(1) -c -x assembler /dev/null -o "$$TMP",$(1),$(2))
|
2006-01-22 12:34:15 +00:00
|
|
|
|
2006-09-26 08:52:30 +00:00
|
|
|
# as-instr
|
2007-02-07 22:04:35 +00:00
|
|
|
# Usage: cflags-y += $(call as-instr,instr,option1,option2)
|
2007-02-08 21:48:51 +00:00
|
|
|
|
kbuild: Add a cache for generated variables
While timing a "no-op" build of the kernel (incrementally building the
kernel even though nothing changed) in the Chrome OS build system I
found that it was much slower than I expected.
Digging into things a bit, I found that quite a bit of the time was
spent invoking the C compiler even though we weren't actually building
anything. Currently in the Chrome OS build system the C compiler is
called through a number of wrappers (one of which is written in
python!) and can take upwards of 100 ms to invoke even if we're not
doing anything difficult, so these invocations of the compiler were
taking a lot of time. Worse the invocations couldn't seem to take
advantage of the multiple cores on my system.
Certainly it seems like we could make the compiler invocations in the
Chrome OS build system faster, but only to a point. Inherently
invoking a program as big as a C compiler is a fairly heavy
operation. Thus even if we can speed the compiler calls it made sense
to track down what was happening.
It turned out that all the compiler invocations were coming from
usages like this in the kernel's Makefile:
KBUILD_CFLAGS += $(call cc-option,-fno-delete-null-pointer-checks,)
Due to the way cc-option and similar statements work the above
contains an implicit call to the C compiler. ...and due to the fact
that we're storing the result in KBUILD_CFLAGS, a simply expanded
variable, the call will happen every time the Makefile is parsed, even
if there are no users of KBUILD_CFLAGS.
Rather than redoing this computation every time, it makes a lot of
sense to cache the result of all of the Makefile's compiler calls just
like we do when we compile a ".c" file to a ".o" file. Conceptually
this is quite a simple idea. ...and since the calls to invoke the
compiler and similar tools are centrally located in the Kbuild.include
file this doesn't even need to be super invasive.
Implementing the cache in a simple-to-use and efficient way is not
quite as simple as it first sounds, though. To get maximum speed we
really want the cache in a format that make can natively understand
and make doesn't really have an ability to load/parse files. ...but
make _can_ import other Makefiles, so the solution is to store the
cache in Makefile format. This requires coming up with a valid/unique
Makefile variable name for each value to be cached, but that's
solvable with some cleverness.
After this change, we'll automatically create a ".cache.mk" file that
will contain our cached variables. We'll load this on each invocation
of make and will avoid recomputing anything that's already in our
cache. The cache is stored in a format that it shouldn't need any
invalidation since anything that might change should affect the "key"
and any old cached value won't be used.
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Tested-by: Ingo Molnar <mingo@kernel.org>
Tested-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-16 17:12:45 +00:00
|
|
|
as-instr = $(call try-run-cached,\
|
2012-10-02 14:42:36 +00:00
|
|
|
printf "%b\n" "$(1)" | $(CC) $(KBUILD_AFLAGS) -c -x assembler -o "$$TMP" -,$(2),$(3))
|
2006-09-26 08:52:30 +00:00
|
|
|
|
2017-06-21 23:28:03 +00:00
|
|
|
# __cc-option
|
|
|
|
|
# Usage: MY_CFLAGS += $(call __cc-option,$(CC),$(MY_CFLAGS),-march=winchip-c6,-march=i586)
|
kbuild: Add a cache for generated variables
While timing a "no-op" build of the kernel (incrementally building the
kernel even though nothing changed) in the Chrome OS build system I
found that it was much slower than I expected.
Digging into things a bit, I found that quite a bit of the time was
spent invoking the C compiler even though we weren't actually building
anything. Currently in the Chrome OS build system the C compiler is
called through a number of wrappers (one of which is written in
python!) and can take upwards of 100 ms to invoke even if we're not
doing anything difficult, so these invocations of the compiler were
taking a lot of time. Worse the invocations couldn't seem to take
advantage of the multiple cores on my system.
Certainly it seems like we could make the compiler invocations in the
Chrome OS build system faster, but only to a point. Inherently
invoking a program as big as a C compiler is a fairly heavy
operation. Thus even if we can speed the compiler calls it made sense
to track down what was happening.
It turned out that all the compiler invocations were coming from
usages like this in the kernel's Makefile:
KBUILD_CFLAGS += $(call cc-option,-fno-delete-null-pointer-checks,)
Due to the way cc-option and similar statements work the above
contains an implicit call to the C compiler. ...and due to the fact
that we're storing the result in KBUILD_CFLAGS, a simply expanded
variable, the call will happen every time the Makefile is parsed, even
if there are no users of KBUILD_CFLAGS.
Rather than redoing this computation every time, it makes a lot of
sense to cache the result of all of the Makefile's compiler calls just
like we do when we compile a ".c" file to a ".o" file. Conceptually
this is quite a simple idea. ...and since the calls to invoke the
compiler and similar tools are centrally located in the Kbuild.include
file this doesn't even need to be super invasive.
Implementing the cache in a simple-to-use and efficient way is not
quite as simple as it first sounds, though. To get maximum speed we
really want the cache in a format that make can natively understand
and make doesn't really have an ability to load/parse files. ...but
make _can_ import other Makefiles, so the solution is to store the
cache in Makefile format. This requires coming up with a valid/unique
Makefile variable name for each value to be cached, but that's
solvable with some cleverness.
After this change, we'll automatically create a ".cache.mk" file that
will contain our cached variables. We'll load this on each invocation
of make and will avoid recomputing anything that's already in our
cache. The cache is stored in a format that it shouldn't need any
invalidation since anything that might change should affect the "key"
and any old cached value won't be used.
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Tested-by: Ingo Molnar <mingo@kernel.org>
Tested-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-16 17:12:45 +00:00
|
|
|
__cc-option = $(call try-run-cached,\
|
2017-06-21 23:28:03 +00:00
|
|
|
$(1) -Werror $(2) $(3) -c -x c /dev/null -o "$$TMP",$(3),$(4))
|
|
|
|
|
|
2016-06-18 06:28:34 +00:00
|
|
|
# Do not attempt to build with gcc plugins during cc-option tests.
|
|
|
|
|
# (And this uses delayed resolution so the flags will be up to date.)
|
|
|
|
|
CC_OPTION_CFLAGS = $(filter-out $(GCC_PLUGINS_CFLAGS),$(KBUILD_CFLAGS))
|
|
|
|
|
|
2006-01-22 12:34:15 +00:00
|
|
|
# cc-option
|
2007-02-07 22:04:35 +00:00
|
|
|
# Usage: cflags-y += $(call cc-option,-march=winchip-c6,-march=i586)
|
2007-02-08 21:48:51 +00:00
|
|
|
|
2017-06-21 23:28:03 +00:00
|
|
|
cc-option = $(call __cc-option, $(CC),\
|
|
|
|
|
$(KBUILD_CPPFLAGS) $(CC_OPTION_CFLAGS),$(1),$(2))
|
|
|
|
|
|
|
|
|
|
# hostcc-option
|
|
|
|
|
# Usage: cflags-y += $(call hostcc-option,-march=winchip-c6,-march=i586)
|
|
|
|
|
hostcc-option = $(call __cc-option, $(HOSTCC),\
|
|
|
|
|
$(HOSTCFLAGS) $(HOST_EXTRACFLAGS),$(1),$(2))
|
2006-01-22 12:34:15 +00:00
|
|
|
|
|
|
|
|
# cc-option-yn
|
2007-02-07 22:04:35 +00:00
|
|
|
# Usage: flag := $(call cc-option-yn,-march=winchip-c6)
|
kbuild: Add a cache for generated variables
While timing a "no-op" build of the kernel (incrementally building the
kernel even though nothing changed) in the Chrome OS build system I
found that it was much slower than I expected.
Digging into things a bit, I found that quite a bit of the time was
spent invoking the C compiler even though we weren't actually building
anything. Currently in the Chrome OS build system the C compiler is
called through a number of wrappers (one of which is written in
python!) and can take upwards of 100 ms to invoke even if we're not
doing anything difficult, so these invocations of the compiler were
taking a lot of time. Worse the invocations couldn't seem to take
advantage of the multiple cores on my system.
Certainly it seems like we could make the compiler invocations in the
Chrome OS build system faster, but only to a point. Inherently
invoking a program as big as a C compiler is a fairly heavy
operation. Thus even if we can speed the compiler calls it made sense
to track down what was happening.
It turned out that all the compiler invocations were coming from
usages like this in the kernel's Makefile:
KBUILD_CFLAGS += $(call cc-option,-fno-delete-null-pointer-checks,)
Due to the way cc-option and similar statements work the above
contains an implicit call to the C compiler. ...and due to the fact
that we're storing the result in KBUILD_CFLAGS, a simply expanded
variable, the call will happen every time the Makefile is parsed, even
if there are no users of KBUILD_CFLAGS.
Rather than redoing this computation every time, it makes a lot of
sense to cache the result of all of the Makefile's compiler calls just
like we do when we compile a ".c" file to a ".o" file. Conceptually
this is quite a simple idea. ...and since the calls to invoke the
compiler and similar tools are centrally located in the Kbuild.include
file this doesn't even need to be super invasive.
Implementing the cache in a simple-to-use and efficient way is not
quite as simple as it first sounds, though. To get maximum speed we
really want the cache in a format that make can natively understand
and make doesn't really have an ability to load/parse files. ...but
make _can_ import other Makefiles, so the solution is to store the
cache in Makefile format. This requires coming up with a valid/unique
Makefile variable name for each value to be cached, but that's
solvable with some cleverness.
After this change, we'll automatically create a ".cache.mk" file that
will contain our cached variables. We'll load this on each invocation
of make and will avoid recomputing anything that's already in our
cache. The cache is stored in a format that it shouldn't need any
invalidation since anything that might change should affect the "key"
and any old cached value won't be used.
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Tested-by: Ingo Molnar <mingo@kernel.org>
Tested-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-16 17:12:45 +00:00
|
|
|
cc-option-yn = $(call try-run-cached,\
|
2017-03-31 20:38:13 +00:00
|
|
|
$(CC) -Werror $(KBUILD_CPPFLAGS) $(CC_OPTION_CFLAGS) $(1) -c -x c /dev/null -o "$$TMP",y,n)
|
2006-01-22 12:34:15 +00:00
|
|
|
|
2011-05-02 10:51:15 +00:00
|
|
|
# cc-disable-warning
|
|
|
|
|
# Usage: cflags-y += $(call cc-disable-warning,unused-but-set-variable)
|
kbuild: Add a cache for generated variables
While timing a "no-op" build of the kernel (incrementally building the
kernel even though nothing changed) in the Chrome OS build system I
found that it was much slower than I expected.
Digging into things a bit, I found that quite a bit of the time was
spent invoking the C compiler even though we weren't actually building
anything. Currently in the Chrome OS build system the C compiler is
called through a number of wrappers (one of which is written in
python!) and can take upwards of 100 ms to invoke even if we're not
doing anything difficult, so these invocations of the compiler were
taking a lot of time. Worse the invocations couldn't seem to take
advantage of the multiple cores on my system.
Certainly it seems like we could make the compiler invocations in the
Chrome OS build system faster, but only to a point. Inherently
invoking a program as big as a C compiler is a fairly heavy
operation. Thus even if we can speed the compiler calls it made sense
to track down what was happening.
It turned out that all the compiler invocations were coming from
usages like this in the kernel's Makefile:
KBUILD_CFLAGS += $(call cc-option,-fno-delete-null-pointer-checks,)
Due to the way cc-option and similar statements work the above
contains an implicit call to the C compiler. ...and due to the fact
that we're storing the result in KBUILD_CFLAGS, a simply expanded
variable, the call will happen every time the Makefile is parsed, even
if there are no users of KBUILD_CFLAGS.
Rather than redoing this computation every time, it makes a lot of
sense to cache the result of all of the Makefile's compiler calls just
like we do when we compile a ".c" file to a ".o" file. Conceptually
this is quite a simple idea. ...and since the calls to invoke the
compiler and similar tools are centrally located in the Kbuild.include
file this doesn't even need to be super invasive.
Implementing the cache in a simple-to-use and efficient way is not
quite as simple as it first sounds, though. To get maximum speed we
really want the cache in a format that make can natively understand
and make doesn't really have an ability to load/parse files. ...but
make _can_ import other Makefiles, so the solution is to store the
cache in Makefile format. This requires coming up with a valid/unique
Makefile variable name for each value to be cached, but that's
solvable with some cleverness.
After this change, we'll automatically create a ".cache.mk" file that
will contain our cached variables. We'll load this on each invocation
of make and will avoid recomputing anything that's already in our
cache. The cache is stored in a format that it shouldn't need any
invalidation since anything that might change should affect the "key"
and any old cached value won't be used.
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Tested-by: Ingo Molnar <mingo@kernel.org>
Tested-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-16 17:12:45 +00:00
|
|
|
cc-disable-warning = $(call try-run-cached,\
|
2017-03-31 20:38:13 +00:00
|
|
|
$(CC) -Werror $(KBUILD_CPPFLAGS) $(CC_OPTION_CFLAGS) -W$(strip $(1)) -c -x c /dev/null -o "$$TMP",-Wno-$(strip $(1)))
|
2011-05-02 10:51:15 +00:00
|
|
|
|
2015-08-19 15:36:41 +00:00
|
|
|
# cc-name
|
|
|
|
|
# Expands to either gcc or clang
|
kbuild: Add a cache for generated variables
While timing a "no-op" build of the kernel (incrementally building the
kernel even though nothing changed) in the Chrome OS build system I
found that it was much slower than I expected.
Digging into things a bit, I found that quite a bit of the time was
spent invoking the C compiler even though we weren't actually building
anything. Currently in the Chrome OS build system the C compiler is
called through a number of wrappers (one of which is written in
python!) and can take upwards of 100 ms to invoke even if we're not
doing anything difficult, so these invocations of the compiler were
taking a lot of time. Worse the invocations couldn't seem to take
advantage of the multiple cores on my system.
Certainly it seems like we could make the compiler invocations in the
Chrome OS build system faster, but only to a point. Inherently
invoking a program as big as a C compiler is a fairly heavy
operation. Thus even if we can speed the compiler calls it made sense
to track down what was happening.
It turned out that all the compiler invocations were coming from
usages like this in the kernel's Makefile:
KBUILD_CFLAGS += $(call cc-option,-fno-delete-null-pointer-checks,)
Due to the way cc-option and similar statements work the above
contains an implicit call to the C compiler. ...and due to the fact
that we're storing the result in KBUILD_CFLAGS, a simply expanded
variable, the call will happen every time the Makefile is parsed, even
if there are no users of KBUILD_CFLAGS.
Rather than redoing this computation every time, it makes a lot of
sense to cache the result of all of the Makefile's compiler calls just
like we do when we compile a ".c" file to a ".o" file. Conceptually
this is quite a simple idea. ...and since the calls to invoke the
compiler and similar tools are centrally located in the Kbuild.include
file this doesn't even need to be super invasive.
Implementing the cache in a simple-to-use and efficient way is not
quite as simple as it first sounds, though. To get maximum speed we
really want the cache in a format that make can natively understand
and make doesn't really have an ability to load/parse files. ...but
make _can_ import other Makefiles, so the solution is to store the
cache in Makefile format. This requires coming up with a valid/unique
Makefile variable name for each value to be cached, but that's
solvable with some cleverness.
After this change, we'll automatically create a ".cache.mk" file that
will contain our cached variables. We'll load this on each invocation
of make and will avoid recomputing anything that's already in our
cache. The cache is stored in a format that it shouldn't need any
invalidation since anything that might change should affect the "key"
and any old cached value won't be used.
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Tested-by: Ingo Molnar <mingo@kernel.org>
Tested-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-16 17:12:45 +00:00
|
|
|
cc-name = $(call shell-cached,$(CC) -v 2>&1 | grep -q "clang version" && echo clang || echo gcc)
|
2015-08-19 15:36:41 +00:00
|
|
|
|
2006-01-22 12:34:15 +00:00
|
|
|
# cc-version
|
kbuild: Add a cache for generated variables
While timing a "no-op" build of the kernel (incrementally building the
kernel even though nothing changed) in the Chrome OS build system I
found that it was much slower than I expected.
Digging into things a bit, I found that quite a bit of the time was
spent invoking the C compiler even though we weren't actually building
anything. Currently in the Chrome OS build system the C compiler is
called through a number of wrappers (one of which is written in
python!) and can take upwards of 100 ms to invoke even if we're not
doing anything difficult, so these invocations of the compiler were
taking a lot of time. Worse the invocations couldn't seem to take
advantage of the multiple cores on my system.
Certainly it seems like we could make the compiler invocations in the
Chrome OS build system faster, but only to a point. Inherently
invoking a program as big as a C compiler is a fairly heavy
operation. Thus even if we can speed the compiler calls it made sense
to track down what was happening.
It turned out that all the compiler invocations were coming from
usages like this in the kernel's Makefile:
KBUILD_CFLAGS += $(call cc-option,-fno-delete-null-pointer-checks,)
Due to the way cc-option and similar statements work the above
contains an implicit call to the C compiler. ...and due to the fact
that we're storing the result in KBUILD_CFLAGS, a simply expanded
variable, the call will happen every time the Makefile is parsed, even
if there are no users of KBUILD_CFLAGS.
Rather than redoing this computation every time, it makes a lot of
sense to cache the result of all of the Makefile's compiler calls just
like we do when we compile a ".c" file to a ".o" file. Conceptually
this is quite a simple idea. ...and since the calls to invoke the
compiler and similar tools are centrally located in the Kbuild.include
file this doesn't even need to be super invasive.
Implementing the cache in a simple-to-use and efficient way is not
quite as simple as it first sounds, though. To get maximum speed we
really want the cache in a format that make can natively understand
and make doesn't really have an ability to load/parse files. ...but
make _can_ import other Makefiles, so the solution is to store the
cache in Makefile format. This requires coming up with a valid/unique
Makefile variable name for each value to be cached, but that's
solvable with some cleverness.
After this change, we'll automatically create a ".cache.mk" file that
will contain our cached variables. We'll load this on each invocation
of make and will avoid recomputing anything that's already in our
cache. The cache is stored in a format that it shouldn't need any
invalidation since anything that might change should affect the "key"
and any old cached value won't be used.
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Tested-by: Ingo Molnar <mingo@kernel.org>
Tested-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-16 17:12:45 +00:00
|
|
|
cc-version = $(call shell-cached,$(CONFIG_SHELL) $(srctree)/scripts/gcc-version.sh $(CC))
|
2006-01-22 12:34:15 +00:00
|
|
|
|
2007-05-19 16:49:07 +00:00
|
|
|
# cc-fullversion
|
kbuild: Add a cache for generated variables
While timing a "no-op" build of the kernel (incrementally building the
kernel even though nothing changed) in the Chrome OS build system I
found that it was much slower than I expected.
Digging into things a bit, I found that quite a bit of the time was
spent invoking the C compiler even though we weren't actually building
anything. Currently in the Chrome OS build system the C compiler is
called through a number of wrappers (one of which is written in
python!) and can take upwards of 100 ms to invoke even if we're not
doing anything difficult, so these invocations of the compiler were
taking a lot of time. Worse the invocations couldn't seem to take
advantage of the multiple cores on my system.
Certainly it seems like we could make the compiler invocations in the
Chrome OS build system faster, but only to a point. Inherently
invoking a program as big as a C compiler is a fairly heavy
operation. Thus even if we can speed the compiler calls it made sense
to track down what was happening.
It turned out that all the compiler invocations were coming from
usages like this in the kernel's Makefile:
KBUILD_CFLAGS += $(call cc-option,-fno-delete-null-pointer-checks,)
Due to the way cc-option and similar statements work the above
contains an implicit call to the C compiler. ...and due to the fact
that we're storing the result in KBUILD_CFLAGS, a simply expanded
variable, the call will happen every time the Makefile is parsed, even
if there are no users of KBUILD_CFLAGS.
Rather than redoing this computation every time, it makes a lot of
sense to cache the result of all of the Makefile's compiler calls just
like we do when we compile a ".c" file to a ".o" file. Conceptually
this is quite a simple idea. ...and since the calls to invoke the
compiler and similar tools are centrally located in the Kbuild.include
file this doesn't even need to be super invasive.
Implementing the cache in a simple-to-use and efficient way is not
quite as simple as it first sounds, though. To get maximum speed we
really want the cache in a format that make can natively understand
and make doesn't really have an ability to load/parse files. ...but
make _can_ import other Makefiles, so the solution is to store the
cache in Makefile format. This requires coming up with a valid/unique
Makefile variable name for each value to be cached, but that's
solvable with some cleverness.
After this change, we'll automatically create a ".cache.mk" file that
will contain our cached variables. We'll load this on each invocation
of make and will avoid recomputing anything that's already in our
cache. The cache is stored in a format that it shouldn't need any
invalidation since anything that might change should affect the "key"
and any old cached value won't be used.
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Tested-by: Ingo Molnar <mingo@kernel.org>
Tested-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-16 17:12:45 +00:00
|
|
|
cc-fullversion = $(call shell-cached,$(CONFIG_SHELL) \
|
2007-05-19 16:49:07 +00:00
|
|
|
$(srctree)/scripts/gcc-version.sh -p $(CC))
|
|
|
|
|
|
2006-01-22 12:34:15 +00:00
|
|
|
# cc-ifversion
|
|
|
|
|
# Usage: EXTRA_CFLAGS += $(call cc-ifversion, -lt, 0402, -O1)
|
2014-12-25 05:31:27 +00:00
|
|
|
cc-ifversion = $(shell [ $(cc-version) $(1) $(2) ] && echo $(3) || echo $(4))
|
2006-01-22 12:34:15 +00:00
|
|
|
|
2017-03-16 19:31:33 +00:00
|
|
|
# cc-if-fullversion
|
|
|
|
|
# Usage: EXTRA_CFLAGS += $(call cc-if-fullversion, -lt, 040502, -O1)
|
|
|
|
|
cc-if-fullversion = $(shell [ $(cc-fullversion) $(1) $(2) ] && echo $(3) || echo $(4))
|
|
|
|
|
|
2009-09-19 08:14:33 +00:00
|
|
|
# cc-ldoption
|
|
|
|
|
# Usage: ldflags += $(call cc-ldoption, -Wl$(comma)--hash-style=both)
|
kbuild: Add a cache for generated variables
While timing a "no-op" build of the kernel (incrementally building the
kernel even though nothing changed) in the Chrome OS build system I
found that it was much slower than I expected.
Digging into things a bit, I found that quite a bit of the time was
spent invoking the C compiler even though we weren't actually building
anything. Currently in the Chrome OS build system the C compiler is
called through a number of wrappers (one of which is written in
python!) and can take upwards of 100 ms to invoke even if we're not
doing anything difficult, so these invocations of the compiler were
taking a lot of time. Worse the invocations couldn't seem to take
advantage of the multiple cores on my system.
Certainly it seems like we could make the compiler invocations in the
Chrome OS build system faster, but only to a point. Inherently
invoking a program as big as a C compiler is a fairly heavy
operation. Thus even if we can speed the compiler calls it made sense
to track down what was happening.
It turned out that all the compiler invocations were coming from
usages like this in the kernel's Makefile:
KBUILD_CFLAGS += $(call cc-option,-fno-delete-null-pointer-checks,)
Due to the way cc-option and similar statements work the above
contains an implicit call to the C compiler. ...and due to the fact
that we're storing the result in KBUILD_CFLAGS, a simply expanded
variable, the call will happen every time the Makefile is parsed, even
if there are no users of KBUILD_CFLAGS.
Rather than redoing this computation every time, it makes a lot of
sense to cache the result of all of the Makefile's compiler calls just
like we do when we compile a ".c" file to a ".o" file. Conceptually
this is quite a simple idea. ...and since the calls to invoke the
compiler and similar tools are centrally located in the Kbuild.include
file this doesn't even need to be super invasive.
Implementing the cache in a simple-to-use and efficient way is not
quite as simple as it first sounds, though. To get maximum speed we
really want the cache in a format that make can natively understand
and make doesn't really have an ability to load/parse files. ...but
make _can_ import other Makefiles, so the solution is to store the
cache in Makefile format. This requires coming up with a valid/unique
Makefile variable name for each value to be cached, but that's
solvable with some cleverness.
After this change, we'll automatically create a ".cache.mk" file that
will contain our cached variables. We'll load this on each invocation
of make and will avoid recomputing anything that's already in our
cache. The cache is stored in a format that it shouldn't need any
invalidation since anything that might change should affect the "key"
and any old cached value won't be used.
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Tested-by: Ingo Molnar <mingo@kernel.org>
Tested-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-16 17:12:45 +00:00
|
|
|
cc-ldoption = $(call try-run-cached,\
|
2017-11-06 18:47:54 +00:00
|
|
|
$(CC) $(1) $(KBUILD_CPPFLAGS) $(CC_OPTION_CFLAGS) -nostdlib -x c /dev/null -o "$$TMP",$(1),$(2))
|
2007-02-06 01:18:21 +00:00
|
|
|
|
2009-09-19 08:31:45 +00:00
|
|
|
# ld-option
|
|
|
|
|
# Usage: LDFLAGS += $(call ld-option, -X)
|
2018-02-23 04:56:53 +00:00
|
|
|
ld-option = $(call try-run-cached, $(LD) $(LDFLAGS) $(1) -v,$(1),$(2))
|
2009-09-19 08:31:45 +00:00
|
|
|
|
2011-04-20 11:45:30 +00:00
|
|
|
# ar-option
|
|
|
|
|
# Usage: KBUILD_ARFLAGS := $(call ar-option,D)
|
|
|
|
|
# Important: no spaces around options
|
kbuild: Add a cache for generated variables
While timing a "no-op" build of the kernel (incrementally building the
kernel even though nothing changed) in the Chrome OS build system I
found that it was much slower than I expected.
Digging into things a bit, I found that quite a bit of the time was
spent invoking the C compiler even though we weren't actually building
anything. Currently in the Chrome OS build system the C compiler is
called through a number of wrappers (one of which is written in
python!) and can take upwards of 100 ms to invoke even if we're not
doing anything difficult, so these invocations of the compiler were
taking a lot of time. Worse the invocations couldn't seem to take
advantage of the multiple cores on my system.
Certainly it seems like we could make the compiler invocations in the
Chrome OS build system faster, but only to a point. Inherently
invoking a program as big as a C compiler is a fairly heavy
operation. Thus even if we can speed the compiler calls it made sense
to track down what was happening.
It turned out that all the compiler invocations were coming from
usages like this in the kernel's Makefile:
KBUILD_CFLAGS += $(call cc-option,-fno-delete-null-pointer-checks,)
Due to the way cc-option and similar statements work the above
contains an implicit call to the C compiler. ...and due to the fact
that we're storing the result in KBUILD_CFLAGS, a simply expanded
variable, the call will happen every time the Makefile is parsed, even
if there are no users of KBUILD_CFLAGS.
Rather than redoing this computation every time, it makes a lot of
sense to cache the result of all of the Makefile's compiler calls just
like we do when we compile a ".c" file to a ".o" file. Conceptually
this is quite a simple idea. ...and since the calls to invoke the
compiler and similar tools are centrally located in the Kbuild.include
file this doesn't even need to be super invasive.
Implementing the cache in a simple-to-use and efficient way is not
quite as simple as it first sounds, though. To get maximum speed we
really want the cache in a format that make can natively understand
and make doesn't really have an ability to load/parse files. ...but
make _can_ import other Makefiles, so the solution is to store the
cache in Makefile format. This requires coming up with a valid/unique
Makefile variable name for each value to be cached, but that's
solvable with some cleverness.
After this change, we'll automatically create a ".cache.mk" file that
will contain our cached variables. We'll load this on each invocation
of make and will avoid recomputing anything that's already in our
cache. The cache is stored in a format that it shouldn't need any
invalidation since anything that might change should affect the "key"
and any old cached value won't be used.
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Tested-by: Ingo Molnar <mingo@kernel.org>
Tested-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-16 17:12:45 +00:00
|
|
|
ar-option = $(call try-run-cached, $(AR) rc$(1) "$$TMP",$(1),$(2))
|
2011-04-20 11:45:30 +00:00
|
|
|
|
2014-02-08 08:01:13 +00:00
|
|
|
# ld-version
|
|
|
|
|
# Note this is mainly for HJ Lu's 3 number binutil versions
|
kbuild: Add a cache for generated variables
While timing a "no-op" build of the kernel (incrementally building the
kernel even though nothing changed) in the Chrome OS build system I
found that it was much slower than I expected.
Digging into things a bit, I found that quite a bit of the time was
spent invoking the C compiler even though we weren't actually building
anything. Currently in the Chrome OS build system the C compiler is
called through a number of wrappers (one of which is written in
python!) and can take upwards of 100 ms to invoke even if we're not
doing anything difficult, so these invocations of the compiler were
taking a lot of time. Worse the invocations couldn't seem to take
advantage of the multiple cores on my system.
Certainly it seems like we could make the compiler invocations in the
Chrome OS build system faster, but only to a point. Inherently
invoking a program as big as a C compiler is a fairly heavy
operation. Thus even if we can speed the compiler calls it made sense
to track down what was happening.
It turned out that all the compiler invocations were coming from
usages like this in the kernel's Makefile:
KBUILD_CFLAGS += $(call cc-option,-fno-delete-null-pointer-checks,)
Due to the way cc-option and similar statements work the above
contains an implicit call to the C compiler. ...and due to the fact
that we're storing the result in KBUILD_CFLAGS, a simply expanded
variable, the call will happen every time the Makefile is parsed, even
if there are no users of KBUILD_CFLAGS.
Rather than redoing this computation every time, it makes a lot of
sense to cache the result of all of the Makefile's compiler calls just
like we do when we compile a ".c" file to a ".o" file. Conceptually
this is quite a simple idea. ...and since the calls to invoke the
compiler and similar tools are centrally located in the Kbuild.include
file this doesn't even need to be super invasive.
Implementing the cache in a simple-to-use and efficient way is not
quite as simple as it first sounds, though. To get maximum speed we
really want the cache in a format that make can natively understand
and make doesn't really have an ability to load/parse files. ...but
make _can_ import other Makefiles, so the solution is to store the
cache in Makefile format. This requires coming up with a valid/unique
Makefile variable name for each value to be cached, but that's
solvable with some cleverness.
After this change, we'll automatically create a ".cache.mk" file that
will contain our cached variables. We'll load this on each invocation
of make and will avoid recomputing anything that's already in our
cache. The cache is stored in a format that it shouldn't need any
invalidation since anything that might change should affect the "key"
and any old cached value won't be used.
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Tested-by: Ingo Molnar <mingo@kernel.org>
Tested-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-16 17:12:45 +00:00
|
|
|
ld-version = $(call shell-cached,$(LD) --version | $(srctree)/scripts/ld-version.sh)
|
2014-02-08 08:01:13 +00:00
|
|
|
|
|
|
|
|
# ld-ifversion
|
|
|
|
|
# Usage: $(call ld-ifversion, -ge, 22252, y)
|
2014-12-25 05:31:27 +00:00
|
|
|
ld-ifversion = $(shell [ $(ld-version) $(1) $(2) ] && echo $(3) || echo $(4))
|
2014-02-08 08:01:13 +00:00
|
|
|
|
2007-02-06 01:18:21 +00:00
|
|
|
######
|
[PATCH] vDSO hash-style fix
The latest toolchains can produce a new ELF section in DSOs and
dynamically-linked executables. The new section ".gnu.hash" replaces
".hash", and allows for more efficient runtime symbol lookups by the
dynamic linker. The new ld option --hash-style={sysv|gnu|both} controls
whether to produce the old ".hash", the new ".gnu.hash", or both. In some
new systems such as Fedora Core 6, gcc by default passes --hash-style=gnu
to the linker, so that a standard invocation of "gcc -shared" results in
producing a DSO with only ".gnu.hash". The new ".gnu.hash" sections need
to be dealt with the same way as ".hash" sections in all respects; only the
dynamic linker cares about their contents. To work with older dynamic
linkers (i.e. preexisting releases of glibc), a binary must have the old
".hash" section. The --hash-style=both option produces binaries that a new
dynamic linker can use more efficiently, but an old dynamic linker can
still handle.
The new section runs afoul of the custom linker scripts used to build vDSO
images for the kernel. On ia64, the failure mode for this is a boot-time
panic because the vDSO's PT_IA_64_UNWIND segment winds up ill-formed.
This patch addresses the problem in two ways.
First, it mentions ".gnu.hash" in all the linker scripts alongside ".hash".
This produces correct vDSO images with --hash-style=sysv (or old tools),
with --hash-style=gnu, or with --hash-style=both.
Second, it passes the --hash-style=sysv option when building the vDSO
images, so that ".gnu.hash" is not actually produced. This is the most
conservative choice for compatibility with any old userland. There is some
concern that some ancient glibc builds (though not any known old production
system) might choke on --hash-style=both binaries. The optimizations
provided by the new style of hash section do not really matter for a DSO
with a tiny number of symbols, as the vDSO has. If someone wants to use
=gnu or =both for their vDSO builds and worry less about that
compatibility, just change the option and the linker script changes will
make any choice work fine.
Signed-off-by: Roland McGrath <roland@redhat.com>
Cc: "Luck, Tony" <tony.luck@intel.com>
Cc: Kyle McMartin <kyle@mcmartin.ca>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Jeff Dike <jdike@addtoit.com>
Cc: Andi Kleen <ak@muc.de>
Cc: Sam Ravnborg <sam@ravnborg.org>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-07-30 10:04:06 +00:00
|
|
|
|
2007-02-08 21:48:51 +00:00
|
|
|
###
|
2005-07-25 20:10:36 +00:00
|
|
|
# Shorthand for $(Q)$(MAKE) -f scripts/Makefile.build obj=
|
|
|
|
|
# Usage:
|
|
|
|
|
# $(Q)$(MAKE) $(build)=dir
|
2014-09-09 11:03:58 +00:00
|
|
|
build := -f $(srctree)/scripts/Makefile.build obj
|
2005-07-25 20:10:36 +00:00
|
|
|
|
2009-12-07 15:38:33 +00:00
|
|
|
###
|
|
|
|
|
# Shorthand for $(Q)$(MAKE) -f scripts/Makefile.modbuiltin obj=
|
|
|
|
|
# Usage:
|
|
|
|
|
# $(Q)$(MAKE) $(modbuiltin)=dir
|
2014-09-09 11:03:58 +00:00
|
|
|
modbuiltin := -f $(srctree)/scripts/Makefile.modbuiltin obj
|
2009-12-07 15:38:33 +00:00
|
|
|
|
2014-09-03 13:29:24 +00:00
|
|
|
###
|
|
|
|
|
# Shorthand for $(Q)$(MAKE) -f scripts/Makefile.dtbinst obj=
|
|
|
|
|
# Usage:
|
|
|
|
|
# $(Q)$(MAKE) $(dtbinst)=dir
|
|
|
|
|
dtbinst := -f $(if $(KBUILD_SRC),$(srctree)/)scripts/Makefile.dtbinst obj
|
|
|
|
|
|
2014-11-26 10:31:13 +00:00
|
|
|
###
|
|
|
|
|
# Shorthand for $(Q)$(MAKE) -f scripts/Makefile.clean obj=
|
|
|
|
|
# Usage:
|
|
|
|
|
# $(Q)$(MAKE) $(clean)=dir
|
|
|
|
|
clean := -f $(srctree)/scripts/Makefile.clean obj
|
|
|
|
|
|
|
|
|
|
###
|
2014-12-02 04:30:46 +00:00
|
|
|
# Shorthand for $(Q)$(MAKE) -f scripts/Makefile.headersinst obj=
|
2014-11-26 10:31:13 +00:00
|
|
|
# Usage:
|
|
|
|
|
# $(Q)$(MAKE) $(hdr-inst)=dir
|
2014-12-02 04:30:46 +00:00
|
|
|
hdr-inst := -f $(srctree)/scripts/Makefile.headersinst obj
|
2014-11-26 10:31:13 +00:00
|
|
|
|
2007-02-08 21:48:51 +00:00
|
|
|
# Prefix -I with $(srctree) if it is not an absolute path.
|
2008-12-03 20:22:21 +00:00
|
|
|
# skip if -I has no parameter
|
|
|
|
|
addtree = $(if $(patsubst -I%,%,$(1)), \
|
2016-06-15 15:45:47 +00:00
|
|
|
$(if $(filter-out -I/% -I./% -I../%,$(1)),$(patsubst -I%,-I$(srctree)/%,$(1)),$(1)))
|
2007-02-06 01:18:21 +00:00
|
|
|
|
2006-04-07 06:36:49 +00:00
|
|
|
# Find all -I options and call addtree
|
2007-02-08 21:48:51 +00:00
|
|
|
flags = $(foreach o,$($(1)),$(if $(filter -I%,$(o)),$(call addtree,$(o)),$(o)))
|
2006-04-07 06:36:49 +00:00
|
|
|
|
2007-02-06 01:18:21 +00:00
|
|
|
# echo command.
|
|
|
|
|
# Short version is used, if $(quiet) equals `quiet_', otherwise full one.
|
2007-02-07 22:04:35 +00:00
|
|
|
echo-cmd = $(if $($(quiet)cmd_$(1)),\
|
2007-02-06 01:18:21 +00:00
|
|
|
echo ' $(call escsq,$($(quiet)cmd_$(1)))$(echo-why)';)
|
|
|
|
|
|
|
|
|
|
# printing commands
|
2006-01-30 09:04:27 +00:00
|
|
|
cmd = @$(echo-cmd) $(cmd_$(1))
|
2005-07-25 20:10:36 +00:00
|
|
|
|
2007-02-06 01:18:21 +00:00
|
|
|
# Add $(obj)/ for paths that are not absolute
|
2007-02-07 22:04:35 +00:00
|
|
|
objectify = $(foreach o,$(1),$(if $(filter /%,$(o)),$(o),$(obj)/$(o)))
|
2005-09-10 19:02:11 +00:00
|
|
|
|
2005-07-25 20:10:36 +00:00
|
|
|
###
|
2007-02-06 01:18:21 +00:00
|
|
|
# if_changed - execute command if any prerequisite is newer than
|
2005-07-25 20:10:36 +00:00
|
|
|
# target, or command line has changed
|
|
|
|
|
# if_changed_dep - as if_changed, but uses fixdep to reveal dependencies
|
|
|
|
|
# including used config symbols
|
|
|
|
|
# if_changed_rule - as if_changed but execute rule instead
|
|
|
|
|
# See Documentation/kbuild/makefiles.txt for more info
|
|
|
|
|
|
|
|
|
|
ifneq ($(KBUILD_NOCMDDEP),1)
|
kbuild: fix if_change and friends to consider argument order
Currently, arg-check is implemented as follows:
arg-check = $(strip $(filter-out $(cmd_$(1)), $(cmd_$@)) \
$(filter-out $(cmd_$@), $(cmd_$(1))) )
This does not care about the order of arguments that appear in
$(cmd_$(1)) and $(cmd_$@). So, if_changed and friends never rebuild
the target if only the argument order is changed. This is a problem
when the link order is changed.
Apparently,
obj-y += foo.o
obj-y += bar.o
and
obj-y += bar.o
obj-y += foo.o
should be distinguished because the link order determines the probe
order of drivers. So, built-in.o should be rebuilt when the order
of objects is changed.
This commit fixes arg-check to compare the old/current commands
including the argument order.
Of course, this change has a side effect; Kbuild will react to the
change of compile option order. For example, "-DFOO -DBAR" and
"-DBAR -DFOO" should give no difference to the build result, but
false positive should be better than false negative.
I am moving space_escape to the top of Kbuild.include just for a
matter of preference. In practical terms, space_escape can be
defined after arg-check because arg-check uses "=" flavor, not ":=".
Having said that, collecting convenient variables in one place makes
sense from the point of readability.
Chaining "%%%SPACE%%%" to "_-_SPACE_-_" is also a matter of taste
at this point. Actually, it can be arbitrary as long as it is an
unlikely used string. The only problem I see in "%%%SPACE%%%" is
that "%" is a special character in "$(patsubst ...)" context. This
commit just uses "$(subst ...)" for arg-check, but I am fixing it now
in case we might want to use it in $(patsubst ...) context in the
future.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Michal Marek <mmarek@suse.com>
2016-05-07 06:48:26 +00:00
|
|
|
# Check if both arguments are the same including their order. Result is empty
|
|
|
|
|
# string if equal. User may override this check using make KBUILD_NOCMDDEP=1
|
|
|
|
|
arg-check = $(filter-out $(subst $(space),$(space_escape),$(strip $(cmd_$@))), \
|
|
|
|
|
$(subst $(space),$(space_escape),$(strip $(cmd_$1))))
|
2011-05-16 14:37:34 +00:00
|
|
|
else
|
|
|
|
|
arg-check = $(if $(strip $(cmd_$@)),,1)
|
2005-07-25 20:10:36 +00:00
|
|
|
endif
|
|
|
|
|
|
2014-08-07 19:39:57 +00:00
|
|
|
# Replace >$< with >$$< to preserve $ when reloading the .cmd file
|
|
|
|
|
# (needed for make)
|
Kbuild: fix # escaping in .cmd files for future Make
I tried building using a freshly built Make (4.2.1-69-g8a731d1), but
already the objtool build broke with
orc_dump.c: In function ‘orc_dump’:
orc_dump.c:106:2: error: ‘elf_getshnum’ is deprecated [-Werror=deprecated-declarations]
if (elf_getshdrnum(elf, &nr_sections)) {
Turns out that with that new Make, the backslash was not removed, so cpp
didn't see a #include directive, grep found nothing, and
-DLIBELF_USE_DEPRECATED was wrongly put in CFLAGS.
Now, that new Make behaviour is documented in their NEWS file:
* WARNING: Backward-incompatibility!
Number signs (#) appearing inside a macro reference or function invocation
no longer introduce comments and should not be escaped with backslashes:
thus a call such as:
foo := $(shell echo '#')
is legal. Previously the number sign needed to be escaped, for example:
foo := $(shell echo '\#')
Now this latter will resolve to "\#". If you want to write makefiles
portable to both versions, assign the number sign to a variable:
C := \#
foo := $(shell echo '$C')
This was claimed to be fixed in 3.81, but wasn't, for some reason.
To detect this change search for 'nocomment' in the .FEATURES variable.
This also fixes up the two make-cmd instances to replace # with $(pound)
rather than with \#. There might very well be other places that need
similar fixup in preparation for whatever future Make release contains
the above change, but at least this builds an x86_64 defconfig with the
new make.
Link: https://bugzilla.kernel.org/show_bug.cgi?id=197847
Cc: Randy Dunlap <rdunlap@infradead.org>
Signed-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-04-08 21:35:28 +00:00
|
|
|
# Replace >#< with >$(pound)< to avoid starting a comment in the .cmd file
|
2014-08-07 19:39:57 +00:00
|
|
|
# (needed for make)
|
|
|
|
|
# Replace >'< with >'\''< to be able to enclose the whole string in '...'
|
|
|
|
|
# (needed for the shell)
|
Kbuild: fix # escaping in .cmd files for future Make
I tried building using a freshly built Make (4.2.1-69-g8a731d1), but
already the objtool build broke with
orc_dump.c: In function ‘orc_dump’:
orc_dump.c:106:2: error: ‘elf_getshnum’ is deprecated [-Werror=deprecated-declarations]
if (elf_getshdrnum(elf, &nr_sections)) {
Turns out that with that new Make, the backslash was not removed, so cpp
didn't see a #include directive, grep found nothing, and
-DLIBELF_USE_DEPRECATED was wrongly put in CFLAGS.
Now, that new Make behaviour is documented in their NEWS file:
* WARNING: Backward-incompatibility!
Number signs (#) appearing inside a macro reference or function invocation
no longer introduce comments and should not be escaped with backslashes:
thus a call such as:
foo := $(shell echo '#')
is legal. Previously the number sign needed to be escaped, for example:
foo := $(shell echo '\#')
Now this latter will resolve to "\#". If you want to write makefiles
portable to both versions, assign the number sign to a variable:
C := \#
foo := $(shell echo '$C')
This was claimed to be fixed in 3.81, but wasn't, for some reason.
To detect this change search for 'nocomment' in the .FEATURES variable.
This also fixes up the two make-cmd instances to replace # with $(pound)
rather than with \#. There might very well be other places that need
similar fixup in preparation for whatever future Make release contains
the above change, but at least this builds an x86_64 defconfig with the
new make.
Link: https://bugzilla.kernel.org/show_bug.cgi?id=197847
Cc: Randy Dunlap <rdunlap@infradead.org>
Signed-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-04-08 21:35:28 +00:00
|
|
|
make-cmd = $(call escsq,$(subst $(pound),$$(pound),$(subst $$,$$$$,$(cmd_$(1)))))
|
2006-01-30 09:04:27 +00:00
|
|
|
|
2006-07-23 17:37:44 +00:00
|
|
|
# Find any prerequisites that is newer than target or that does not exist.
|
|
|
|
|
# PHONY targets skipped in both cases.
|
|
|
|
|
any-prereq = $(filter-out $(PHONY),$?) $(filter-out $(PHONY) $(wildcard $^),$^)
|
|
|
|
|
|
2007-02-06 01:18:21 +00:00
|
|
|
# Execute command if command has changed or prerequisite(s) are updated.
|
2006-07-23 17:37:44 +00:00
|
|
|
if_changed = $(if $(strip $(any-prereq) $(arg-check)), \
|
|
|
|
|
@set -e; \
|
|
|
|
|
$(echo-cmd) $(cmd_$(1)); \
|
kbuild: suppress annoying "... is up to date." message
Under certain conditions, Kbuild shows "... is up to date" where
if_changed or friends are used.
For example, the incremental build of ARM64 Linux shows this message
when the kernel image has not been updated.
$ make ARCH=arm64 CROSS_COMPILE=aarch64-linux-gnu-
CHK include/config/kernel.release
CHK include/generated/uapi/linux/version.h
CHK include/generated/utsrelease.h
CHK include/generated/bounds.h
CHK include/generated/timeconst.h
CHK include/generated/asm-offsets.h
CALL scripts/checksyscalls.sh
CHK include/generated/compile.h
CHK kernel/config_data.h
make[1]: `arch/arm64/boot/Image.gz' is up to date.
Building modules, stage 2.
MODPOST 0 modules
The following is the build rule in arch/arm64/boot/Makefile:
$(obj)/Image.gz: $(obj)/Image FORCE
$(call if_changed,gzip)
If the Image.gz is newer than the Image and the command line has not
changed (i.e., $(any-prereq) and $(arg-check) are both empty), the
build rule $(call if_changed,gzip) is evaluated to be empty, then
GNU Make reports the target is up to date. In order to make GNU Make
quiet, we need to give it something to do, for example, "@:". This
should be fixed in the Kbuild core part rather than in each Makefile.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Michal Marek <mmarek@suse.com>
2016-03-03 08:36:30 +00:00
|
|
|
printf '%s\n' 'cmd_$@ := $(make-cmd)' > $(dot-target).cmd, @:)
|
2005-07-25 20:10:36 +00:00
|
|
|
|
2007-02-06 01:18:21 +00:00
|
|
|
# Execute the command and also postprocess generated .d dependencies file.
|
2006-07-23 17:37:44 +00:00
|
|
|
if_changed_dep = $(if $(strip $(any-prereq) $(arg-check) ), \
|
|
|
|
|
@set -e; \
|
2016-02-17 20:50:06 +00:00
|
|
|
$(cmd_and_fixdep), @:)
|
|
|
|
|
|
kbuild: add fine grained build dependencies for exported symbols
Like with kconfig options, we now have the ability to compile in and
out individual EXPORT_SYMBOL() declarations based on the content of
include/generated/autoksyms.h. However we don't want the entire
world to be rebuilt whenever that file is touched.
Let's apply the same build dependency trick used for CONFIG_* symbols
where the time stamp of empty files whose paths matching those symbols
is used to trigger fine grained rebuilds. In our case the key is the
symbol name passed to EXPORT_SYMBOL().
However, unlike config options, we cannot just use fixdep to parse
the source code for EXPORT_SYMBOL(ksym) because several variants exist
and parsing them all in a separate tool, and keeping it in synch, is
not trivially maintainable. Furthermore, there are variants such as
EXPORT_SYMBOL_GPL(pci_user_read_config_##size);
that are instanciated via a macro for which we can't easily determine
the actual exported symbol name(s) short of actually running the
preprocessor on them.
Storing the symbol name string in a special ELF section doesn't work
for targets that output assembly or preprocessed source.
So the best way is really to leverage the preprocessor by having it
output actual symbol names anchored by a special sequence that can be
easily filtered out. Then the list of symbols is simply fed to fixdep
to be merged with the other dependencies.
That implies the preprocessor is executed twice for each source file.
A previous attempt relied on a warning pragma for each EXPORT_SYMBOL()
instance that was filtered apart from stderr by the build system with
a sed script during the actual compilation pass. Unfortunately the
preprocessor/compiler diagnostic output isn't stable between versions
and this solution, although more efficient, was deemed too fragile.
Because of the lowercasing performed by fixdep, there might be name
collisions triggering spurious rebuilds for similar symbols. But this
shouldn't be a big issue in practice. (This is the case for CONFIG_*
symbols and I didn't want to be different here, whatever the original
reason for doing so.)
To avoid needless build overhead, the exported symbol name gathering is
performed only when CONFIG_TRIM_UNUSED_KSYMS is selected.
Signed-off-by: Nicolas Pitre <nico@linaro.org>
Acked-by: Rusty Russell <rusty@rustcorp.com.au>
2016-01-22 18:41:57 +00:00
|
|
|
ifndef CONFIG_TRIM_UNUSED_KSYMS
|
|
|
|
|
|
2016-02-17 20:50:06 +00:00
|
|
|
cmd_and_fixdep = \
|
2006-07-23 17:37:44 +00:00
|
|
|
$(echo-cmd) $(cmd_$(1)); \
|
|
|
|
|
scripts/basic/fixdep $(depfile) $@ '$(make-cmd)' > $(dot-target).tmp;\
|
|
|
|
|
rm -f $(depfile); \
|
2016-02-17 20:50:06 +00:00
|
|
|
mv -f $(dot-target).tmp $(dot-target).cmd;
|
2005-07-25 20:10:36 +00:00
|
|
|
|
kbuild: add fine grained build dependencies for exported symbols
Like with kconfig options, we now have the ability to compile in and
out individual EXPORT_SYMBOL() declarations based on the content of
include/generated/autoksyms.h. However we don't want the entire
world to be rebuilt whenever that file is touched.
Let's apply the same build dependency trick used for CONFIG_* symbols
where the time stamp of empty files whose paths matching those symbols
is used to trigger fine grained rebuilds. In our case the key is the
symbol name passed to EXPORT_SYMBOL().
However, unlike config options, we cannot just use fixdep to parse
the source code for EXPORT_SYMBOL(ksym) because several variants exist
and parsing them all in a separate tool, and keeping it in synch, is
not trivially maintainable. Furthermore, there are variants such as
EXPORT_SYMBOL_GPL(pci_user_read_config_##size);
that are instanciated via a macro for which we can't easily determine
the actual exported symbol name(s) short of actually running the
preprocessor on them.
Storing the symbol name string in a special ELF section doesn't work
for targets that output assembly or preprocessed source.
So the best way is really to leverage the preprocessor by having it
output actual symbol names anchored by a special sequence that can be
easily filtered out. Then the list of symbols is simply fed to fixdep
to be merged with the other dependencies.
That implies the preprocessor is executed twice for each source file.
A previous attempt relied on a warning pragma for each EXPORT_SYMBOL()
instance that was filtered apart from stderr by the build system with
a sed script during the actual compilation pass. Unfortunately the
preprocessor/compiler diagnostic output isn't stable between versions
and this solution, although more efficient, was deemed too fragile.
Because of the lowercasing performed by fixdep, there might be name
collisions triggering spurious rebuilds for similar symbols. But this
shouldn't be a big issue in practice. (This is the case for CONFIG_*
symbols and I didn't want to be different here, whatever the original
reason for doing so.)
To avoid needless build overhead, the exported symbol name gathering is
performed only when CONFIG_TRIM_UNUSED_KSYMS is selected.
Signed-off-by: Nicolas Pitre <nico@linaro.org>
Acked-by: Rusty Russell <rusty@rustcorp.com.au>
2016-01-22 18:41:57 +00:00
|
|
|
else
|
|
|
|
|
|
|
|
|
|
# Filter out exported kernel symbol names from the preprocessor output.
|
|
|
|
|
# See also __KSYM_DEPS__ in include/linux/export.h.
|
|
|
|
|
# We disable the depfile generation here, so as not to overwrite the existing
|
|
|
|
|
# depfile while fixdep is parsing it.
|
|
|
|
|
flags_nodeps = $(filter-out -Wp$(comma)-M%, $($(1)))
|
|
|
|
|
ksym_dep_filter = \
|
|
|
|
|
case "$(1)" in \
|
2016-04-26 15:21:34 +00:00
|
|
|
cc_*_c|cpp_i_c) \
|
|
|
|
|
$(CPP) $(call flags_nodeps,c_flags) -D__KSYM_DEPS__ $< ;; \
|
|
|
|
|
as_*_S|cpp_s_S) \
|
|
|
|
|
$(CPP) $(call flags_nodeps,a_flags) -D__KSYM_DEPS__ $< ;; \
|
2017-02-13 10:15:56 +00:00
|
|
|
boot*|build*|cpp_its_S|*cpp_lds_S|dtc|host*|vdso*) : ;; \
|
2016-04-26 15:21:34 +00:00
|
|
|
*) echo "Don't know how to preprocess $(1)" >&2; false ;; \
|
2018-03-16 07:37:14 +00:00
|
|
|
esac | tr ";" "\n" | sed -n 's/^.*=== __KSYM_\(.*\) ===.*$$/_\1/p'
|
kbuild: add fine grained build dependencies for exported symbols
Like with kconfig options, we now have the ability to compile in and
out individual EXPORT_SYMBOL() declarations based on the content of
include/generated/autoksyms.h. However we don't want the entire
world to be rebuilt whenever that file is touched.
Let's apply the same build dependency trick used for CONFIG_* symbols
where the time stamp of empty files whose paths matching those symbols
is used to trigger fine grained rebuilds. In our case the key is the
symbol name passed to EXPORT_SYMBOL().
However, unlike config options, we cannot just use fixdep to parse
the source code for EXPORT_SYMBOL(ksym) because several variants exist
and parsing them all in a separate tool, and keeping it in synch, is
not trivially maintainable. Furthermore, there are variants such as
EXPORT_SYMBOL_GPL(pci_user_read_config_##size);
that are instanciated via a macro for which we can't easily determine
the actual exported symbol name(s) short of actually running the
preprocessor on them.
Storing the symbol name string in a special ELF section doesn't work
for targets that output assembly or preprocessed source.
So the best way is really to leverage the preprocessor by having it
output actual symbol names anchored by a special sequence that can be
easily filtered out. Then the list of symbols is simply fed to fixdep
to be merged with the other dependencies.
That implies the preprocessor is executed twice for each source file.
A previous attempt relied on a warning pragma for each EXPORT_SYMBOL()
instance that was filtered apart from stderr by the build system with
a sed script during the actual compilation pass. Unfortunately the
preprocessor/compiler diagnostic output isn't stable between versions
and this solution, although more efficient, was deemed too fragile.
Because of the lowercasing performed by fixdep, there might be name
collisions triggering spurious rebuilds for similar symbols. But this
shouldn't be a big issue in practice. (This is the case for CONFIG_*
symbols and I didn't want to be different here, whatever the original
reason for doing so.)
To avoid needless build overhead, the exported symbol name gathering is
performed only when CONFIG_TRIM_UNUSED_KSYMS is selected.
Signed-off-by: Nicolas Pitre <nico@linaro.org>
Acked-by: Rusty Russell <rusty@rustcorp.com.au>
2016-01-22 18:41:57 +00:00
|
|
|
|
|
|
|
|
cmd_and_fixdep = \
|
|
|
|
|
$(echo-cmd) $(cmd_$(1)); \
|
|
|
|
|
$(ksym_dep_filter) | \
|
|
|
|
|
scripts/basic/fixdep -e $(depfile) $@ '$(make-cmd)' \
|
|
|
|
|
> $(dot-target).tmp; \
|
|
|
|
|
rm -f $(depfile); \
|
|
|
|
|
mv -f $(dot-target).tmp $(dot-target).cmd;
|
|
|
|
|
|
|
|
|
|
endif
|
|
|
|
|
|
2005-07-25 20:10:36 +00:00
|
|
|
# Usage: $(call if_changed_rule,foo)
|
2007-02-08 21:48:51 +00:00
|
|
|
# Will check if $(cmd_foo) or any of the prerequisites changed,
|
|
|
|
|
# and if so will execute $(rule_foo).
|
2006-07-23 17:37:44 +00:00
|
|
|
if_changed_rule = $(if $(strip $(any-prereq) $(arg-check) ), \
|
|
|
|
|
@set -e; \
|
kbuild: suppress annoying "... is up to date." message
Under certain conditions, Kbuild shows "... is up to date" where
if_changed or friends are used.
For example, the incremental build of ARM64 Linux shows this message
when the kernel image has not been updated.
$ make ARCH=arm64 CROSS_COMPILE=aarch64-linux-gnu-
CHK include/config/kernel.release
CHK include/generated/uapi/linux/version.h
CHK include/generated/utsrelease.h
CHK include/generated/bounds.h
CHK include/generated/timeconst.h
CHK include/generated/asm-offsets.h
CALL scripts/checksyscalls.sh
CHK include/generated/compile.h
CHK kernel/config_data.h
make[1]: `arch/arm64/boot/Image.gz' is up to date.
Building modules, stage 2.
MODPOST 0 modules
The following is the build rule in arch/arm64/boot/Makefile:
$(obj)/Image.gz: $(obj)/Image FORCE
$(call if_changed,gzip)
If the Image.gz is newer than the Image and the command line has not
changed (i.e., $(any-prereq) and $(arg-check) are both empty), the
build rule $(call if_changed,gzip) is evaluated to be empty, then
GNU Make reports the target is up to date. In order to make GNU Make
quiet, we need to give it something to do, for example, "@:". This
should be fixed in the Kbuild core part rather than in each Makefile.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Michal Marek <mmarek@suse.com>
2016-03-03 08:36:30 +00:00
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$(rule_$(1)), @:)
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2006-07-23 17:37:44 +00:00
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2006-08-08 19:35:14 +00:00
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###
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2017-08-02 02:31:06 +00:00
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# why - tell why a target got built
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2006-08-08 19:35:14 +00:00
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# enabled by make V=2
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# Output (listed in the order they are checked):
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# (1) - due to target is PHONY
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# (2) - due to target missing
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# (3) - due to: file1.h file2.h
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# (4) - due to command line change
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# (5) - due to missing .cmd file
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# (6) - due to target not in $(targets)
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# (1) PHONY targets are always build
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# (2) No target, so we better build it
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# (3) Prerequisite is newer than target
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# (4) The command line stored in the file named dir/.target.cmd
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# differed from actual command line. This happens when compiler
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# options changes
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# (5) No dir/.target.cmd file (used to store command line)
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# (6) No dir/.target.cmd file and target not listed in $(targets)
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# This is a good hint that there is a bug in the kbuild file
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ifeq ($(KBUILD_VERBOSE),2)
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why = \
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$(if $(filter $@, $(PHONY)),- due to target is PHONY, \
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$(if $(wildcard $@), \
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$(if $(strip $(any-prereq)),- due to: $(any-prereq), \
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$(if $(arg-check), \
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$(if $(cmd_$@),- due to command line change, \
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$(if $(filter $@, $(targets)), \
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- due to missing .cmd file, \
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- due to $(notdir $@) not in $$(targets) \
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) \
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) \
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) \
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), \
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- due to target missing \
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) \
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)
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echo-why = $(call escsq, $(strip $(why)))
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endif
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2015-08-14 15:17:16 +00:00
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###############################################################################
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#
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# When a Kconfig string contains a filename, it is suitable for
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# passing to shell commands. It is surrounded by double-quotes, and
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# any double-quotes or backslashes within it are escaped by
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# backslashes.
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#
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# This is no use for dependencies or $(wildcard). We need to strip the
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# surrounding quotes and the escaping from quotes and backslashes, and
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# we *do* need to escape any spaces in the string. So, for example:
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#
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# Usage: $(eval $(call config_filename,FOO))
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#
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# Defines FOO_FILENAME based on the contents of the CONFIG_FOO option,
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# transformed as described above to be suitable for use within the
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# makefile.
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#
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# Also, if the filename is a relative filename and exists in the source
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# tree but not the build tree, define FOO_SRCPREFIX as $(srctree)/ to
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# be prefixed to *both* command invocation and dependencies.
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#
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# Note: We also print the filenames in the quiet_cmd_foo text, and
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# perhaps ought to have a version specially escaped for that purpose.
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# But it's only cosmetic, and $(patsubst "%",%,$(CONFIG_FOO)) is good
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# enough. It'll strip the quotes in the common case where there's no
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# space and it's a simple filename, and it'll retain the quotes when
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# there's a space. There are some esoteric cases in which it'll print
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# the wrong thing, but we don't really care. The actual dependencies
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# and commands *do* get it right, with various combinations of single
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# and double quotes, backslashes and spaces in the filenames.
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#
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###############################################################################
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#
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define config_filename
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ifneq ($$(CONFIG_$(1)),"")
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$(1)_FILENAME := $$(subst \\,\,$$(subst \$$(quote),$$(quote),$$(subst $$(space_escape),\$$(space),$$(patsubst "%",%,$$(subst $$(space),$$(space_escape),$$(CONFIG_$(1)))))))
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ifneq ($$(patsubst /%,%,$$(firstword $$($(1)_FILENAME))),$$(firstword $$($(1)_FILENAME)))
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else
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ifeq ($$(wildcard $$($(1)_FILENAME)),)
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ifneq ($$(wildcard $$(srctree)/$$($(1)_FILENAME)),)
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$(1)_SRCPREFIX := $(srctree)/
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endif
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endif
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endif
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endif
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endef
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#
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###############################################################################
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