2009-02-05 05:18:13 +00:00
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/**
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* AMCC SoC PPC4xx Crypto Driver
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*
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* Copyright (c) 2008 Applied Micro Circuits Corporation.
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* All rights reserved. James Hsiao <jhsiao@amcc.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* This is the header file for AMCC Crypto offload Linux device driver for
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* use with Linux CryptoAPI.
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*/
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#ifndef __CRYPTO4XX_CORE_H__
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#define __CRYPTO4XX_CORE_H__
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2009-07-14 12:21:46 +00:00
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#include <crypto/internal/hash.h>
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2017-08-25 13:47:25 +00:00
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#include "crypto4xx_reg_def.h"
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#include "crypto4xx_sa.h"
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2009-07-14 12:21:46 +00:00
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2016-04-18 10:57:41 +00:00
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#define MODULE_NAME "crypto4xx"
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2009-02-05 05:18:13 +00:00
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#define PPC460SX_SDR0_SRST 0x201
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#define PPC405EX_SDR0_SRST 0x200
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#define PPC460EX_SDR0_SRST 0x201
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#define PPC460EX_CE_RESET 0x08000000
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#define PPC460SX_CE_RESET 0x20000000
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#define PPC405EX_CE_RESET 0x00000008
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#define CRYPTO4XX_CRYPTO_PRIORITY 300
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2017-10-03 23:00:08 +00:00
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#define PPC4XX_NUM_PD 256
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#define PPC4XX_LAST_PD (PPC4XX_NUM_PD - 1)
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2009-02-05 05:18:13 +00:00
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#define PPC4XX_NUM_GD 1024
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2017-10-03 23:00:08 +00:00
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#define PPC4XX_LAST_GD (PPC4XX_NUM_GD - 1)
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#define PPC4XX_NUM_SD 256
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#define PPC4XX_LAST_SD (PPC4XX_NUM_SD - 1)
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2009-02-05 05:18:13 +00:00
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#define PPC4XX_SD_BUFFER_SIZE 2048
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crypto: crypto4xx - add backlog queue support
Previously, If the crypto4xx driver used all available
security contexts, it would simply refuse new requests
with -EAGAIN. CRYPTO_TFM_REQ_MAY_BACKLOG was ignored.
in case of dm-crypt.c's crypt_convert() function this was
causing the following errors to manifest, if the system was
pushed hard enough:
| EXT4-fs warning (dm-1): ext4_end_bio:314: I/O error -5 writing to ino ..
| EXT4-fs warning (dm-1): ext4_end_bio:314: I/O error -5 writing to ino ..
| EXT4-fs warning (dm-1): ext4_end_bio:314: I/O error -5 writing to ino ..
| JBD2: Detected IO errors while flushing file data on dm-1-8
| Aborting journal on device dm-1-8.
| EXT4-fs error : ext4_journal_check_start:56: Detected aborted journal
| EXT4-fs (dm-1): Remounting filesystem read-only
| EXT4-fs : ext4_writepages: jbd2_start: 2048 pages, inode 498...; err -30
(This did cause corruptions due to failed writes)
To fix this mess, the crypto4xx driver needs to notifiy the
user to slow down. This can be achieved by returning -EBUSY
on requests, once the crypto hardware was falling behind.
Note: -EBUSY has two different meanings. Setting the flag
CRYPTO_TFM_REQ_MAY_BACKLOG implies that the request was
successfully queued, by the crypto driver. To achieve this
requirement, the implementation introduces a threshold check and
adds logic to the completion routines in much the same way as
AMD's Cryptographic Coprocessor (CCP) driver do.
Note2: Tests showed that dm-crypt starved ipsec traffic.
Under load, ipsec links dropped to 0 Kbits/s. This is because
dm-crypt's callback would instantly queue the next request.
In order to not starve ipsec, the driver reserves a small
portion of the available crypto contexts for this purpose.
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2017-10-03 23:00:09 +00:00
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#define PD_ENTRY_BUSY BIT(1)
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#define PD_ENTRY_INUSE BIT(0)
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2009-02-05 05:18:13 +00:00
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#define PD_ENTRY_FREE 0
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#define ERING_WAS_FULL 0xffffffff
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struct crypto4xx_device;
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2017-08-25 13:47:25 +00:00
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union shadow_sa_buf {
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struct dynamic_sa_ctl sa;
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/* alloc 256 bytes which is enough for any kind of dynamic sa */
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u8 buf[256];
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} __packed;
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2009-02-05 05:18:13 +00:00
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struct pd_uinfo {
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struct crypto4xx_device *dev;
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u32 state;
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u32 using_sd;
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u32 first_gd; /* first gather discriptor
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used by this packet */
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u32 num_gd; /* number of gather discriptor
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used by this packet */
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u32 first_sd; /* first scatter discriptor
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used by this packet */
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u32 num_sd; /* number of scatter discriptors
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used by this packet */
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2017-08-25 13:47:25 +00:00
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struct dynamic_sa_ctl *sa_va; /* shadow sa */
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2009-02-05 05:18:13 +00:00
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u32 sa_pa;
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2017-08-25 13:47:25 +00:00
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struct sa_state_record *sr_va; /* state record for shadow sa */
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2009-02-05 05:18:13 +00:00
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u32 sr_pa;
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struct scatterlist *dest_va;
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struct crypto_async_request *async_req; /* base crypto request
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for this packet */
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};
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struct crypto4xx_device {
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struct crypto4xx_core_device *core_dev;
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char *name;
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void __iomem *ce_base;
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2016-04-18 10:57:41 +00:00
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void __iomem *trng_base;
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2009-02-05 05:18:13 +00:00
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2017-08-25 13:47:25 +00:00
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struct ce_pd *pdr; /* base address of packet descriptor ring */
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dma_addr_t pdr_pa; /* physical address of pdr_base_register */
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struct ce_gd *gdr; /* gather descriptor ring */
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dma_addr_t gdr_pa; /* physical address of gdr_base_register */
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struct ce_sd *sdr; /* scatter descriptor ring */
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dma_addr_t sdr_pa; /* physical address of sdr_base_register */
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2009-02-05 05:18:13 +00:00
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void *scatter_buffer_va;
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dma_addr_t scatter_buffer_pa;
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2017-08-25 13:47:25 +00:00
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union shadow_sa_buf *shadow_sa_pool;
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2009-02-05 05:18:13 +00:00
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dma_addr_t shadow_sa_pool_pa;
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2017-08-25 13:47:25 +00:00
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struct sa_state_record *shadow_sr_pool;
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2009-02-05 05:18:13 +00:00
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dma_addr_t shadow_sr_pool_pa;
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u32 pdr_tail;
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u32 pdr_head;
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u32 gdr_tail;
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u32 gdr_head;
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u32 sdr_tail;
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u32 sdr_head;
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2017-08-25 13:47:25 +00:00
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struct pd_uinfo *pdr_uinfo;
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2009-02-05 05:18:13 +00:00
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struct list_head alg_list; /* List of algorithm supported
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by this device */
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};
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struct crypto4xx_core_device {
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struct device *device;
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2010-08-06 15:25:50 +00:00
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struct platform_device *ofdev;
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2009-02-05 05:18:13 +00:00
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struct crypto4xx_device *dev;
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2016-04-18 10:57:41 +00:00
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struct hwrng *trng;
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2009-02-05 05:18:13 +00:00
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u32 int_status;
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u32 irq;
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struct tasklet_struct tasklet;
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spinlock_t lock;
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};
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struct crypto4xx_ctx {
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struct crypto4xx_device *dev;
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2017-08-25 13:47:25 +00:00
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struct dynamic_sa_ctl *sa_in;
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2009-02-05 05:18:13 +00:00
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dma_addr_t sa_in_dma_addr;
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2017-08-25 13:47:25 +00:00
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struct dynamic_sa_ctl *sa_out;
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2009-02-05 05:18:13 +00:00
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dma_addr_t sa_out_dma_addr;
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2017-08-25 13:47:25 +00:00
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struct sa_state_record *state_record;
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2009-02-05 05:18:13 +00:00
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dma_addr_t state_record_dma_addr;
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u32 sa_len;
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u32 offset_to_sr_ptr; /* offset to state ptr, in dynamic sa */
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u32 direction;
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u32 save_iv;
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u32 pd_ctl;
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u32 is_hash;
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};
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2009-07-14 12:21:46 +00:00
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struct crypto4xx_alg_common {
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u32 type;
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union {
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struct crypto_alg cipher;
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struct ahash_alg hash;
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} u;
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};
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2009-02-05 05:18:13 +00:00
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struct crypto4xx_alg {
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struct list_head entry;
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2009-07-14 12:21:46 +00:00
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struct crypto4xx_alg_common alg;
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2009-02-05 05:18:13 +00:00
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struct crypto4xx_device *dev;
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};
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2009-07-14 12:21:46 +00:00
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static inline struct crypto4xx_alg *crypto_alg_to_crypto4xx_alg(
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struct crypto_alg *x)
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{
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switch (x->cra_flags & CRYPTO_ALG_TYPE_MASK) {
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case CRYPTO_ALG_TYPE_AHASH:
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return container_of(__crypto_ahash_alg(x),
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struct crypto4xx_alg, alg.u.hash);
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}
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return container_of(x, struct crypto4xx_alg, alg.u.cipher);
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}
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2009-02-05 05:18:13 +00:00
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2017-08-25 13:47:17 +00:00
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int crypto4xx_alloc_sa(struct crypto4xx_ctx *ctx, u32 size);
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void crypto4xx_free_sa(struct crypto4xx_ctx *ctx);
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void crypto4xx_free_ctx(struct crypto4xx_ctx *ctx);
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u32 crypto4xx_alloc_state_record(struct crypto4xx_ctx *ctx);
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2017-10-03 23:00:10 +00:00
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int crypto4xx_build_pd(struct crypto_async_request *req,
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2017-08-25 13:47:17 +00:00
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struct crypto4xx_ctx *ctx,
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struct scatterlist *src,
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struct scatterlist *dst,
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unsigned int datalen,
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void *iv, u32 iv_len);
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int crypto4xx_setkey_aes_cbc(struct crypto_ablkcipher *cipher,
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const u8 *key, unsigned int keylen);
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2017-08-25 13:47:21 +00:00
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int crypto4xx_setkey_aes_cfb(struct crypto_ablkcipher *cipher,
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const u8 *key, unsigned int keylen);
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int crypto4xx_setkey_aes_ecb(struct crypto_ablkcipher *cipher,
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const u8 *key, unsigned int keylen);
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int crypto4xx_setkey_aes_ofb(struct crypto_ablkcipher *cipher,
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const u8 *key, unsigned int keylen);
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int crypto4xx_setkey_rfc3686(struct crypto_ablkcipher *cipher,
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const u8 *key, unsigned int keylen);
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2017-08-25 13:47:17 +00:00
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int crypto4xx_encrypt(struct ablkcipher_request *req);
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int crypto4xx_decrypt(struct ablkcipher_request *req);
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2017-08-25 13:47:21 +00:00
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int crypto4xx_rfc3686_encrypt(struct ablkcipher_request *req);
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int crypto4xx_rfc3686_decrypt(struct ablkcipher_request *req);
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2017-08-25 13:47:17 +00:00
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int crypto4xx_sha1_alg_init(struct crypto_tfm *tfm);
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int crypto4xx_hash_digest(struct ahash_request *req);
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int crypto4xx_hash_final(struct ahash_request *req);
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int crypto4xx_hash_update(struct ahash_request *req);
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int crypto4xx_hash_init(struct ahash_request *req);
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2017-10-03 23:00:10 +00:00
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/**
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* Note: Only use this function to copy items that is word aligned.
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*/
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static inline void crypto4xx_memcpy_swab32(u32 *dst, const void *buf,
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size_t len)
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{
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for (; len >= 4; buf += 4, len -= 4)
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*dst++ = __swab32p((u32 *) buf);
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if (len) {
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const u8 *tmp = (u8 *)buf;
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switch (len) {
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case 3:
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*dst = (tmp[2] << 16) |
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(tmp[1] << 8) |
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tmp[0];
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break;
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case 2:
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*dst = (tmp[1] << 8) |
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tmp[0];
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break;
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case 1:
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*dst = tmp[0];
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break;
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default:
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break;
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}
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}
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}
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static inline void crypto4xx_memcpy_from_le32(u32 *dst, const void *buf,
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size_t len)
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{
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crypto4xx_memcpy_swab32(dst, buf, len);
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}
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static inline void crypto4xx_memcpy_to_le32(__le32 *dst, const void *buf,
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size_t len)
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{
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crypto4xx_memcpy_swab32((u32 *)dst, buf, len);
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}
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2009-02-05 05:18:13 +00:00
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#endif
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