2016-07-13 15:03:40 +00:00
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/*
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* Copyright © 2016 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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*/
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#include "i915_drv.h"
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#include "intel_ringbuffer.h"
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#include "intel_lrc.h"
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static const struct engine_info {
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const char *name;
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unsigned exec_id;
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2016-08-16 16:04:20 +00:00
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enum intel_engine_hw_id hw_id;
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2016-07-13 15:03:40 +00:00
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u32 mmio_base;
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unsigned irq_shift;
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int (*init_legacy)(struct intel_engine_cs *engine);
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int (*init_execlists)(struct intel_engine_cs *engine);
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} intel_engines[] = {
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[RCS] = {
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.name = "render ring",
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.exec_id = I915_EXEC_RENDER,
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2016-08-16 16:04:20 +00:00
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.hw_id = RCS_HW,
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2016-07-13 15:03:40 +00:00
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.mmio_base = RENDER_RING_BASE,
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.irq_shift = GEN8_RCS_IRQ_SHIFT,
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.init_execlists = logical_render_ring_init,
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.init_legacy = intel_init_render_ring_buffer,
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},
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[BCS] = {
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.name = "blitter ring",
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.exec_id = I915_EXEC_BLT,
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2016-08-16 16:04:20 +00:00
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.hw_id = BCS_HW,
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2016-07-13 15:03:40 +00:00
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.mmio_base = BLT_RING_BASE,
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.irq_shift = GEN8_BCS_IRQ_SHIFT,
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.init_execlists = logical_xcs_ring_init,
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.init_legacy = intel_init_blt_ring_buffer,
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},
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[VCS] = {
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.name = "bsd ring",
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.exec_id = I915_EXEC_BSD,
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2016-08-16 16:04:20 +00:00
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.hw_id = VCS_HW,
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2016-07-13 15:03:40 +00:00
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.mmio_base = GEN6_BSD_RING_BASE,
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.irq_shift = GEN8_VCS1_IRQ_SHIFT,
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.init_execlists = logical_xcs_ring_init,
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.init_legacy = intel_init_bsd_ring_buffer,
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},
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[VCS2] = {
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.name = "bsd2 ring",
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.exec_id = I915_EXEC_BSD,
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2016-08-16 16:04:20 +00:00
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.hw_id = VCS2_HW,
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2016-07-13 15:03:40 +00:00
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.mmio_base = GEN8_BSD2_RING_BASE,
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.irq_shift = GEN8_VCS2_IRQ_SHIFT,
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.init_execlists = logical_xcs_ring_init,
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.init_legacy = intel_init_bsd2_ring_buffer,
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},
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[VECS] = {
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.name = "video enhancement ring",
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.exec_id = I915_EXEC_VEBOX,
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2016-08-16 16:04:20 +00:00
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.hw_id = VECS_HW,
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2016-07-13 15:03:40 +00:00
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.mmio_base = VEBOX_RING_BASE,
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.irq_shift = GEN8_VECS_IRQ_SHIFT,
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.init_execlists = logical_xcs_ring_init,
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.init_legacy = intel_init_vebox_ring_buffer,
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},
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};
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static struct intel_engine_cs *
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intel_engine_setup(struct drm_i915_private *dev_priv,
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enum intel_engine_id id)
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{
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const struct engine_info *info = &intel_engines[id];
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struct intel_engine_cs *engine = &dev_priv->engine[id];
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engine->id = id;
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engine->i915 = dev_priv;
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engine->name = info->name;
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engine->exec_id = info->exec_id;
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2016-08-16 16:04:20 +00:00
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engine->hw_id = engine->guc_id = info->hw_id;
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2016-07-13 15:03:40 +00:00
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engine->mmio_base = info->mmio_base;
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engine->irq_shift = info->irq_shift;
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return engine;
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}
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/**
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* intel_engines_init() - allocate, populate and init the Engine Command Streamers
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* @dev: DRM device.
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*
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* Return: non-zero if the initialization failed.
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*/
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int intel_engines_init(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = to_i915(dev);
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2016-08-10 15:22:10 +00:00
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struct intel_device_info *device_info = mkwrite_device_info(dev_priv);
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2016-07-13 15:03:40 +00:00
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unsigned int mask = 0;
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int (*init)(struct intel_engine_cs *engine);
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unsigned int i;
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int ret;
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2016-07-28 23:45:35 +00:00
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WARN_ON(INTEL_INFO(dev_priv)->ring_mask == 0);
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2016-07-13 15:03:40 +00:00
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WARN_ON(INTEL_INFO(dev_priv)->ring_mask &
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GENMASK(sizeof(mask) * BITS_PER_BYTE - 1, I915_NUM_ENGINES));
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for (i = 0; i < ARRAY_SIZE(intel_engines); i++) {
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if (!HAS_ENGINE(dev_priv, i))
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continue;
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if (i915.enable_execlists)
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init = intel_engines[i].init_execlists;
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else
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init = intel_engines[i].init_legacy;
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if (!init)
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continue;
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ret = init(intel_engine_setup(dev_priv, i));
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if (ret)
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goto cleanup;
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mask |= ENGINE_MASK(i);
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}
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/*
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* Catch failures to update intel_engines table when the new engines
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* are added to the driver by a warning and disabling the forgotten
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* engines.
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*/
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2016-08-10 15:22:10 +00:00
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if (WARN_ON(mask != INTEL_INFO(dev_priv)->ring_mask))
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device_info->ring_mask = mask;
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device_info->num_rings = hweight32(mask);
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2016-07-13 15:03:40 +00:00
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return 0;
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cleanup:
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for (i = 0; i < I915_NUM_ENGINES; i++) {
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if (i915.enable_execlists)
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intel_logical_ring_cleanup(&dev_priv->engine[i]);
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else
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2016-08-02 21:50:21 +00:00
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intel_engine_cleanup(&dev_priv->engine[i]);
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2016-07-13 15:03:40 +00:00
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}
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return ret;
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}
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2016-08-15 09:49:00 +00:00
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void intel_engine_init_seqno(struct intel_engine_cs *engine, u32 seqno)
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{
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struct drm_i915_private *dev_priv = engine->i915;
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/* Our semaphore implementation is strictly monotonic (i.e. we proceed
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* so long as the semaphore value in the register/page is greater
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* than the sync value), so whenever we reset the seqno,
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* so long as we reset the tracking semaphore value to 0, it will
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* always be before the next request's seqno. If we don't reset
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* the semaphore value, then when the seqno moves backwards all
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* future waits will complete instantly (causing rendering corruption).
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*/
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if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) {
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I915_WRITE(RING_SYNC_0(engine->mmio_base), 0);
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I915_WRITE(RING_SYNC_1(engine->mmio_base), 0);
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if (HAS_VEBOX(dev_priv))
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I915_WRITE(RING_SYNC_2(engine->mmio_base), 0);
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}
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2016-08-15 09:49:02 +00:00
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if (dev_priv->semaphore) {
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struct page *page = i915_vma_first_page(dev_priv->semaphore);
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void *semaphores;
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/* Semaphores are in noncoherent memory, flush to be safe */
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semaphores = kmap(page);
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2016-08-15 09:49:00 +00:00
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memset(semaphores + GEN8_SEMAPHORE_OFFSET(engine->id, 0),
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0, I915_NUM_ENGINES * gen8_semaphore_seqno_size);
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2016-08-15 09:49:02 +00:00
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drm_clflush_virt_range(semaphores + GEN8_SEMAPHORE_OFFSET(engine->id, 0),
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I915_NUM_ENGINES * gen8_semaphore_seqno_size);
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2016-08-15 09:49:00 +00:00
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kunmap(page);
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}
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memset(engine->semaphore.sync_seqno, 0,
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sizeof(engine->semaphore.sync_seqno));
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intel_write_status_page(engine, I915_GEM_HWS_INDEX, seqno);
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if (engine->irq_seqno_barrier)
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engine->irq_seqno_barrier(engine);
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engine->last_submitted_seqno = seqno;
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engine->hangcheck.seqno = seqno;
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/* After manually advancing the seqno, fake the interrupt in case
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* there are any waiters for that seqno.
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*/
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intel_engine_wakeup(engine);
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}
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2016-07-13 15:03:41 +00:00
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void intel_engine_init_hangcheck(struct intel_engine_cs *engine)
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{
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memset(&engine->hangcheck, 0, sizeof(engine->hangcheck));
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2016-08-09 16:47:51 +00:00
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clear_bit(engine->id, &engine->i915->gpu_error.missed_irq_rings);
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2016-07-13 15:03:41 +00:00
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}
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2016-08-05 09:14:11 +00:00
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static void intel_engine_init_requests(struct intel_engine_cs *engine)
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{
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init_request_active(&engine->last_request, NULL);
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INIT_LIST_HEAD(&engine->request_list);
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}
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2016-07-13 15:03:41 +00:00
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/**
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* intel_engines_setup_common - setup engine state not requiring hw access
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* @engine: Engine to setup.
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*
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* Initializes @engine@ structure members shared between legacy and execlists
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* submission modes which do not require hardware access.
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*
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* Typically done early in the submission mode specific engine setup stage.
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*/
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void intel_engine_setup_common(struct intel_engine_cs *engine)
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{
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INIT_LIST_HEAD(&engine->buffers);
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INIT_LIST_HEAD(&engine->execlist_queue);
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spin_lock_init(&engine->execlist_lock);
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2016-07-20 08:21:11 +00:00
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engine->fence_context = fence_context_alloc(1);
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2016-08-05 09:14:11 +00:00
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intel_engine_init_requests(engine);
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2016-07-13 15:03:41 +00:00
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intel_engine_init_hangcheck(engine);
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2016-08-04 15:32:19 +00:00
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i915_gem_batch_pool_init(engine, &engine->batch_pool);
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2016-08-18 16:17:10 +00:00
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intel_engine_init_cmd_parser(engine);
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2016-07-13 15:03:41 +00:00
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}
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2016-08-15 09:48:59 +00:00
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int intel_engine_create_scratch(struct intel_engine_cs *engine, int size)
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{
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struct drm_i915_gem_object *obj;
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struct i915_vma *vma;
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int ret;
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WARN_ON(engine->scratch);
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obj = i915_gem_object_create_stolen(&engine->i915->drm, size);
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if (!obj)
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obj = i915_gem_object_create(&engine->i915->drm, size);
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if (IS_ERR(obj)) {
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DRM_ERROR("Failed to allocate scratch page\n");
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return PTR_ERR(obj);
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}
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vma = i915_vma_create(obj, &engine->i915->ggtt.base, NULL);
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if (IS_ERR(vma)) {
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ret = PTR_ERR(vma);
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goto err_unref;
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}
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ret = i915_vma_pin(vma, 0, 4096, PIN_GLOBAL | PIN_HIGH);
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if (ret)
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goto err_unref;
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engine->scratch = vma;
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2016-08-15 09:49:07 +00:00
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DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
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engine->name, i915_ggtt_offset(vma));
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2016-08-15 09:48:59 +00:00
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return 0;
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err_unref:
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i915_gem_object_put(obj);
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return ret;
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}
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static void intel_engine_cleanup_scratch(struct intel_engine_cs *engine)
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{
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2016-08-15 09:49:05 +00:00
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i915_vma_unpin_and_release(&engine->scratch);
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2016-08-15 09:48:59 +00:00
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}
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2016-07-13 15:03:41 +00:00
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/**
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* intel_engines_init_common - initialize cengine state which might require hw access
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* @engine: Engine to initialize.
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*
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* Initializes @engine@ structure members shared between legacy and execlists
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* submission modes which do require hardware access.
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*
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* Typcally done at later stages of submission mode specific engine setup.
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*
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* Returns zero on success or an error code on failure.
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*/
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int intel_engine_init_common(struct intel_engine_cs *engine)
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{
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int ret;
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ret = intel_engine_init_breadcrumbs(engine);
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if (ret)
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return ret;
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2016-08-18 16:17:10 +00:00
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return 0;
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2016-07-13 15:03:41 +00:00
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}
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2016-08-03 12:19:16 +00:00
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/**
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* intel_engines_cleanup_common - cleans up the engine state created by
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* the common initiailizers.
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* @engine: Engine to cleanup.
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*
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* This cleans up everything created by the common helpers.
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*/
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void intel_engine_cleanup_common(struct intel_engine_cs *engine)
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{
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2016-08-15 09:48:59 +00:00
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intel_engine_cleanup_scratch(engine);
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2016-08-03 12:19:16 +00:00
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intel_engine_fini_breadcrumbs(engine);
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2016-08-18 16:17:10 +00:00
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intel_engine_cleanup_cmd_parser(engine);
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2016-08-03 12:19:16 +00:00
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i915_gem_batch_pool_fini(&engine->batch_pool);
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}
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