2016-11-10 14:29:37 +00:00
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/*
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* Copyright (C) 2016 BayLibre, SAS
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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/* Video Clock */
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#ifndef __MESON_VCLK_H
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#define __MESON_VCLK_H
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enum {
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MESON_VCLK_TARGET_CVBS = 0,
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2017-04-04 12:15:25 +00:00
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MESON_VCLK_TARGET_HDMI = 1,
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2018-07-16 07:40:14 +00:00
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MESON_VCLK_TARGET_DMT = 2,
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2016-11-10 14:29:37 +00:00
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};
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/* 27MHz is the CVBS Pixel Clock */
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2017-04-04 12:15:25 +00:00
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#define MESON_VCLK_CVBS 27000
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2016-11-10 14:29:37 +00:00
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2018-07-16 07:40:14 +00:00
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enum drm_mode_status
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meson_vclk_dmt_supported_freq(struct meson_drm *priv, unsigned int freq);
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2018-11-06 10:54:35 +00:00
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enum drm_mode_status
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meson_vclk_vic_supported_freq(unsigned int freq);
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2018-07-16 07:40:14 +00:00
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2016-11-10 14:29:37 +00:00
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void meson_vclk_setup(struct meson_drm *priv, unsigned int target,
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2017-04-04 12:15:25 +00:00
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unsigned int vclk_freq, unsigned int venc_freq,
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unsigned int dac_freq, bool hdmi_use_enci);
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2016-11-10 14:29:37 +00:00
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#endif /* __MESON_VCLK_H */
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