2012-07-05 21:36:43 +00:00
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/*
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* Copyright 2012 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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2012-07-10 00:49:22 +00:00
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#include <subdev/bios.h>
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2012-11-04 00:01:53 +00:00
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#include <subdev/bus.h>
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2012-07-10 02:20:17 +00:00
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#include <subdev/gpio.h>
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2012-07-10 04:36:38 +00:00
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#include <subdev/i2c.h>
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2014-08-25 22:26:38 +00:00
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#include <subdev/fuse.h>
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2015-01-13 13:37:38 +00:00
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#include <subdev/clk.h>
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2012-09-02 00:55:58 +00:00
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#include <subdev/therm.h>
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2012-07-22 06:41:26 +00:00
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#include <subdev/mxm.h>
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2012-07-11 00:44:20 +00:00
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#include <subdev/devinit.h>
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2012-07-11 05:58:56 +00:00
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#include <subdev/mc.h>
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2012-07-11 06:08:25 +00:00
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#include <subdev/timer.h>
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2012-07-11 09:05:01 +00:00
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#include <subdev/fb.h>
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2014-08-09 18:10:28 +00:00
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#include <subdev/ltc.h>
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2012-09-26 03:05:01 +00:00
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#include <subdev/ibus.h>
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2012-07-14 09:09:17 +00:00
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#include <subdev/instmem.h>
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2015-01-13 23:57:36 +00:00
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#include <subdev/mmu.h>
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2012-07-14 09:09:17 +00:00
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#include <subdev/bar.h>
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2015-01-13 14:04:21 +00:00
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#include <subdev/pmu.h>
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2013-02-07 23:34:56 +00:00
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#include <subdev/volt.h>
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2012-07-05 21:36:43 +00:00
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2013-04-25 07:23:43 +00:00
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#include <engine/device.h>
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2012-07-19 22:17:34 +00:00
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#include <engine/dmaobj.h>
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#include <engine/fifo.h>
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2015-01-14 02:34:00 +00:00
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#include <engine/sw.h>
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2015-01-14 02:02:28 +00:00
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#include <engine/gr.h>
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2015-01-14 02:50:04 +00:00
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#include <engine/mspdec.h>
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2012-07-19 22:17:34 +00:00
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#include <engine/bsp.h>
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2015-01-14 00:09:24 +00:00
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#include <engine/msvld.h>
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2015-01-14 02:26:28 +00:00
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#include <engine/msppp.h>
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2015-01-14 01:50:20 +00:00
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#include <engine/ce.h>
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2012-07-19 22:17:34 +00:00
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#include <engine/disp.h>
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2015-01-14 02:11:28 +00:00
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#include <engine/pm.h>
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2012-07-19 22:17:34 +00:00
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2012-07-05 21:36:43 +00:00
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int
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nvc0_identify(struct nouveau_device *device)
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{
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switch (device->chipset) {
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case 0xc0:
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2012-07-26 22:28:20 +00:00
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device->cname = "GF100";
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2012-07-10 00:49:22 +00:00
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device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
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2015-01-14 05:02:59 +00:00
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device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
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2015-01-14 05:04:16 +00:00
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device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
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2014-08-25 22:26:38 +00:00
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device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
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2015-01-14 04:47:24 +00:00
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device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass;
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2012-12-04 02:18:59 +00:00
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device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
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2012-07-22 06:41:26 +00:00
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device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
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2015-01-14 04:48:16 +00:00
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device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
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2015-01-14 05:08:21 +00:00
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device->oclass[NVDEV_SUBDEV_MC ] = gf100_mc_oclass;
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2015-01-14 04:40:22 +00:00
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device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
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2012-07-11 06:08:25 +00:00
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device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
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2015-01-14 04:52:58 +00:00
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device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass;
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2014-08-09 18:10:28 +00:00
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device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
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2015-01-14 05:04:31 +00:00
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device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass;
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2013-12-22 14:39:47 +00:00
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device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
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2015-01-14 05:09:19 +00:00
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device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
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2015-01-14 04:35:35 +00:00
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device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
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2015-01-13 14:04:21 +00:00
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device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass;
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2013-02-07 23:34:56 +00:00
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device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
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2014-08-09 18:10:24 +00:00
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device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass;
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2013-11-05 04:26:58 +00:00
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device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
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2015-01-14 02:34:00 +00:00
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device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
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2015-01-14 02:02:28 +00:00
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device->oclass[NVDEV_ENGINE_GR ] = nvc0_gr_oclass;
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2015-01-14 02:50:04 +00:00
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device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;
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2015-01-14 00:09:24 +00:00
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device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
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2015-01-14 02:26:28 +00:00
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device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
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2015-01-14 01:50:20 +00:00
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device->oclass[NVDEV_ENGINE_CE0 ] = &nvc0_ce0_oclass;
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device->oclass[NVDEV_ENGINE_CE1 ] = &nvc0_ce1_oclass;
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2014-02-20 11:33:34 +00:00
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device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
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2015-01-14 02:11:28 +00:00
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device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass;
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2012-07-05 21:36:43 +00:00
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break;
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case 0xc4:
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2012-07-26 22:28:20 +00:00
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device->cname = "GF104";
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2012-07-10 00:49:22 +00:00
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device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
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2015-01-14 05:02:59 +00:00
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device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
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2015-01-14 05:04:16 +00:00
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device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
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2014-08-25 22:26:38 +00:00
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device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
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2015-01-14 04:47:24 +00:00
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device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass;
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2012-12-04 02:18:59 +00:00
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device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
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2012-07-22 06:41:26 +00:00
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device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
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2015-01-14 04:48:16 +00:00
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device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
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2015-01-14 05:08:21 +00:00
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device->oclass[NVDEV_SUBDEV_MC ] = gf100_mc_oclass;
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2015-01-14 04:40:22 +00:00
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device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
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2012-07-11 06:08:25 +00:00
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device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
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2015-01-14 04:52:58 +00:00
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device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass;
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2014-08-09 18:10:28 +00:00
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device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
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2015-01-14 05:04:31 +00:00
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device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass;
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2013-12-22 14:39:47 +00:00
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device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
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2015-01-14 05:09:19 +00:00
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device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
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2015-01-14 04:35:35 +00:00
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device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
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2015-01-13 14:04:21 +00:00
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device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass;
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2013-02-07 23:34:56 +00:00
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device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
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2014-08-09 18:10:24 +00:00
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device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass;
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2013-11-05 04:26:58 +00:00
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device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
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2015-01-14 02:34:00 +00:00
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device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
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2015-01-14 02:02:28 +00:00
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device->oclass[NVDEV_ENGINE_GR ] = nvc4_gr_oclass;
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2015-01-14 02:50:04 +00:00
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device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;
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2015-01-14 00:09:24 +00:00
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device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
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2015-01-14 02:26:28 +00:00
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device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
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2015-01-14 01:50:20 +00:00
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device->oclass[NVDEV_ENGINE_CE0 ] = &nvc0_ce0_oclass;
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device->oclass[NVDEV_ENGINE_CE1 ] = &nvc0_ce1_oclass;
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2014-02-20 11:33:34 +00:00
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device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
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2015-01-14 02:11:28 +00:00
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device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass;
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2012-07-05 21:36:43 +00:00
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break;
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case 0xc3:
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2012-07-26 22:28:20 +00:00
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device->cname = "GF106";
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2012-07-10 00:49:22 +00:00
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device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
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2015-01-14 05:02:59 +00:00
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device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
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2015-01-14 05:04:16 +00:00
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device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
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2014-08-25 22:26:38 +00:00
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device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
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2015-01-14 04:47:24 +00:00
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device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass;
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2012-12-04 02:18:59 +00:00
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device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
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2012-07-22 06:41:26 +00:00
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device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
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2015-01-14 04:48:16 +00:00
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device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
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2015-01-14 05:08:21 +00:00
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device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
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2015-01-14 04:40:22 +00:00
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device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
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2012-07-11 06:08:25 +00:00
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device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
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2015-01-14 04:52:58 +00:00
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device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass;
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2014-08-09 18:10:28 +00:00
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device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
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2015-01-14 05:04:31 +00:00
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device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass;
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2013-12-22 14:39:47 +00:00
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device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
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2015-01-14 05:09:19 +00:00
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device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
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2015-01-14 04:35:35 +00:00
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device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
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2015-01-13 14:04:21 +00:00
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device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass;
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2013-02-07 23:34:56 +00:00
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device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
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2014-08-09 18:10:24 +00:00
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device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass;
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2013-11-05 04:26:58 +00:00
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device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
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2015-01-14 02:34:00 +00:00
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device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
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2015-01-14 02:02:28 +00:00
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device->oclass[NVDEV_ENGINE_GR ] = nvc4_gr_oclass;
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2015-01-14 02:50:04 +00:00
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device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;
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2015-01-14 00:09:24 +00:00
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device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
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2015-01-14 02:26:28 +00:00
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device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
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2015-01-14 01:50:20 +00:00
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device->oclass[NVDEV_ENGINE_CE0 ] = &nvc0_ce0_oclass;
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2014-02-20 11:33:34 +00:00
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device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
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2015-01-14 02:11:28 +00:00
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device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass;
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2012-07-05 21:36:43 +00:00
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break;
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case 0xce:
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2012-07-26 22:28:20 +00:00
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device->cname = "GF114";
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2012-07-10 00:49:22 +00:00
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device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
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2015-01-14 05:02:59 +00:00
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device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
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2015-01-14 05:04:16 +00:00
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device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
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2014-08-25 22:26:38 +00:00
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device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
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2015-01-14 04:47:24 +00:00
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device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass;
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2012-12-04 02:18:59 +00:00
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device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
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2012-07-22 06:41:26 +00:00
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device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
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2015-01-14 04:48:16 +00:00
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device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
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2015-01-14 05:08:21 +00:00
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device->oclass[NVDEV_SUBDEV_MC ] = gf100_mc_oclass;
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2015-01-14 04:40:22 +00:00
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device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
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2012-07-11 06:08:25 +00:00
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device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
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2015-01-14 04:52:58 +00:00
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device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass;
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2014-08-09 18:10:28 +00:00
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device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
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2015-01-14 05:04:31 +00:00
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device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass;
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2013-12-22 14:39:47 +00:00
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device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
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2015-01-14 05:09:19 +00:00
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device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
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2015-01-14 04:35:35 +00:00
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device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
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2015-01-13 14:04:21 +00:00
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device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass;
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2013-02-07 23:34:56 +00:00
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device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
|
2014-08-09 18:10:24 +00:00
|
|
|
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass;
|
2013-11-05 04:26:58 +00:00
|
|
|
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
|
2015-01-14 02:34:00 +00:00
|
|
|
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
|
2015-01-14 02:02:28 +00:00
|
|
|
device->oclass[NVDEV_ENGINE_GR ] = nvc4_gr_oclass;
|
2015-01-14 02:50:04 +00:00
|
|
|
device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;
|
2015-01-14 00:09:24 +00:00
|
|
|
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
|
2015-01-14 02:26:28 +00:00
|
|
|
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
|
2015-01-14 01:50:20 +00:00
|
|
|
device->oclass[NVDEV_ENGINE_CE0 ] = &nvc0_ce0_oclass;
|
|
|
|
device->oclass[NVDEV_ENGINE_CE1 ] = &nvc0_ce1_oclass;
|
2014-02-20 11:33:34 +00:00
|
|
|
device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
|
2015-01-14 02:11:28 +00:00
|
|
|
device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass;
|
2012-07-05 21:36:43 +00:00
|
|
|
break;
|
|
|
|
case 0xcf:
|
2012-07-26 22:28:20 +00:00
|
|
|
device->cname = "GF116";
|
2012-07-10 00:49:22 +00:00
|
|
|
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
|
2015-01-14 05:02:59 +00:00
|
|
|
device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
|
2015-01-14 05:04:16 +00:00
|
|
|
device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
|
2014-08-25 22:26:38 +00:00
|
|
|
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
|
2015-01-14 04:47:24 +00:00
|
|
|
device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass;
|
2012-12-04 02:18:59 +00:00
|
|
|
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
|
2012-07-22 06:41:26 +00:00
|
|
|
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
|
2015-01-14 04:48:16 +00:00
|
|
|
device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
|
2015-01-14 05:08:21 +00:00
|
|
|
device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
|
2015-01-14 04:40:22 +00:00
|
|
|
device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
|
2012-07-11 06:08:25 +00:00
|
|
|
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
|
2015-01-14 04:52:58 +00:00
|
|
|
device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass;
|
2014-08-09 18:10:28 +00:00
|
|
|
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
|
2015-01-14 05:04:31 +00:00
|
|
|
device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass;
|
2013-12-22 14:39:47 +00:00
|
|
|
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
|
2015-01-14 05:09:19 +00:00
|
|
|
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
|
2015-01-14 04:35:35 +00:00
|
|
|
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
|
2015-01-13 14:04:21 +00:00
|
|
|
device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass;
|
2013-02-07 23:34:56 +00:00
|
|
|
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
|
2014-08-09 18:10:24 +00:00
|
|
|
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass;
|
2013-11-05 04:26:58 +00:00
|
|
|
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
|
2015-01-14 02:34:00 +00:00
|
|
|
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
|
2015-01-14 02:02:28 +00:00
|
|
|
device->oclass[NVDEV_ENGINE_GR ] = nvc4_gr_oclass;
|
2015-01-14 02:50:04 +00:00
|
|
|
device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;
|
2015-01-14 00:09:24 +00:00
|
|
|
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
|
2015-01-14 02:26:28 +00:00
|
|
|
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
|
2015-01-14 01:50:20 +00:00
|
|
|
device->oclass[NVDEV_ENGINE_CE0 ] = &nvc0_ce0_oclass;
|
2014-02-20 11:33:34 +00:00
|
|
|
device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
|
2015-01-14 02:11:28 +00:00
|
|
|
device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass;
|
2012-07-05 21:36:43 +00:00
|
|
|
break;
|
|
|
|
case 0xc1:
|
2012-07-26 22:28:20 +00:00
|
|
|
device->cname = "GF108";
|
2012-07-10 00:49:22 +00:00
|
|
|
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
|
2015-01-14 05:02:59 +00:00
|
|
|
device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
|
2015-01-14 05:04:16 +00:00
|
|
|
device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
|
2014-08-25 22:26:38 +00:00
|
|
|
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
|
2015-01-14 04:47:24 +00:00
|
|
|
device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass;
|
2012-12-04 02:18:59 +00:00
|
|
|
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
|
2012-07-22 06:41:26 +00:00
|
|
|
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
|
2015-01-14 04:48:16 +00:00
|
|
|
device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
|
2015-01-14 05:08:21 +00:00
|
|
|
device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
|
2015-01-14 04:40:22 +00:00
|
|
|
device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
|
2012-07-11 06:08:25 +00:00
|
|
|
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
|
2015-01-14 04:52:58 +00:00
|
|
|
device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass;
|
2014-08-09 18:10:28 +00:00
|
|
|
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
|
2015-01-14 05:04:31 +00:00
|
|
|
device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass;
|
2013-12-22 14:39:47 +00:00
|
|
|
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
|
2015-01-14 05:09:19 +00:00
|
|
|
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
|
2015-01-14 04:35:35 +00:00
|
|
|
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
|
2015-01-13 14:04:21 +00:00
|
|
|
device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass;
|
2013-02-07 23:34:56 +00:00
|
|
|
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
|
2014-08-09 18:10:24 +00:00
|
|
|
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass;
|
2013-11-05 04:26:58 +00:00
|
|
|
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
|
2015-01-14 02:34:00 +00:00
|
|
|
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
|
2015-01-14 02:02:28 +00:00
|
|
|
device->oclass[NVDEV_ENGINE_GR ] = nvc1_gr_oclass;
|
2015-01-14 02:50:04 +00:00
|
|
|
device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;
|
2015-01-14 00:09:24 +00:00
|
|
|
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
|
2015-01-14 02:26:28 +00:00
|
|
|
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
|
2015-01-14 01:50:20 +00:00
|
|
|
device->oclass[NVDEV_ENGINE_CE0 ] = &nvc0_ce0_oclass;
|
2014-02-20 11:33:34 +00:00
|
|
|
device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
|
2015-01-14 02:11:28 +00:00
|
|
|
device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass;
|
2012-07-05 21:36:43 +00:00
|
|
|
break;
|
|
|
|
case 0xc8:
|
2012-07-26 22:28:20 +00:00
|
|
|
device->cname = "GF110";
|
2012-07-10 00:49:22 +00:00
|
|
|
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
|
2015-01-14 05:02:59 +00:00
|
|
|
device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
|
2015-01-14 05:04:16 +00:00
|
|
|
device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
|
2014-08-25 22:26:38 +00:00
|
|
|
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
|
2015-01-14 04:47:24 +00:00
|
|
|
device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass;
|
2012-12-04 02:18:59 +00:00
|
|
|
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
|
2012-07-22 06:41:26 +00:00
|
|
|
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
|
2015-01-14 04:48:16 +00:00
|
|
|
device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
|
2015-01-14 05:08:21 +00:00
|
|
|
device->oclass[NVDEV_SUBDEV_MC ] = gf100_mc_oclass;
|
2015-01-14 04:40:22 +00:00
|
|
|
device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
|
2012-07-11 06:08:25 +00:00
|
|
|
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
|
2015-01-14 04:52:58 +00:00
|
|
|
device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass;
|
2014-08-09 18:10:28 +00:00
|
|
|
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
|
2015-01-14 05:04:31 +00:00
|
|
|
device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass;
|
2013-12-22 14:39:47 +00:00
|
|
|
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
|
2015-01-14 05:09:19 +00:00
|
|
|
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
|
2015-01-14 04:35:35 +00:00
|
|
|
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
|
2015-01-13 14:04:21 +00:00
|
|
|
device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass;
|
2013-02-07 23:34:56 +00:00
|
|
|
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
|
2014-08-09 18:10:24 +00:00
|
|
|
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass;
|
2013-11-05 04:26:58 +00:00
|
|
|
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
|
2015-01-14 02:34:00 +00:00
|
|
|
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
|
2015-01-14 02:02:28 +00:00
|
|
|
device->oclass[NVDEV_ENGINE_GR ] = nvc8_gr_oclass;
|
2015-01-14 02:50:04 +00:00
|
|
|
device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;
|
2015-01-14 00:09:24 +00:00
|
|
|
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
|
2015-01-14 02:26:28 +00:00
|
|
|
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
|
2015-01-14 01:50:20 +00:00
|
|
|
device->oclass[NVDEV_ENGINE_CE0 ] = &nvc0_ce0_oclass;
|
|
|
|
device->oclass[NVDEV_ENGINE_CE1 ] = &nvc0_ce1_oclass;
|
2014-02-20 11:33:34 +00:00
|
|
|
device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
|
2015-01-14 02:11:28 +00:00
|
|
|
device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass;
|
2012-07-05 21:36:43 +00:00
|
|
|
break;
|
|
|
|
case 0xd9:
|
2012-07-26 22:28:20 +00:00
|
|
|
device->cname = "GF119";
|
2012-07-10 00:49:22 +00:00
|
|
|
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
|
2015-01-14 05:02:59 +00:00
|
|
|
device->oclass[NVDEV_SUBDEV_GPIO ] = gf110_gpio_oclass;
|
2015-01-14 05:04:16 +00:00
|
|
|
device->oclass[NVDEV_SUBDEV_I2C ] = gf110_i2c_oclass;
|
2014-08-25 22:26:38 +00:00
|
|
|
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
|
2015-01-14 04:47:24 +00:00
|
|
|
device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass;
|
2012-12-03 23:50:33 +00:00
|
|
|
device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
|
2012-07-22 06:41:26 +00:00
|
|
|
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
|
2015-01-14 04:48:16 +00:00
|
|
|
device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
|
2015-01-14 05:08:21 +00:00
|
|
|
device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
|
2015-01-14 04:40:22 +00:00
|
|
|
device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
|
2012-07-11 06:08:25 +00:00
|
|
|
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
|
2015-01-14 04:52:58 +00:00
|
|
|
device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass;
|
2014-08-09 18:10:28 +00:00
|
|
|
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
|
2015-01-14 05:04:31 +00:00
|
|
|
device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass;
|
2013-12-22 14:39:47 +00:00
|
|
|
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
|
2015-01-14 05:09:19 +00:00
|
|
|
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
|
2015-01-14 04:35:35 +00:00
|
|
|
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
|
2015-01-13 14:04:21 +00:00
|
|
|
device->oclass[NVDEV_SUBDEV_PMU ] = nvd0_pmu_oclass;
|
2013-02-07 23:34:56 +00:00
|
|
|
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
|
2014-08-09 18:10:24 +00:00
|
|
|
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass;
|
2013-11-05 04:26:58 +00:00
|
|
|
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
|
2015-01-14 02:34:00 +00:00
|
|
|
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
|
2015-01-14 02:02:28 +00:00
|
|
|
device->oclass[NVDEV_ENGINE_GR ] = nvd9_gr_oclass;
|
2015-01-14 02:50:04 +00:00
|
|
|
device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;
|
2015-01-14 00:09:24 +00:00
|
|
|
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
|
2015-01-14 02:26:28 +00:00
|
|
|
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
|
2015-01-14 01:50:20 +00:00
|
|
|
device->oclass[NVDEV_ENGINE_CE0 ] = &nvc0_ce0_oclass;
|
2014-02-20 11:33:34 +00:00
|
|
|
device->oclass[NVDEV_ENGINE_DISP ] = nvd0_disp_oclass;
|
2015-01-14 02:11:28 +00:00
|
|
|
device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass;
|
2013-03-30 11:56:26 +00:00
|
|
|
break;
|
|
|
|
case 0xd7:
|
|
|
|
device->cname = "GF117";
|
|
|
|
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
|
2015-01-14 05:02:59 +00:00
|
|
|
device->oclass[NVDEV_SUBDEV_GPIO ] = gf110_gpio_oclass;
|
2014-06-18 05:46:22 +00:00
|
|
|
device->oclass[NVDEV_SUBDEV_I2C ] = gf117_i2c_oclass;
|
2014-08-25 22:26:38 +00:00
|
|
|
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
|
2015-01-14 04:47:24 +00:00
|
|
|
device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass;
|
2013-03-30 11:56:26 +00:00
|
|
|
device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
|
|
|
|
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
|
2015-01-14 04:48:16 +00:00
|
|
|
device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
|
2015-01-14 05:08:21 +00:00
|
|
|
device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
|
2015-01-14 04:40:22 +00:00
|
|
|
device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
|
2013-03-30 11:56:26 +00:00
|
|
|
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
|
2015-01-14 04:52:58 +00:00
|
|
|
device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass;
|
2014-08-09 18:10:28 +00:00
|
|
|
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
|
2015-01-14 05:04:31 +00:00
|
|
|
device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass;
|
2013-12-22 14:39:47 +00:00
|
|
|
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
|
2015-01-14 05:09:19 +00:00
|
|
|
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
|
2015-01-14 04:35:35 +00:00
|
|
|
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
|
2014-08-09 18:10:24 +00:00
|
|
|
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass;
|
2013-11-05 04:26:58 +00:00
|
|
|
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
|
2015-01-14 02:34:00 +00:00
|
|
|
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
|
2015-01-14 02:02:28 +00:00
|
|
|
device->oclass[NVDEV_ENGINE_GR ] = nvd7_gr_oclass;
|
2015-01-14 02:50:04 +00:00
|
|
|
device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;
|
2015-01-14 00:09:24 +00:00
|
|
|
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
|
2015-01-14 02:26:28 +00:00
|
|
|
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
|
2015-01-14 01:50:20 +00:00
|
|
|
device->oclass[NVDEV_ENGINE_CE0 ] = &nvc0_ce0_oclass;
|
2014-02-20 11:33:34 +00:00
|
|
|
device->oclass[NVDEV_ENGINE_DISP ] = nvd0_disp_oclass;
|
2015-01-14 02:11:28 +00:00
|
|
|
device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass;
|
2012-07-05 21:36:43 +00:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
nv_fatal(device, "unknown Fermi chipset\n");
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
2012-12-04 02:18:59 +00:00
|
|
|
}
|