[ARM] add Marvell 78xx0 ARM SoC support
The Marvell Discovery Duo (MV78xx0) is a family of ARM SoCs featuring
(depending on the model) one or two Feroceon CPU cores with 512K of L2
cache and VFP coprocessors running at (depending on the model) between
800 MHz and 1.2 GHz, and features a DDR2 controller, two PCIe
interfaces that can each run either in x4 or quad x1 mode, three USB
2.0 interfaces, two 3Gb/s SATA II interfaces, a SPI interface, two
TWSI interfaces, a crypto accelerator, IDMA/XOR engines, a SPI
interface, four UARTs, and depending on the model, two or four gigabit
ethernet interfaces.
This patch adds basic support for the platform, and allows booting
on the MV78x00 development board, with functional UARTs, SATA, PCIe,
GigE and USB ports.
Signed-off-by: Stanislav Samsonov <samsonov@marvell.com>
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
2008-06-22 20:45:10 +00:00
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/*
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* arch/arm/mach-mv78xx0/common.h
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*
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* Core functions for Marvell MV78xx0 SoCs
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#ifndef __ARCH_MV78XX0_COMMON_H
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#define __ARCH_MV78XX0_COMMON_H
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struct mv643xx_eth_platform_data;
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struct mv_sata_platform_data;
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/*
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* Basic MV78xx0 init functions used early by machine-setup.
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*/
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int mv78xx0_core_index(void);
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void mv78xx0_map_io(void);
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void mv78xx0_init(void);
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void mv78xx0_init_irq(void);
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extern struct mbus_dram_target_info mv78xx0_mbus_dram_info;
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void mv78xx0_setup_cpu_mbus(void);
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void mv78xx0_setup_pcie_io_win(int window, u32 base, u32 size,
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int maj, int min);
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void mv78xx0_setup_pcie_mem_win(int window, u32 base, u32 size,
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int maj, int min);
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2009-02-20 01:31:35 +00:00
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void mv78xx0_pcie_id(u32 *dev, u32 *rev);
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[ARM] add Marvell 78xx0 ARM SoC support
The Marvell Discovery Duo (MV78xx0) is a family of ARM SoCs featuring
(depending on the model) one or two Feroceon CPU cores with 512K of L2
cache and VFP coprocessors running at (depending on the model) between
800 MHz and 1.2 GHz, and features a DDR2 controller, two PCIe
interfaces that can each run either in x4 or quad x1 mode, three USB
2.0 interfaces, two 3Gb/s SATA II interfaces, a SPI interface, two
TWSI interfaces, a crypto accelerator, IDMA/XOR engines, a SPI
interface, four UARTs, and depending on the model, two or four gigabit
ethernet interfaces.
This patch adds basic support for the platform, and allows booting
on the MV78x00 development board, with functional UARTs, SATA, PCIe,
GigE and USB ports.
Signed-off-by: Stanislav Samsonov <samsonov@marvell.com>
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
2008-06-22 20:45:10 +00:00
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void mv78xx0_ehci0_init(void);
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void mv78xx0_ehci1_init(void);
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void mv78xx0_ehci2_init(void);
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void mv78xx0_ge00_init(struct mv643xx_eth_platform_data *eth_data);
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void mv78xx0_ge01_init(struct mv643xx_eth_platform_data *eth_data);
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void mv78xx0_ge10_init(struct mv643xx_eth_platform_data *eth_data);
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void mv78xx0_ge11_init(struct mv643xx_eth_platform_data *eth_data);
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void mv78xx0_pcie_init(int init_port0, int init_port1);
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void mv78xx0_sata_init(struct mv_sata_platform_data *sata_data);
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void mv78xx0_uart0_init(void);
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void mv78xx0_uart1_init(void);
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void mv78xx0_uart2_init(void);
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void mv78xx0_uart3_init(void);
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2009-03-03 19:13:50 +00:00
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void mv78xx0_i2c_init(void);
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[ARM] add Marvell 78xx0 ARM SoC support
The Marvell Discovery Duo (MV78xx0) is a family of ARM SoCs featuring
(depending on the model) one or two Feroceon CPU cores with 512K of L2
cache and VFP coprocessors running at (depending on the model) between
800 MHz and 1.2 GHz, and features a DDR2 controller, two PCIe
interfaces that can each run either in x4 or quad x1 mode, three USB
2.0 interfaces, two 3Gb/s SATA II interfaces, a SPI interface, two
TWSI interfaces, a crypto accelerator, IDMA/XOR engines, a SPI
interface, four UARTs, and depending on the model, two or four gigabit
ethernet interfaces.
This patch adds basic support for the platform, and allows booting
on the MV78x00 development board, with functional UARTs, SATA, PCIe,
GigE and USB ports.
Signed-off-by: Stanislav Samsonov <samsonov@marvell.com>
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
2008-06-22 20:45:10 +00:00
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extern struct sys_timer mv78xx0_timer;
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#endif
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