2005-10-31 14:25:02 +00:00
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/*
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* linux/include/asm-arm/arch-realview/platform.h
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*
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* Copyright (c) ARM Limited 2003. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifndef __address_h
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#define __address_h 1
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/*
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* Memory definitions
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*/
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#define REALVIEW_BOOT_ROM_LO 0x30000000 /* DoC Base (64Mb)...*/
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#define REALVIEW_BOOT_ROM_HI 0x30000000
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#define REALVIEW_BOOT_ROM_BASE REALVIEW_BOOT_ROM_HI /* Normal position */
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#define REALVIEW_BOOT_ROM_SIZE SZ_64M
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#define REALVIEW_SSRAM_BASE /* REALVIEW_SSMC_BASE ? */
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#define REALVIEW_SSRAM_SIZE SZ_2M
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#define REALVIEW_FLASH_BASE 0x40000000
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#define REALVIEW_FLASH_SIZE SZ_64M
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/*
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* SDRAM
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*/
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#define REALVIEW_SDRAM_BASE 0x00000000
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/*
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* Logic expansion modules
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*
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*/
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/* ------------------------------------------------------------------------
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* RealView Registers
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* ------------------------------------------------------------------------
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*
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*/
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#define REALVIEW_SYS_ID_OFFSET 0x00
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#define REALVIEW_SYS_SW_OFFSET 0x04
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#define REALVIEW_SYS_LED_OFFSET 0x08
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#define REALVIEW_SYS_OSC0_OFFSET 0x0C
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#define REALVIEW_SYS_OSC1_OFFSET 0x10
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#define REALVIEW_SYS_OSC2_OFFSET 0x14
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#define REALVIEW_SYS_OSC3_OFFSET 0x18
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#define REALVIEW_SYS_OSC4_OFFSET 0x1C /* OSC1 for RealView/AB */
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#define REALVIEW_SYS_LOCK_OFFSET 0x20
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#define REALVIEW_SYS_100HZ_OFFSET 0x24
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#define REALVIEW_SYS_CFGDATA1_OFFSET 0x28
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#define REALVIEW_SYS_CFGDATA2_OFFSET 0x2C
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#define REALVIEW_SYS_FLAGS_OFFSET 0x30
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#define REALVIEW_SYS_FLAGSSET_OFFSET 0x30
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#define REALVIEW_SYS_FLAGSCLR_OFFSET 0x34
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#define REALVIEW_SYS_NVFLAGS_OFFSET 0x38
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#define REALVIEW_SYS_NVFLAGSSET_OFFSET 0x38
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#define REALVIEW_SYS_NVFLAGSCLR_OFFSET 0x3C
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#define REALVIEW_SYS_RESETCTL_OFFSET 0x40
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#define REALVIEW_SYS_PCICTL_OFFSET 0x44
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#define REALVIEW_SYS_MCI_OFFSET 0x48
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#define REALVIEW_SYS_FLASH_OFFSET 0x4C
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#define REALVIEW_SYS_CLCD_OFFSET 0x50
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#define REALVIEW_SYS_CLCDSER_OFFSET 0x54
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#define REALVIEW_SYS_BOOTCS_OFFSET 0x58
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#define REALVIEW_SYS_24MHz_OFFSET 0x5C
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#define REALVIEW_SYS_MISC_OFFSET 0x60
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#define REALVIEW_SYS_IOSEL_OFFSET 0x70
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#define REALVIEW_SYS_TEST_OSC0_OFFSET 0x80
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#define REALVIEW_SYS_TEST_OSC1_OFFSET 0x84
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#define REALVIEW_SYS_TEST_OSC2_OFFSET 0x88
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#define REALVIEW_SYS_TEST_OSC3_OFFSET 0x8C
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#define REALVIEW_SYS_TEST_OSC4_OFFSET 0x90
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#define REALVIEW_SYS_BASE 0x10000000
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#define REALVIEW_SYS_ID (REALVIEW_SYS_BASE + REALVIEW_SYS_ID_OFFSET)
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#define REALVIEW_SYS_SW (REALVIEW_SYS_BASE + REALVIEW_SYS_SW_OFFSET)
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#define REALVIEW_SYS_LED (REALVIEW_SYS_BASE + REALVIEW_SYS_LED_OFFSET)
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#define REALVIEW_SYS_OSC0 (REALVIEW_SYS_BASE + REALVIEW_SYS_OSC0_OFFSET)
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#define REALVIEW_SYS_OSC1 (REALVIEW_SYS_BASE + REALVIEW_SYS_OSC1_OFFSET)
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#define REALVIEW_SYS_LOCK (REALVIEW_SYS_BASE + REALVIEW_SYS_LOCK_OFFSET)
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#define REALVIEW_SYS_100HZ (REALVIEW_SYS_BASE + REALVIEW_SYS_100HZ_OFFSET)
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#define REALVIEW_SYS_CFGDATA1 (REALVIEW_SYS_BASE + REALVIEW_SYS_CFGDATA1_OFFSET)
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#define REALVIEW_SYS_CFGDATA2 (REALVIEW_SYS_BASE + REALVIEW_SYS_CFGDATA2_OFFSET)
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#define REALVIEW_SYS_FLAGS (REALVIEW_SYS_BASE + REALVIEW_SYS_FLAGS_OFFSET)
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#define REALVIEW_SYS_FLAGSSET (REALVIEW_SYS_BASE + REALVIEW_SYS_FLAGSSET_OFFSET)
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#define REALVIEW_SYS_FLAGSCLR (REALVIEW_SYS_BASE + REALVIEW_SYS_FLAGSCLR_OFFSET)
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#define REALVIEW_SYS_NVFLAGS (REALVIEW_SYS_BASE + REALVIEW_SYS_NVFLAGS_OFFSET)
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#define REALVIEW_SYS_NVFLAGSSET (REALVIEW_SYS_BASE + REALVIEW_SYS_NVFLAGSSET_OFFSET)
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#define REALVIEW_SYS_NVFLAGSCLR (REALVIEW_SYS_BASE + REALVIEW_SYS_NVFLAGSCLR_OFFSET)
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#define REALVIEW_SYS_RESETCTL (REALVIEW_SYS_BASE + REALVIEW_SYS_RESETCTL_OFFSET)
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#define REALVIEW_SYS_PCICTL (REALVIEW_SYS_BASE + REALVIEW_SYS_PCICTL_OFFSET)
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#define REALVIEW_SYS_MCI (REALVIEW_SYS_BASE + REALVIEW_SYS_MCI_OFFSET)
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#define REALVIEW_SYS_FLASH (REALVIEW_SYS_BASE + REALVIEW_SYS_FLASH_OFFSET)
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#define REALVIEW_SYS_CLCD (REALVIEW_SYS_BASE + REALVIEW_SYS_CLCD_OFFSET)
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#define REALVIEW_SYS_CLCDSER (REALVIEW_SYS_BASE + REALVIEW_SYS_CLCDSER_OFFSET)
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#define REALVIEW_SYS_BOOTCS (REALVIEW_SYS_BASE + REALVIEW_SYS_BOOTCS_OFFSET)
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#define REALVIEW_SYS_24MHz (REALVIEW_SYS_BASE + REALVIEW_SYS_24MHz_OFFSET)
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#define REALVIEW_SYS_MISC (REALVIEW_SYS_BASE + REALVIEW_SYS_MISC_OFFSET)
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#define REALVIEW_SYS_IOSEL (REALVIEW_SYS_BASE + REALVIEW_SYS_IOSEL_OFFSET)
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#define REALVIEW_SYS_TEST_OSC0 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC0_OFFSET)
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#define REALVIEW_SYS_TEST_OSC1 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC1_OFFSET)
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#define REALVIEW_SYS_TEST_OSC2 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC2_OFFSET)
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#define REALVIEW_SYS_TEST_OSC3 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC3_OFFSET)
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#define REALVIEW_SYS_TEST_OSC4 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC4_OFFSET)
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/*
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* Values for REALVIEW_SYS_RESET_CTRL
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*/
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#define REALVIEW_SYS_CTRL_RESET_CONFIGCLR 0x01
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#define REALVIEW_SYS_CTRL_RESET_CONFIGINIT 0x02
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#define REALVIEW_SYS_CTRL_RESET_DLLRESET 0x03
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#define REALVIEW_SYS_CTRL_RESET_PLLRESET 0x04
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#define REALVIEW_SYS_CTRL_RESET_POR 0x05
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#define REALVIEW_SYS_CTRL_RESET_DoC 0x06
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#define REALVIEW_SYS_CTRL_LED (1 << 0)
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/* ------------------------------------------------------------------------
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* RealView control registers
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* ------------------------------------------------------------------------
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*/
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/*
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* REALVIEW_IDFIELD
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*
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* 31:24 = manufacturer (0x41 = ARM)
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* 23:16 = architecture (0x08 = AHB system bus, ASB processor bus)
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* 15:12 = FPGA (0x3 = XVC600 or XVC600E)
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* 11:4 = build value
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* 3:0 = revision number (0x1 = rev B (AHB))
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*/
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/*
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* REALVIEW_SYS_LOCK
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* control access to SYS_OSCx, SYS_CFGDATAx, SYS_RESETCTL,
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* SYS_CLD, SYS_BOOTCS
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*/
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#define REALVIEW_SYS_LOCK_LOCKED (1 << 16)
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#define REALVIEW_SYS_LOCKVAL_MASK 0xFFFF /* write 0xA05F to enable write access */
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/*
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* REALVIEW_SYS_FLASH
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*/
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#define REALVIEW_FLASHPROG_FLVPPEN (1 << 0) /* Enable writing to flash */
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/*
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* REALVIEW_INTREG
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* - used to acknowledge and control MMCI and UART interrupts
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*/
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#define REALVIEW_INTREG_WPROT 0x00 /* MMC protection status (no interrupt generated) */
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#define REALVIEW_INTREG_RI0 0x01 /* Ring indicator UART0 is asserted, */
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#define REALVIEW_INTREG_CARDIN 0x08 /* MMCI card in detect */
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/* write 1 to acknowledge and clear */
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#define REALVIEW_INTREG_RI1 0x02 /* Ring indicator UART1 is asserted, */
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#define REALVIEW_INTREG_CARDINSERT 0x03 /* Signal insertion of MMC card */
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/*
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* REALVIEW peripheral addresses
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*/
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#define REALVIEW_SCTL_BASE 0x10001000 /* System controller */
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#define REALVIEW_I2C_BASE 0x10002000 /* I2C control */
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/* Reserved 0x10003000 */
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#define REALVIEW_AACI_BASE 0x10004000 /* Audio */
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#define REALVIEW_MMCI0_BASE 0x10005000 /* MMC interface */
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#define REALVIEW_KMI0_BASE 0x10006000 /* KMI interface */
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#define REALVIEW_KMI1_BASE 0x10007000 /* KMI 2nd interface */
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#define REALVIEW_CHAR_LCD_BASE 0x10008000 /* Character LCD */
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#define REALVIEW_UART0_BASE 0x10009000 /* UART 0 */
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#define REALVIEW_UART1_BASE 0x1000A000 /* UART 1 */
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#define REALVIEW_UART2_BASE 0x1000B000 /* UART 2 */
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#define REALVIEW_UART3_BASE 0x1000C000 /* UART 3 */
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#define REALVIEW_SSP_BASE 0x1000D000 /* Synchronous Serial Port */
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#define REALVIEW_SCI_BASE 0x1000E000 /* Smart card controller */
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/* Reserved 0x1000F000 */
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#define REALVIEW_WATCHDOG_BASE 0x10010000 /* watchdog interface */
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#define REALVIEW_TIMER0_1_BASE 0x10011000 /* Timer 0 and 1 */
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#define REALVIEW_TIMER2_3_BASE 0x10012000 /* Timer 2 and 3 */
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#define REALVIEW_GPIO0_BASE 0x10013000 /* GPIO port 0 */
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#define REALVIEW_GPIO1_BASE 0x10014000 /* GPIO port 1 */
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#define REALVIEW_GPIO2_BASE 0x10015000 /* GPIO port 2 */
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/* Reserved 0x10016000 */
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#define REALVIEW_RTC_BASE 0x10017000 /* Real Time Clock */
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#define REALVIEW_DMC_BASE 0x10018000 /* DMC configuration */
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#define REALVIEW_PCI_CORE_BASE 0x10019000 /* PCI configuration */
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/* Reserved 0x1001A000 - 0x1001FFFF */
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#define REALVIEW_CLCD_BASE 0x10020000 /* CLCD */
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#define REALVIEW_DMAC_BASE 0x10030000 /* DMA controller */
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2005-11-07 21:01:06 +00:00
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#ifndef CONFIG_REALVIEW_MPCORE
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2005-10-31 14:25:02 +00:00
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#define REALVIEW_GIC_CPU_BASE 0x10040000 /* Generic interrupt controller CPU interface */
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#define REALVIEW_GIC_DIST_BASE 0x10041000 /* Generic interrupt controller distributor */
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2005-11-07 21:01:06 +00:00
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#else
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2005-11-07 21:05:42 +00:00
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#define REALVIEW_MPCORE_SCU_BASE 0x10100000 /* SCU registers */
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2005-11-07 21:01:06 +00:00
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#define REALVIEW_GIC_CPU_BASE 0x10100100 /* Generic interrupt controller CPU interface */
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#define REALVIEW_GIC_DIST_BASE 0x10101000 /* Generic interrupt controller distributor */
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#endif
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2005-10-31 14:25:02 +00:00
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#define REALVIEW_SMC_BASE 0x10080000 /* SMC */
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/* Reserved 0x10090000 - 0x100EFFFF */
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#define REALVIEW_ETH_BASE 0x4E000000 /* Ethernet */
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/* PCI space */
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#define REALVIEW_PCI_BASE 0x41000000 /* PCI Interface */
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#define REALVIEW_PCI_CFG_BASE 0x42000000
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#define REALVIEW_PCI_MEM_BASE0 0x44000000
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#define REALVIEW_PCI_MEM_BASE1 0x50000000
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#define REALVIEW_PCI_MEM_BASE2 0x60000000
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/* Sizes of above maps */
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#define REALVIEW_PCI_BASE_SIZE 0x01000000
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#define REALVIEW_PCI_CFG_BASE_SIZE 0x02000000
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#define REALVIEW_PCI_MEM_BASE0_SIZE 0x0c000000 /* 32Mb */
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#define REALVIEW_PCI_MEM_BASE1_SIZE 0x10000000 /* 256Mb */
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#define REALVIEW_PCI_MEM_BASE2_SIZE 0x10000000 /* 256Mb */
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#define REALVIEW_SDRAM67_BASE 0x70000000 /* SDRAM banks 6 and 7 */
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#define REALVIEW_LT_BASE 0x80000000 /* Logic Tile expansion */
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/*
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* Disk on Chip
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*/
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#define REALVIEW_DOC_BASE 0x2C000000
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#define REALVIEW_DOC_SIZE (16 << 20)
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#define REALVIEW_DOC_PAGE_SIZE 512
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#define REALVIEW_DOC_TOTAL_PAGES (DOC_SIZE / PAGE_SIZE)
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#define ERASE_UNIT_PAGES 32
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#define START_PAGE 0x80
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/*
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* LED settings, bits [7:0]
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*/
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#define REALVIEW_SYS_LED0 (1 << 0)
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#define REALVIEW_SYS_LED1 (1 << 1)
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#define REALVIEW_SYS_LED2 (1 << 2)
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#define REALVIEW_SYS_LED3 (1 << 3)
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#define REALVIEW_SYS_LED4 (1 << 4)
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#define REALVIEW_SYS_LED5 (1 << 5)
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#define REALVIEW_SYS_LED6 (1 << 6)
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#define REALVIEW_SYS_LED7 (1 << 7)
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#define ALL_LEDS 0xFF
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#define LED_BANK REALVIEW_SYS_LED
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/*
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* Control registers
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*/
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#define REALVIEW_IDFIELD_OFFSET 0x0 /* RealView build information */
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#define REALVIEW_FLASHPROG_OFFSET 0x4 /* Flash devices */
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#define REALVIEW_INTREG_OFFSET 0x8 /* Interrupt control */
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#define REALVIEW_DECODE_OFFSET 0xC /* Fitted logic modules */
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/* ------------------------------------------------------------------------
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* Interrupts - bit assignment (primary)
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* ------------------------------------------------------------------------
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*/
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2005-11-07 21:01:06 +00:00
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#ifndef CONFIG_REALVIEW_MPCORE
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2005-10-31 14:25:02 +00:00
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#define INT_WDOGINT 0 /* Watchdog timer */
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#define INT_SOFTINT 1 /* Software interrupt */
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#define INT_COMMRx 2 /* Debug Comm Rx interrupt */
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#define INT_COMMTx 3 /* Debug Comm Tx interrupt */
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#define INT_TIMERINT0_1 4 /* Timer 0 and 1 */
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#define INT_TIMERINT2_3 5 /* Timer 2 and 3 */
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#define INT_GPIOINT0 6 /* GPIO 0 */
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#define INT_GPIOINT1 7 /* GPIO 1 */
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#define INT_GPIOINT2 8 /* GPIO 2 */
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/* 9 reserved */
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#define INT_RTCINT 10 /* Real Time Clock */
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#define INT_SSPINT 11 /* Synchronous Serial Port */
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#define INT_UARTINT0 12 /* UART 0 on development chip */
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#define INT_UARTINT1 13 /* UART 1 on development chip */
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#define INT_UARTINT2 14 /* UART 2 on development chip */
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#define INT_UARTINT3 15 /* UART 3 on development chip */
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#define INT_SCIINT 16 /* Smart Card Interface */
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#define INT_MMCI0A 17 /* Multimedia Card 0A */
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#define INT_MMCI0B 18 /* Multimedia Card 0B */
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#define INT_AACI 19 /* Audio Codec */
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#define INT_KMI0 20 /* Keyboard/Mouse port 0 */
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#define INT_KMI1 21 /* Keyboard/Mouse port 1 */
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#define INT_CHARLCD 22 /* Character LCD */
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#define INT_CLCDINT 23 /* CLCD controller */
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#define INT_DMAINT 24 /* DMA controller */
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#define INT_PWRFAILINT 25 /* Power failure */
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#define INT_PISMO 26
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#define INT_DoC 27 /* Disk on Chip memory controller */
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#define INT_ETH 28 /* Ethernet controller */
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#define INT_USB 29 /* USB controller */
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#define INT_TSPENINT 30 /* Touchscreen pen */
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#define INT_TSKPADINT 31 /* Touchscreen keypad */
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2005-11-07 21:01:06 +00:00
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#else
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#define INT_LOCALTIMER 29
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#define INT_LOCALWDOG 30
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#define INT_AACI 0
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#define INT_TIMERINT0_1 1
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#define INT_TIMERINT2_3 2
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#define INT_USB 3
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#define INT_UARTINT0 4
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#define INT_UARTINT1 5
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#define INT_RTCINT 6
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#define INT_KMI0 7
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#define INT_KMI1 8
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#define INT_ETH 9
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#define INT_EB_IRQ1 10 /* main GIC */
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#define INT_EB_IRQ2 11 /* tile GIC */
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#define INT_EB_FIQ1 12 /* main GIC */
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#define INT_EB_FIQ2 13 /* tile GIC */
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#define INT_MMCI0A 14
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#define INT_MMCI0B 15
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#define INT_PMU_CPU0 17
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#define INT_PMU_CPU1 18
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#define INT_PMU_CPU2 19
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#define INT_PMU_CPU3 20
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#define INT_PMU_SCU0 21
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#define INT_PMU_SCU1 22
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#define INT_PMU_SCU2 23
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#define INT_PMU_SCU3 24
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#define INT_PMU_SCU4 25
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#define INT_PMU_SCU5 26
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#define INT_PMU_SCU6 27
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#define INT_PMU_SCU7 28
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#define INT_L220_EVENT 29
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#define INT_L220_SLAVE 30
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#define INT_L220_DECODE 31
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#define INT_UARTINT2 -1
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#define INT_UARTINT3 -1
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#define INT_CLCDINT -1
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#define INT_DMAINT -1
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#define INT_WDOGINT -1
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#define INT_GPIOINT0 -1
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#define INT_GPIOINT1 -1
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#define INT_GPIOINT2 -1
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#define INT_SCIINT -1
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#define INT_SSPINT -1
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#endif
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2005-10-31 14:25:02 +00:00
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/*
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* Interrupt bit positions
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*
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*/
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#define INTMASK_WDOGINT (1 << INT_WDOGINT)
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#define INTMASK_SOFTINT (1 << INT_SOFTINT)
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#define INTMASK_COMMRx (1 << INT_COMMRx)
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#define INTMASK_COMMTx (1 << INT_COMMTx)
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#define INTMASK_TIMERINT0_1 (1 << INT_TIMERINT0_1)
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#define INTMASK_TIMERINT2_3 (1 << INT_TIMERINT2_3)
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#define INTMASK_GPIOINT0 (1 << INT_GPIOINT0)
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#define INTMASK_GPIOINT1 (1 << INT_GPIOINT1)
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#define INTMASK_GPIOINT2 (1 << INT_GPIOINT2)
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#define INTMASK_RTCINT (1 << INT_RTCINT)
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#define INTMASK_SSPINT (1 << INT_SSPINT)
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#define INTMASK_UARTINT0 (1 << INT_UARTINT0)
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#define INTMASK_UARTINT1 (1 << INT_UARTINT1)
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#define INTMASK_UARTINT2 (1 << INT_UARTINT2)
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#define INTMASK_UARTINT3 (1 << INT_UARTINT3)
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#define INTMASK_SCIINT (1 << INT_SCIINT)
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#define INTMASK_MMCI0A (1 << INT_MMCI0A)
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#define INTMASK_MMCI0B (1 << INT_MMCI0B)
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#define INTMASK_AACI (1 << INT_AACI)
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#define INTMASK_KMI0 (1 << INT_KMI0)
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#define INTMASK_KMI1 (1 << INT_KMI1)
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#define INTMASK_CHARLCD (1 << INT_CHARLCD)
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#define INTMASK_CLCDINT (1 << INT_CLCDINT)
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#define INTMASK_DMAINT (1 << INT_DMAINT)
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#define INTMASK_PWRFAILINT (1 << INT_PWRFAILINT)
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#define INTMASK_PISMO (1 << INT_PISMO)
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#define INTMASK_DoC (1 << INT_DoC)
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#define INTMASK_ETH (1 << INT_ETH)
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#define INTMASK_USB (1 << INT_USB)
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#define INTMASK_TSPENINT (1 << INT_TSPENINT)
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#define INTMASK_TSKPADINT (1 << INT_TSKPADINT)
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#define MAXIRQNUM 31
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#define MAXFIQNUM 31
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#define MAXSWINUM 31
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/*
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* Application Flash
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*
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*/
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#define FLASH_BASE REALVIEW_FLASH_BASE
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#define FLASH_SIZE REALVIEW_FLASH_SIZE
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#define FLASH_END (FLASH_BASE + FLASH_SIZE - 1)
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#define FLASH_BLOCK_SIZE SZ_128K
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/*
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* Boot Flash
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*
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*/
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#define EPROM_BASE REALVIEW_BOOT_ROM_HI
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#define EPROM_SIZE REALVIEW_BOOT_ROM_SIZE
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#define EPROM_END (EPROM_BASE + EPROM_SIZE - 1)
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/*
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* Clean base - dummy
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*
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*/
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#define CLEAN_BASE EPROM_BASE
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/*
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* System controller bit assignment
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*/
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#define REALVIEW_REFCLK 0
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#define REALVIEW_TIMCLK 1
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#define REALVIEW_TIMER1_EnSel 15
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#define REALVIEW_TIMER2_EnSel 17
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#define REALVIEW_TIMER3_EnSel 19
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#define REALVIEW_TIMER4_EnSel 21
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#define MAX_TIMER 2
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#define MAX_PERIOD 699050
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#define TICKS_PER_uSEC 1
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/*
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* These are useconds NOT ticks.
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*
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*/
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#define mSEC_1 1000
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#define mSEC_5 (mSEC_1 * 5)
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#define mSEC_10 (mSEC_1 * 10)
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#define mSEC_25 (mSEC_1 * 25)
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#define SEC_1 (mSEC_1 * 1000)
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#define REALVIEW_CSR_BASE 0x10000000
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#define REALVIEW_CSR_SIZE 0x10000000
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#endif
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/* END */
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