2005-04-16 22:20:36 +00:00
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/* include/asm-arm/arch-lh7a40x/dma.h
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*
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2006-05-16 10:41:27 +00:00
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* Copyright (C) 2005 Marc Singer
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2005-04-16 22:20:36 +00:00
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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*/
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2006-05-16 10:41:27 +00:00
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typedef enum {
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DMA_M2M0 = 0,
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DMA_M2M1 = 1,
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DMA_M2P0 = 2, /* Tx */
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DMA_M2P1 = 3, /* Rx */
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DMA_M2P2 = 4, /* Tx */
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DMA_M2P3 = 5, /* Rx */
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DMA_M2P4 = 6, /* Tx - AC97 */
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DMA_M2P5 = 7, /* Rx - AC97 */
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DMA_M2P6 = 8, /* Tx */
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DMA_M2P7 = 9, /* Rx */
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} dma_device_t;
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#define DMA_LENGTH_MAX ((64*1024) - 4) /* bytes */
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#define DMAC_GCA __REG(DMAC_PHYS + 0x2b80)
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#define DMAC_GIR __REG(DMAC_PHYS + 0x2bc0)
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#define DMAC_GIR_MMI1 (1<<11)
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#define DMAC_GIR_MMI0 (1<<10)
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#define DMAC_GIR_MPI8 (1<<9)
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#define DMAC_GIR_MPI9 (1<<8)
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#define DMAC_GIR_MPI6 (1<<7)
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#define DMAC_GIR_MPI7 (1<<6)
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#define DMAC_GIR_MPI4 (1<<5)
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#define DMAC_GIR_MPI5 (1<<4)
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#define DMAC_GIR_MPI2 (1<<3)
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#define DMAC_GIR_MPI3 (1<<2)
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#define DMAC_GIR_MPI0 (1<<1)
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#define DMAC_GIR_MPI1 (1<<0)
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#define DMAC_M2P0 0x0000
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#define DMAC_M2P1 0x0040
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#define DMAC_M2P2 0x0080
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#define DMAC_M2P3 0x00c0
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#define DMAC_M2P4 0x0240
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#define DMAC_M2P5 0x0200
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#define DMAC_M2P6 0x02c0
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#define DMAC_M2P7 0x0280
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#define DMAC_M2P8 0x0340
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#define DMAC_M2P9 0x0300
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#define DMAC_M2M0 0x0100
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#define DMAC_M2M1 0x0140
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#define DMAC_P_PCONTROL(c) __REG(DMAC_PHYS + (c) + 0x00)
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#define DMAC_P_PINTERRUPT(c) __REG(DMAC_PHYS + (c) + 0x04)
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#define DMAC_P_PPALLOC(c) __REG(DMAC_PHYS + (c) + 0x08)
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#define DMAC_P_PSTATUS(c) __REG(DMAC_PHYS + (c) + 0x0c)
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#define DMAC_P_REMAIN(c) __REG(DMAC_PHYS + (c) + 0x14)
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#define DMAC_P_MAXCNT0(c) __REG(DMAC_PHYS + (c) + 0x20)
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#define DMAC_P_BASE0(c) __REG(DMAC_PHYS + (c) + 0x24)
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#define DMAC_P_CURRENT0(c) __REG(DMAC_PHYS + (c) + 0x28)
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#define DMAC_P_MAXCNT1(c) __REG(DMAC_PHYS + (c) + 0x30)
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#define DMAC_P_BASE1(c) __REG(DMAC_PHYS + (c) + 0x34)
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#define DMAC_P_CURRENT1(c) __REG(DMAC_PHYS + (c) + 0x38)
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#define DMAC_PCONTROL_ENABLE (1<<4)
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#define DMAC_PORT_USB 0
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#define DMAC_PORT_SDMMC 1
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#define DMAC_PORT_AC97_1 2
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#define DMAC_PORT_AC97_2 3
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#define DMAC_PORT_AC97_3 4
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#define DMAC_PORT_UART1 6
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#define DMAC_PORT_UART2 7
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#define DMAC_PORT_UART3 8
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#define DMAC_PSTATUS_CURRSTATE_SHIFT 4
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#define DMAC_PSTATUS_CURRSTATE_MASK 0x3
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#define DMAC_PSTATUS_NEXTBUF (1<<6)
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#define DMAC_PSTATUS_STALLRINT (1<<0)
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#define DMAC_INT_CHE (1<<3)
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#define DMAC_INT_NFB (1<<1)
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#define DMAC_INT_STALL (1<<0)
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