2019-05-27 06:55:01 +00:00
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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2005-09-26 06:04:21 +00:00
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/*
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* PowerPC version
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* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
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*
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* Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
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* Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
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* Adapted for Power Macintosh by Paul Mackerras.
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* Low-level exception handlers and MMU support
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* rewritten by Paul Mackerras.
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* Copyright (C) 1996 Paul Mackerras.
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*
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* Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and
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* Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com
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*
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2009-06-02 21:17:38 +00:00
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* This file contains the entry point for the 64-bit kernel along
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* with some early initialization code common to all 64-bit powerpc
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* variants.
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2005-09-26 06:04:21 +00:00
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*/
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#include <linux/threads.h>
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2014-01-09 05:44:29 +00:00
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#include <linux/init.h>
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2005-10-10 04:01:07 +00:00
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#include <asm/reg.h>
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2005-09-26 06:04:21 +00:00
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#include <asm/page.h>
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#include <asm/mmu.h>
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#include <asm/ppc_asm.h>
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2016-09-28 01:31:48 +00:00
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#include <asm/head-64.h>
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2005-09-26 06:04:21 +00:00
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#include <asm/asm-offsets.h>
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#include <asm/bug.h>
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#include <asm/cputable.h>
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#include <asm/setup.h>
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#include <asm/hvcall.h>
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[PATCH] powerpc: Merge thread_info.h
Merge ppc32 and ppc64 versions of thread_info.h. They were pretty
similar already, the chief changes are:
- Instead of inline asm to implement current_thread_info(),
which needs to be different for ppc32 and ppc64, we use C with an
asm("r1") register variable. gcc turns it into the same asm as we
used to have for both platforms.
- We replace ppc32's 'local_flags' with the ppc64
'syscall_noerror' field. The noerror flag was in fact the only thing
in the local_flags field anyway, so the ppc64 approach is simpler, and
means we only need a load-immediate/store instead of load/mask/store
when clearing the flag.
- In readiness for 64k pages, when THREAD_SIZE will be less
than a page, ppc64 used kmalloc() rather than get_free_pages() to
allocate the kernel stack. With this patch we do the same for ppc32,
since there's no strong reason not to.
- For ppc64, we no longer export THREAD_SHIFT and THREAD_SIZE
via asm-offsets, thread_info.h can now be safely included in asm, as
on ppc32.
Built and booted on G4 Powerbook (ARCH=ppc and ARCH=powerpc) and
Power5 (ARCH=ppc64 and ARCH=powerpc).
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2005-10-21 05:45:50 +00:00
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#include <asm/thread_info.h>
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2006-09-25 08:19:00 +00:00
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#include <asm/firmware.h>
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2007-08-20 04:58:36 +00:00
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#include <asm/page_64.h>
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2008-04-17 04:35:01 +00:00
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#include <asm/irqflags.h>
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2010-04-15 22:11:32 +00:00
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#include <asm/kvm_book3s_asm.h>
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2010-11-18 15:06:17 +00:00
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#include <asm/ptrace.h>
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powerpc: Rework lazy-interrupt handling
The current implementation of lazy interrupts handling has some
issues that this tries to address.
We don't do the various workarounds we need to do when re-enabling
interrupts in some cases such as when returning from an interrupt
and thus we may still lose or get delayed decrementer or doorbell
interrupts.
The current scheme also makes it much harder to handle the external
"edge" interrupts provided by some BookE processors when using the
EPR facility (External Proxy) and the Freescale Hypervisor.
Additionally, we tend to keep interrupts hard disabled in a number
of cases, such as decrementer interrupts, external interrupts, or
when a masked decrementer interrupt is pending. This is sub-optimal.
This is an attempt at fixing it all in one go by reworking the way
we do the lazy interrupt disabling from the ground up.
The base idea is to replace the "hard_enabled" field with a
"irq_happened" field in which we store a bit mask of what interrupt
occurred while soft-disabled.
When re-enabling, either via arch_local_irq_restore() or when returning
from an interrupt, we can now decide what to do by testing bits in that
field.
We then implement replaying of the missed interrupts either by
re-using the existing exception frame (in exception exit case) or via
the creation of a new one from an assembly trampoline (in the
arch_local_irq_enable case).
This removes the need to play with the decrementer to try to create
fake interrupts, among others.
In addition, this adds a few refinements:
- We no longer hard disable decrementer interrupts that occur
while soft-disabled. We now simply bump the decrementer back to max
(on BookS) or leave it stopped (on BookE) and continue with hard interrupts
enabled, which means that we'll potentially get better sample quality from
performance monitor interrupts.
- Timer, decrementer and doorbell interrupts now hard-enable
shortly after removing the source of the interrupt, which means
they no longer run entirely hard disabled. Again, this will improve
perf sample quality.
- On Book3E 64-bit, we now make the performance monitor interrupt
act as an NMI like Book3S (the necessary C code for that to work
appear to already be present in the FSL perf code, notably calling
nmi_enter instead of irq_enter). (This also fixes a bug where BookE
perfmon interrupts could clobber r14 ... oops)
- We could make "masked" decrementer interrupts act as NMIs when doing
timer-based perf sampling to improve the sample quality.
Signed-off-by-yet: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
v2:
- Add hard-enable to decrementer, timer and doorbells
- Fix CR clobber in masked irq handling on BookE
- Make embedded perf interrupt act as an NMI
- Add a PACA_HAPPENED_EE_EDGE for use by FSL if they want
to retrigger an interrupt without preventing hard-enable
v3:
- Fix or vs. ori bug on Book3E
- Fix enabling of interrupts for some exceptions on Book3E
v4:
- Fix resend of doorbells on return from interrupt on Book3E
v5:
- Rebased on top of my latest series, which involves some significant
rework of some aspects of the patch.
v6:
- 32-bit compile fix
- more compile fixes with various .config combos
- factor out the asm code to soft-disable interrupts
- remove the C wrapper around preempt_schedule_irq
v7:
- Fix a bug with hard irq state tracking on native power7
2012-03-06 07:27:59 +00:00
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#include <asm/hw_irq.h>
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2015-11-20 09:14:02 +00:00
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#include <asm/cputhreads.h>
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2016-03-15 06:47:38 +00:00
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#include <asm/ppc-opcode.h>
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2016-01-14 04:33:46 +00:00
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#include <asm/export.h>
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2018-07-05 16:25:01 +00:00
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#include <asm/feature-fixups.h>
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2005-09-26 06:04:21 +00:00
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2011-03-31 01:57:33 +00:00
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/* The physical memory is laid out such that the secondary processor
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2009-06-02 21:17:38 +00:00
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* spin code sits at 0x0000...0x00ff. On server, the vectors follow
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* using the layout described in exceptions-64s.S
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2005-09-26 06:04:21 +00:00
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*/
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/*
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* Entering into this code we make the following assumptions:
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2009-06-02 21:17:38 +00:00
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*
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* For pSeries or server processors:
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2005-09-26 06:04:21 +00:00
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* 1. The MMU is off & open firmware is running in real mode.
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2017-10-23 08:05:07 +00:00
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* 2. The primary CPU enters at __start.
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* 3. If the RTAS supports "query-cpu-stopped-state", then secondary
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* CPUs will enter as directed by "start-cpu" RTAS call, which is
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* generic_secondary_smp_init, with PIR in r3.
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* 4. Else the secondary CPUs will enter at secondary_hold (0x60) as
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* directed by the "start-cpu" RTS call, with PIR in r3.
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2011-09-19 18:27:58 +00:00
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* -or- For OPAL entry:
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2017-10-23 08:05:07 +00:00
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* 1. The MMU is off, processor in HV mode.
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* 2. The primary CPU enters at 0 with device-tree in r3, OPAL base
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* in r8, and entry in r9 for debugging purposes.
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* 3. Secondary CPUs enter as directed by OPAL_START_CPU call, which
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* is at generic_secondary_smp_init, with PIR in r3.
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2005-09-26 06:04:21 +00:00
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*
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2009-06-02 21:17:38 +00:00
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* For Book3E processors:
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* 1. The MMU is on running in AS0 in a state defined in ePAPR
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* 2. The kernel is entered at __start
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2005-09-26 06:04:21 +00:00
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*/
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2016-09-28 01:31:48 +00:00
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OPEN_FIXED_SECTION(first_256B, 0x0, 0x100)
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USE_FIXED_SECTION(first_256B)
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/*
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* Offsets are relative from the start of fixed section, and
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* first_256B starts at 0. Offsets are a bit easier to use here
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* than the fixed section entry macros.
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*/
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. = 0x0
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2005-09-26 06:04:21 +00:00
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_GLOBAL(__start)
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/* NOP this out unconditionally */
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BEGIN_FTR_SECTION
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2013-09-23 02:04:45 +00:00
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FIXUP_ENDIAN
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2014-02-04 05:04:35 +00:00
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b __start_initialization_multiplatform
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2005-09-26 06:04:21 +00:00
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END_FTR_SECTION(0, 1)
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/* Catch branch to 0 in real mode */
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trap
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2014-03-11 00:54:06 +00:00
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/* Secondary processors spin on this value until it becomes non-zero.
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* When non-zero, it contains the real address of the function the cpu
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* should jump to.
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2008-08-30 01:40:24 +00:00
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*/
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2013-12-28 21:01:47 +00:00
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.balign 8
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2005-09-26 06:04:21 +00:00
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.globl __secondary_hold_spinloop
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__secondary_hold_spinloop:
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2017-03-09 05:42:12 +00:00
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.8byte 0x0
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2005-09-26 06:04:21 +00:00
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/* Secondary processors write this value with their cpu # */
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/* after they enter the spin loop immediately below. */
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.globl __secondary_hold_acknowledge
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__secondary_hold_acknowledge:
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2017-03-09 05:42:12 +00:00
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.8byte 0x0
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2005-09-26 06:04:21 +00:00
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2010-11-18 00:35:07 +00:00
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#ifdef CONFIG_RELOCATABLE
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2008-10-23 18:41:09 +00:00
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/* This flag is set to 1 by a loader if the kernel should run
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* at the loaded address instead of the linked address. This
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* is used by kexec-tools to keep the the kdump kernel in the
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* crash_kernel region. The loader is responsible for
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* observing the alignment requirement.
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*/
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2016-10-14 07:31:33 +00:00
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#ifdef CONFIG_RELOCATABLE_TEST
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#define RUN_AT_LOAD_DEFAULT 1 /* Test relocation, do not copy to 0 */
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#else
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#define RUN_AT_LOAD_DEFAULT 0x72756e30 /* "run0" -- relocate to 0 by default */
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#endif
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2008-10-23 18:41:09 +00:00
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/* Do not move this variable as kexec-tools knows about it. */
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. = 0x5c
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.globl __run_at_load
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__run_at_load:
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2016-09-28 01:31:48 +00:00
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DEFINE_FIXED_SYMBOL(__run_at_load)
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2016-10-14 07:31:33 +00:00
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.long RUN_AT_LOAD_DEFAULT
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2008-10-23 18:41:09 +00:00
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#endif
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2005-09-26 06:04:21 +00:00
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. = 0x60
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/*
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2007-06-15 22:06:23 +00:00
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* The following code is used to hold secondary processors
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* in a spin loop after they have entered the kernel, but
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2005-09-26 06:04:21 +00:00
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* before the bulk of the kernel has been relocated. This code
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* is relocated to physical address 0x60 before prom_init is run.
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* All of it must fit below the first exception vector at 0x100.
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2008-08-30 01:40:24 +00:00
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* Use .globl here not _GLOBAL because we want __secondary_hold
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* to be the actual text address, not a descriptor.
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2005-09-26 06:04:21 +00:00
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*/
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2008-08-30 01:40:24 +00:00
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.globl __secondary_hold
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__secondary_hold:
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2013-09-23 02:04:45 +00:00
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FIXUP_ENDIAN
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2009-07-23 23:15:59 +00:00
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#ifndef CONFIG_PPC_BOOK3E
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2005-09-26 06:04:21 +00:00
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mfmsr r24
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ori r24,r24,MSR_RI
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mtmsrd r24 /* RI on */
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2009-07-23 23:15:59 +00:00
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#endif
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2006-02-13 07:11:13 +00:00
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/* Grab our physical cpu number */
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2005-09-26 06:04:21 +00:00
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mr r24,r3
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2012-12-03 17:05:47 +00:00
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/* stash r4 for book3e */
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mr r25,r4
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2005-09-26 06:04:21 +00:00
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/* Tell the master cpu we're here */
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/* Relocation is off & we are located at an address less */
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/* than 0x100, so only need to grab low order offset. */
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2016-09-28 01:31:48 +00:00
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std r24,(ABS_ADDR(__secondary_hold_acknowledge))(0)
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2005-09-26 06:04:21 +00:00
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sync
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2012-12-03 17:05:47 +00:00
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li r26,0
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#ifdef CONFIG_PPC_BOOK3E
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tovirt(r26,r26)
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#endif
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2005-09-26 06:04:21 +00:00
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/* All secondary cpus wait here until told to start. */
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2016-09-28 01:31:48 +00:00
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100: ld r12,(ABS_ADDR(__secondary_hold_spinloop))(r26)
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2014-02-04 05:07:47 +00:00
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cmpdi 0,r12,0
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2008-08-30 01:40:24 +00:00
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beq 100b
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2005-09-26 06:04:21 +00:00
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2016-11-29 12:45:50 +00:00
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#if defined(CONFIG_SMP) || defined(CONFIG_KEXEC_CORE)
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2012-12-03 17:05:47 +00:00
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#ifdef CONFIG_PPC_BOOK3E
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2014-02-04 05:07:47 +00:00
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tovirt(r12,r12)
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#endif
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mtctr r12
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2005-09-26 06:04:21 +00:00
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mr r3,r24
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2012-12-03 17:05:47 +00:00
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/*
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* it may be the case that other platforms have r4 right to
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* begin with, this gives us some safety in case it is not
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*/
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#ifdef CONFIG_PPC_BOOK3E
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mr r4,r25
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#else
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2009-07-23 23:15:59 +00:00
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li r4,0
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2012-12-03 17:05:47 +00:00
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#endif
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2011-04-05 04:34:58 +00:00
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/* Make sure that patched code is visible */
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isync
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2005-12-05 21:49:00 +00:00
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bctr
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2005-09-26 06:04:21 +00:00
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#else
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2019-08-26 11:10:23 +00:00
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0: trap
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EMIT_BUG_ENTRY 0b, __FILE__, __LINE__, 0
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2005-09-26 06:04:21 +00:00
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#endif
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2016-09-28 01:31:48 +00:00
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CLOSE_FIXED_SECTION(first_256B)
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2005-09-26 06:04:21 +00:00
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/* This value is used to mark exception frames on the stack. */
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.section ".toc","aw"
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exception_marker:
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.tc ID_72656773_68657265[TC],0x7265677368657265
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2016-09-28 01:31:48 +00:00
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.previous
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2005-09-26 06:04:21 +00:00
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/*
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2009-06-02 21:17:38 +00:00
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* On server, we include the exception vectors code here as it
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* relies on absolute addressing which is only possible within
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* this compilation unit
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2005-11-07 00:06:55 +00:00
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*/
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2009-06-02 21:17:38 +00:00
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#ifdef CONFIG_PPC_BOOK3S
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#include "exceptions-64s.S"
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2016-09-28 01:31:48 +00:00
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#else
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OPEN_TEXT_SECTION(0x100)
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2008-08-30 01:40:24 +00:00
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#endif
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2005-11-07 00:06:55 +00:00
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2016-09-28 01:31:48 +00:00
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USE_TEXT_SECTION()
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2011-12-08 07:20:27 +00:00
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#ifdef CONFIG_PPC_BOOK3E
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2015-11-20 09:14:02 +00:00
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/*
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* The booting_thread_hwid holds the thread id we want to boot in cpu
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* hotplug case. It is set by cpu hotplug code, and is invalid by default.
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* The thread id is the same as the initial value of SPRN_PIR[THREAD_ID]
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* bit field.
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*/
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|
.globl booting_thread_hwid
|
|
|
|
|
booting_thread_hwid:
|
|
|
|
|
.long INVALID_THREAD_HWID
|
|
|
|
|
.align 3
|
|
|
|
|
/*
|
|
|
|
|
* start a thread in the same core
|
|
|
|
|
* input parameters:
|
|
|
|
|
* r3 = the thread physical id
|
|
|
|
|
* r4 = the entry point where thread starts
|
|
|
|
|
*/
|
|
|
|
|
_GLOBAL(book3e_start_thread)
|
|
|
|
|
LOAD_REG_IMMEDIATE(r5, MSR_KERNEL)
|
2016-11-23 13:02:07 +00:00
|
|
|
cmpwi r3, 0
|
2015-11-20 09:14:02 +00:00
|
|
|
beq 10f
|
2016-11-23 13:02:07 +00:00
|
|
|
cmpwi r3, 1
|
2015-11-20 09:14:02 +00:00
|
|
|
beq 11f
|
|
|
|
|
/* If the thread id is invalid, just exit. */
|
|
|
|
|
b 13f
|
|
|
|
|
10:
|
2016-03-15 06:47:38 +00:00
|
|
|
MTTMR(TMRN_IMSR0, 5)
|
|
|
|
|
MTTMR(TMRN_INIA0, 4)
|
2015-11-20 09:14:02 +00:00
|
|
|
b 12f
|
|
|
|
|
11:
|
2016-03-15 06:47:38 +00:00
|
|
|
MTTMR(TMRN_IMSR1, 5)
|
|
|
|
|
MTTMR(TMRN_INIA1, 4)
|
2015-11-20 09:14:02 +00:00
|
|
|
12:
|
|
|
|
|
isync
|
|
|
|
|
li r6, 1
|
|
|
|
|
sld r6, r6, r3
|
|
|
|
|
mtspr SPRN_TENS, r6
|
|
|
|
|
13:
|
|
|
|
|
blr
|
|
|
|
|
|
2015-11-20 09:13:59 +00:00
|
|
|
/*
|
|
|
|
|
* stop a thread in the same core
|
|
|
|
|
* input parameter:
|
|
|
|
|
* r3 = the thread physical id
|
|
|
|
|
*/
|
|
|
|
|
_GLOBAL(book3e_stop_thread)
|
2016-11-23 13:02:07 +00:00
|
|
|
cmpwi r3, 0
|
2015-11-20 09:13:59 +00:00
|
|
|
beq 10f
|
2016-11-23 13:02:07 +00:00
|
|
|
cmpwi r3, 1
|
2015-11-20 09:13:59 +00:00
|
|
|
beq 10f
|
|
|
|
|
/* If the thread id is invalid, just exit. */
|
|
|
|
|
b 13f
|
|
|
|
|
10:
|
|
|
|
|
li r4, 1
|
|
|
|
|
sld r4, r4, r3
|
|
|
|
|
mtspr SPRN_TENC, r4
|
|
|
|
|
13:
|
|
|
|
|
blr
|
|
|
|
|
|
2011-12-08 07:20:27 +00:00
|
|
|
_GLOBAL(fsl_secondary_thread_init)
|
2015-10-07 03:48:12 +00:00
|
|
|
mfspr r4,SPRN_BUCSR
|
|
|
|
|
|
2011-12-08 07:20:27 +00:00
|
|
|
/* Enable branch prediction */
|
|
|
|
|
lis r3,BUCSR_INIT@h
|
|
|
|
|
ori r3,r3,BUCSR_INIT@l
|
|
|
|
|
mtspr SPRN_BUCSR,r3
|
|
|
|
|
isync
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Fix PIR to match the linear numbering in the device tree.
|
|
|
|
|
*
|
|
|
|
|
* On e6500, the reset value of PIR uses the low three bits for
|
|
|
|
|
* the thread within a core, and the upper bits for the core
|
|
|
|
|
* number. There are two threads per core, so shift everything
|
|
|
|
|
* but the low bit right by two bits so that the cpu numbering is
|
|
|
|
|
* continuous.
|
2015-10-07 03:48:12 +00:00
|
|
|
*
|
|
|
|
|
* If the old value of BUCSR is non-zero, this thread has run
|
|
|
|
|
* before. Thus, we assume we are coming from kexec or a similar
|
|
|
|
|
* scenario, and PIR is already set to the correct value. This
|
|
|
|
|
* is a bit of a hack, but there are limited opportunities for
|
|
|
|
|
* getting information into the thread and the alternatives
|
|
|
|
|
* seemed like they'd be overkill. We can't tell just by looking
|
|
|
|
|
* at the old PIR value which state it's in, since the same value
|
|
|
|
|
* could be valid for one thread out of reset and for a different
|
|
|
|
|
* thread in Linux.
|
2011-12-08 07:20:27 +00:00
|
|
|
*/
|
2015-10-07 03:48:12 +00:00
|
|
|
|
2011-12-08 07:20:27 +00:00
|
|
|
mfspr r3, SPRN_PIR
|
2015-10-07 03:48:12 +00:00
|
|
|
cmpwi r4,0
|
|
|
|
|
bne 1f
|
2011-12-08 07:20:27 +00:00
|
|
|
rlwimi r3, r3, 30, 2, 30
|
|
|
|
|
mtspr SPRN_PIR, r3
|
2015-10-07 03:48:12 +00:00
|
|
|
1:
|
2009-07-23 23:15:59 +00:00
|
|
|
mr r24,r3
|
|
|
|
|
|
|
|
|
|
/* turn on 64-bit mode */
|
2014-02-04 05:04:35 +00:00
|
|
|
bl enable_64b_mode
|
2009-07-23 23:15:59 +00:00
|
|
|
|
|
|
|
|
/* get a valid TOC pointer, wherever we're mapped at */
|
2014-02-04 05:04:35 +00:00
|
|
|
bl relative_toc
|
2012-11-26 17:41:08 +00:00
|
|
|
tovirt(r2,r2)
|
2009-07-23 23:15:59 +00:00
|
|
|
|
|
|
|
|
/* Book3E initialization */
|
|
|
|
|
mr r3,r24
|
2014-02-04 05:04:35 +00:00
|
|
|
bl book3e_secondary_thread_init
|
2009-07-23 23:15:59 +00:00
|
|
|
b generic_secondary_common_init
|
2005-09-26 06:04:21 +00:00
|
|
|
|
2020-08-19 01:57:04 +00:00
|
|
|
#endif /* CONFIG_PPC_BOOK3E */
|
|
|
|
|
|
2005-09-26 06:04:21 +00:00
|
|
|
/*
|
2006-08-11 05:07:08 +00:00
|
|
|
* On pSeries and most other platforms, secondary processors spin
|
|
|
|
|
* in the following code.
|
2005-09-26 06:04:21 +00:00
|
|
|
* At entry, r3 = this processor's number (physical cpu id)
|
2009-07-23 23:15:59 +00:00
|
|
|
*
|
|
|
|
|
* On Book3E, r4 = 1 to indicate that the initial TLB entry for
|
|
|
|
|
* this core already exists (setup via some other mechanism such
|
|
|
|
|
* as SCOM before entry).
|
2005-09-26 06:04:21 +00:00
|
|
|
*/
|
2006-08-11 05:07:08 +00:00
|
|
|
_GLOBAL(generic_secondary_smp_init)
|
2013-09-23 02:04:45 +00:00
|
|
|
FIXUP_ENDIAN
|
2005-09-26 06:04:21 +00:00
|
|
|
mr r24,r3
|
2009-07-23 23:15:59 +00:00
|
|
|
mr r25,r4
|
|
|
|
|
|
2005-09-26 06:04:21 +00:00
|
|
|
/* turn on 64-bit mode */
|
2014-02-04 05:04:35 +00:00
|
|
|
bl enable_64b_mode
|
2005-09-26 06:04:21 +00:00
|
|
|
|
2009-07-23 23:15:59 +00:00
|
|
|
/* get a valid TOC pointer, wherever we're mapped at */
|
2014-02-04 05:04:35 +00:00
|
|
|
bl relative_toc
|
2012-11-26 17:41:08 +00:00
|
|
|
tovirt(r2,r2)
|
2008-08-30 01:41:12 +00:00
|
|
|
|
2009-07-23 23:15:59 +00:00
|
|
|
#ifdef CONFIG_PPC_BOOK3E
|
|
|
|
|
/* Book3E initialization */
|
|
|
|
|
mr r3,r24
|
|
|
|
|
mr r4,r25
|
2014-02-04 05:04:35 +00:00
|
|
|
bl book3e_secondary_core_init
|
2015-11-20 09:14:02 +00:00
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* After common core init has finished, check if the current thread is the
|
|
|
|
|
* one we wanted to boot. If not, start the specified thread and stop the
|
|
|
|
|
* current thread.
|
|
|
|
|
*/
|
|
|
|
|
LOAD_REG_ADDR(r4, booting_thread_hwid)
|
|
|
|
|
lwz r3, 0(r4)
|
|
|
|
|
li r5, INVALID_THREAD_HWID
|
|
|
|
|
cmpw r3, r5
|
|
|
|
|
beq 20f
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* The value of booting_thread_hwid has been stored in r3,
|
|
|
|
|
* so make it invalid.
|
|
|
|
|
*/
|
|
|
|
|
stw r5, 0(r4)
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Get the current thread id and check if it is the one we wanted.
|
|
|
|
|
* If not, start the one specified in booting_thread_hwid and stop
|
|
|
|
|
* the current thread.
|
|
|
|
|
*/
|
|
|
|
|
mfspr r8, SPRN_TIR
|
|
|
|
|
cmpw r3, r8
|
|
|
|
|
beq 20f
|
|
|
|
|
|
|
|
|
|
/* start the specified thread */
|
|
|
|
|
LOAD_REG_ADDR(r5, fsl_secondary_thread_init)
|
|
|
|
|
ld r4, 0(r5)
|
|
|
|
|
bl book3e_start_thread
|
|
|
|
|
|
|
|
|
|
/* stop the current thread */
|
|
|
|
|
mr r3, r8
|
|
|
|
|
bl book3e_stop_thread
|
|
|
|
|
10:
|
|
|
|
|
b 10b
|
|
|
|
|
20:
|
2009-07-23 23:15:59 +00:00
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
generic_secondary_common_init:
|
2005-09-26 06:04:21 +00:00
|
|
|
/* Set up a paca value for this processor. Since we have the
|
|
|
|
|
* physical cpu id in r24, we need to search the pacas to find
|
|
|
|
|
* which logical id maps to our physical one.
|
|
|
|
|
*/
|
2011-05-10 19:28:37 +00:00
|
|
|
#ifndef CONFIG_SMP
|
2014-02-04 05:04:35 +00:00
|
|
|
b kexec_wait /* wait for next kernel if !SMP */
|
2011-05-10 19:28:37 +00:00
|
|
|
#else
|
2018-02-13 15:08:12 +00:00
|
|
|
LOAD_REG_ADDR(r8, paca_ptrs) /* Load paca_ptrs pointe */
|
|
|
|
|
ld r8,0(r8) /* Get base vaddr of array */
|
2011-05-10 19:28:37 +00:00
|
|
|
LOAD_REG_ADDR(r7, nr_cpu_ids) /* Load nr_cpu_ids address */
|
|
|
|
|
lwz r7,0(r7) /* also the max paca allocated */
|
2005-09-26 06:04:21 +00:00
|
|
|
li r5,0 /* logical cpu id */
|
2018-02-13 15:08:12 +00:00
|
|
|
1:
|
|
|
|
|
sldi r9,r5,3 /* get paca_ptrs[] index from cpu id */
|
|
|
|
|
ldx r13,r9,r8 /* r13 = paca_ptrs[cpu id] */
|
|
|
|
|
lhz r6,PACAHWCPUID(r13) /* Load HW procid from paca */
|
2005-09-26 06:04:21 +00:00
|
|
|
cmpw r6,r24 /* Compare to our id */
|
|
|
|
|
beq 2f
|
|
|
|
|
addi r5,r5,1
|
2011-05-10 19:28:37 +00:00
|
|
|
cmpw r5,r7 /* Check if more pacas exist */
|
2005-09-26 06:04:21 +00:00
|
|
|
blt 1b
|
|
|
|
|
|
|
|
|
|
mr r3,r24 /* not found, copy phys to r3 */
|
2014-02-04 05:04:35 +00:00
|
|
|
b kexec_wait /* next kernel might do better */
|
2005-09-26 06:04:21 +00:00
|
|
|
|
2011-01-20 06:50:21 +00:00
|
|
|
2: SET_PACA(r13)
|
2009-07-23 23:15:59 +00:00
|
|
|
#ifdef CONFIG_PPC_BOOK3E
|
|
|
|
|
addi r12,r13,PACA_EXTLB /* and TLB exc frame in another */
|
|
|
|
|
mtspr SPRN_SPRG_TLB_EXFRAME,r12
|
|
|
|
|
#endif
|
|
|
|
|
|
2005-09-26 06:04:21 +00:00
|
|
|
/* From now on, r24 is expected to be logical cpuid */
|
|
|
|
|
mr r24,r5
|
2008-07-11 23:00:26 +00:00
|
|
|
|
2006-08-11 05:07:08 +00:00
|
|
|
/* See if we need to call a cpu state restore handler */
|
2008-08-30 01:41:12 +00:00
|
|
|
LOAD_REG_ADDR(r23, cur_cpu_spec)
|
2006-08-11 05:07:08 +00:00
|
|
|
ld r23,0(r23)
|
2014-03-11 00:54:06 +00:00
|
|
|
ld r12,CPU_SPEC_RESTORE(r23)
|
|
|
|
|
cmpdi 0,r12,0
|
2011-03-16 03:54:35 +00:00
|
|
|
beq 3f
|
2016-06-06 16:56:10 +00:00
|
|
|
#ifdef PPC64_ELF_ABI_v1
|
2014-03-11 00:54:06 +00:00
|
|
|
ld r12,0(r12)
|
|
|
|
|
#endif
|
2014-02-04 05:07:47 +00:00
|
|
|
mtctr r12
|
2006-08-11 05:07:08 +00:00
|
|
|
bctrl
|
|
|
|
|
|
2011-05-25 18:09:12 +00:00
|
|
|
3: LOAD_REG_ADDR(r3, spinning_secondaries) /* Decrement spinning_secondaries */
|
2011-03-16 03:54:35 +00:00
|
|
|
lwarx r4,0,r3
|
|
|
|
|
subi r4,r4,1
|
|
|
|
|
stwcx. r4,0,r3
|
|
|
|
|
bne 3b
|
|
|
|
|
isync
|
|
|
|
|
|
|
|
|
|
4: HMT_LOW
|
2011-02-01 01:13:09 +00:00
|
|
|
lbz r23,PACAPROCSTART(r13) /* Test if this processor should */
|
|
|
|
|
/* start. */
|
|
|
|
|
cmpwi 0,r23,0
|
2011-03-16 03:54:35 +00:00
|
|
|
beq 4b /* Loop until told to go */
|
2011-02-01 01:13:09 +00:00
|
|
|
|
|
|
|
|
sync /* order paca.run and cur_cpu_spec */
|
2011-03-16 03:54:35 +00:00
|
|
|
isync /* In case code patching happened */
|
2011-02-01 01:13:09 +00:00
|
|
|
|
2011-03-16 03:54:35 +00:00
|
|
|
/* Create a temp kernel stack for use before relocation is on. */
|
2005-09-26 06:04:21 +00:00
|
|
|
ld r1,PACAEMERGSP(r13)
|
|
|
|
|
subi r1,r1,STACK_FRAME_OVERHEAD
|
|
|
|
|
|
2006-11-27 03:59:50 +00:00
|
|
|
b __secondary_start
|
2011-05-10 19:28:37 +00:00
|
|
|
#endif /* SMP */
|
2005-09-26 06:04:21 +00:00
|
|
|
|
2008-08-30 01:41:12 +00:00
|
|
|
/*
|
|
|
|
|
* Turn the MMU off.
|
|
|
|
|
* Assumes we're mapped EA == RA if the MMU is on.
|
|
|
|
|
*/
|
2009-07-23 23:15:59 +00:00
|
|
|
#ifdef CONFIG_PPC_BOOK3S
|
2014-02-04 05:06:11 +00:00
|
|
|
__mmu_off:
|
2005-09-26 06:04:21 +00:00
|
|
|
mfmsr r3
|
|
|
|
|
andi. r0,r3,MSR_IR|MSR_DR
|
|
|
|
|
beqlr
|
2008-08-30 01:41:12 +00:00
|
|
|
mflr r4
|
2005-09-26 06:04:21 +00:00
|
|
|
andc r3,r3,r0
|
|
|
|
|
mtspr SPRN_SRR0,r4
|
|
|
|
|
mtspr SPRN_SRR1,r3
|
|
|
|
|
sync
|
|
|
|
|
rfid
|
|
|
|
|
b . /* prevent speculative execution */
|
2009-07-23 23:15:59 +00:00
|
|
|
#endif
|
2005-09-26 06:04:21 +00:00
|
|
|
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Here is our main kernel entry point. We support currently 2 kind of entries
|
|
|
|
|
* depending on the value of r5.
|
|
|
|
|
*
|
|
|
|
|
* r5 != NULL -> OF entry, we go to prom_init, "legacy" parameter content
|
|
|
|
|
* in r3...r7
|
|
|
|
|
*
|
|
|
|
|
* r5 == NULL -> kexec style entry. r3 is a physical pointer to the
|
|
|
|
|
* DT block, r4 is a physical pointer to the kernel itself
|
|
|
|
|
*
|
|
|
|
|
*/
|
2014-02-04 05:06:11 +00:00
|
|
|
__start_initialization_multiplatform:
|
2008-08-30 01:41:12 +00:00
|
|
|
/* Make sure we are running in 64 bits mode */
|
2014-02-04 05:04:35 +00:00
|
|
|
bl enable_64b_mode
|
2008-08-30 01:41:12 +00:00
|
|
|
|
|
|
|
|
/* Get TOC pointer (current runtime address) */
|
2014-02-04 05:04:35 +00:00
|
|
|
bl relative_toc
|
2008-08-30 01:41:12 +00:00
|
|
|
|
|
|
|
|
/* find out where we are now */
|
|
|
|
|
bcl 20,31,$+4
|
|
|
|
|
0: mflr r26 /* r26 = runtime addr here */
|
|
|
|
|
addis r26,r26,(_stext - 0b)@ha
|
|
|
|
|
addi r26,r26,(_stext - 0b)@l /* current runtime base addr */
|
|
|
|
|
|
2005-09-26 06:04:21 +00:00
|
|
|
/*
|
|
|
|
|
* Are we booted from a PROM Of-type client-interface ?
|
|
|
|
|
*/
|
|
|
|
|
cmpldi cr0,r5,0
|
2007-07-31 06:44:13 +00:00
|
|
|
beq 1f
|
2014-02-04 05:04:35 +00:00
|
|
|
b __boot_from_prom /* yes -> prom */
|
2007-07-31 06:44:13 +00:00
|
|
|
1:
|
2005-09-26 06:04:21 +00:00
|
|
|
/* Save parameters */
|
|
|
|
|
mr r31,r3
|
|
|
|
|
mr r30,r4
|
2011-09-19 17:44:59 +00:00
|
|
|
#ifdef CONFIG_PPC_EARLY_DEBUG_OPAL
|
|
|
|
|
/* Save OPAL entry */
|
|
|
|
|
mr r28,r8
|
|
|
|
|
mr r29,r9
|
|
|
|
|
#endif
|
2005-09-26 06:04:21 +00:00
|
|
|
|
2009-07-23 23:15:59 +00:00
|
|
|
#ifdef CONFIG_PPC_BOOK3E
|
2014-02-04 05:04:35 +00:00
|
|
|
bl start_initialization_book3e
|
|
|
|
|
b __after_prom_start
|
2009-07-23 23:15:59 +00:00
|
|
|
#else
|
2005-09-26 06:04:21 +00:00
|
|
|
/* Setup some critical 970 SPRs before switching MMU off */
|
2006-08-11 05:07:08 +00:00
|
|
|
mfspr r0,SPRN_PVR
|
|
|
|
|
srwi r0,r0,16
|
|
|
|
|
cmpwi r0,0x39 /* 970 */
|
|
|
|
|
beq 1f
|
|
|
|
|
cmpwi r0,0x3c /* 970FX */
|
|
|
|
|
beq 1f
|
|
|
|
|
cmpwi r0,0x44 /* 970MP */
|
2006-10-25 22:32:40 +00:00
|
|
|
beq 1f
|
|
|
|
|
cmpwi r0,0x45 /* 970GX */
|
2006-08-11 05:07:08 +00:00
|
|
|
bne 2f
|
2014-02-04 05:04:35 +00:00
|
|
|
1: bl __cpu_preinit_ppc970
|
2006-08-11 05:07:08 +00:00
|
|
|
2:
|
2005-09-26 06:04:21 +00:00
|
|
|
|
2008-08-30 01:41:12 +00:00
|
|
|
/* Switch off MMU if not already off */
|
2014-02-04 05:04:35 +00:00
|
|
|
bl __mmu_off
|
|
|
|
|
b __after_prom_start
|
2009-07-23 23:15:59 +00:00
|
|
|
#endif /* CONFIG_PPC_BOOK3E */
|
2005-09-26 06:04:21 +00:00
|
|
|
|
powerpc/64s: Fix section mismatch warnings from boot code
We currently have two section mismatch warnings:
The function __boot_from_prom() references
the function __init prom_init().
The function start_here_common() references
the function __init start_kernel().
The warnings are correct, we do have branches from non-init code into
init code, which is freed after boot. But we don't expect to ever
execute any of that early boot code after boot, if we did that would
be a bug. In particular calling into OF after boot would be fatal
because OF is no longer resident.
So for now fix the warnings by marking the relevant functions as
__REF, which puts them in the ".ref.text" section.
This causes some reordering of the functions in the final link:
@@ -217,10 +217,9 @@
c00000000000b088 t generic_secondary_common_init
c00000000000b124 t __mmu_off
c00000000000b14c t __start_initialization_multiplatform
-c00000000000b1ac t __boot_from_prom
-c00000000000b1ec t __after_prom_start
-c00000000000b260 t p_end
-c00000000000b27c T copy_and_flush
+c00000000000b1ac t __after_prom_start
+c00000000000b220 t p_end
+c00000000000b23c T copy_and_flush
c00000000000b300 T __secondary_start
c00000000000b300 t copy_to_here
c00000000000b344 t start_secondary_prolog
@@ -228,8 +227,9 @@
c00000000000b36c t enable_64b_mode
c00000000000b388 T relative_toc
c00000000000b3a8 t p_toc
-c00000000000b3b0 t start_here_common
-c00000000000b3d0 t start_here_multiplatform
+c00000000000b3b0 t __boot_from_prom
+c00000000000b3f0 t start_here_multiplatform
+c00000000000b480 t start_here_common
c00000000000b880 T system_call_common
c00000000000b974 t system_call
c00000000000b9dc t system_call_exit
In particular __boot_from_prom moves after copy_to_here, which means
it's not copied to zero in the first stage of copy of the kernel to
zero.
But that's OK, because we only call __boot_from_prom before we do the
copy, so it makes no difference when it's copied. The call sequence
is:
__start
-> __start_initialization_multiplatform
-> __boot_from_prom
-> __start
-> __start_initialization_multiplatform
-> __after_prom_start
-> copy_and_flush
-> copy_and_flush (relocated to 0)
-> start_here_multiplatform
-> early_setup
Reported-by: Mauricio Faria de Oliveira <mauricfo@linux.ibm.com>
Reported-by: Roman Bolshakov <r.bolshakov@yadro.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200225031328.14676-1-mpe@ellerman.id.au
2020-02-25 03:13:28 +00:00
|
|
|
__REF
|
2014-02-04 05:06:11 +00:00
|
|
|
__boot_from_prom:
|
2009-03-10 17:53:27 +00:00
|
|
|
#ifdef CONFIG_PPC_OF_BOOT_TRAMPOLINE
|
2005-09-26 06:04:21 +00:00
|
|
|
/* Save parameters */
|
|
|
|
|
mr r31,r3
|
|
|
|
|
mr r30,r4
|
|
|
|
|
mr r29,r5
|
|
|
|
|
mr r28,r6
|
|
|
|
|
mr r27,r7
|
|
|
|
|
|
[PATCH] correct the comment about stackpointer alignment in __boot_from_prom
The address of variable val in prom_init_stdout is passed to prom_getprop.
prom_getprop casts the pointer to u32 and passes it to call_prom in the hope
that OpenFirmware stores something there.
But the pointer is truncated in the lower bits and the expected value is
stored somewhere else.
In my testing I had a stackpointer of 0x0023e6b4. val was at offset 120,
wich has address 0x0023e72c. But the value passed to OF was 0x0023e728.
c00000000040b710: 3b 01 00 78 addi r24,r1,120
...
c00000000040b754: 57 08 00 38 rlwinm r8,r24,0,0,28
...
c00000000040b784: 80 01 00 78 lwz r0,120(r1)
...
c00000000040b798: 90 1b 00 0c stw r0,12(r27)
...
The stackpointer came from 32bit code.
The chain was yaboot -> zImage -> vmlinux
PowerMac OpenFirmware does appearently not handle the ELF sections
correctly. If yaboot was compiled in
/usr/src/packages/BUILD/lilo-10.1.1/yaboot, then the stackpointer is
unaligned. But the stackpointer is correct if yaboot is compiled in
/tmp/yaboot.
This bug triggered since 2.6.15, now prom_getprop is an inline
function. gcc clears the lower bits, instead of just clearing the
upper 32 bits.
Signed-off-by: Olaf Hering <olh@suse.de>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-03-23 20:50:59 +00:00
|
|
|
/*
|
|
|
|
|
* Align the stack to 16-byte boundary
|
|
|
|
|
* Depending on the size and layout of the ELF sections in the initial
|
2008-08-30 01:41:12 +00:00
|
|
|
* boot binary, the stack pointer may be unaligned on PowerMac
|
[PATCH] correct the comment about stackpointer alignment in __boot_from_prom
The address of variable val in prom_init_stdout is passed to prom_getprop.
prom_getprop casts the pointer to u32 and passes it to call_prom in the hope
that OpenFirmware stores something there.
But the pointer is truncated in the lower bits and the expected value is
stored somewhere else.
In my testing I had a stackpointer of 0x0023e6b4. val was at offset 120,
wich has address 0x0023e72c. But the value passed to OF was 0x0023e728.
c00000000040b710: 3b 01 00 78 addi r24,r1,120
...
c00000000040b754: 57 08 00 38 rlwinm r8,r24,0,0,28
...
c00000000040b784: 80 01 00 78 lwz r0,120(r1)
...
c00000000040b798: 90 1b 00 0c stw r0,12(r27)
...
The stackpointer came from 32bit code.
The chain was yaboot -> zImage -> vmlinux
PowerMac OpenFirmware does appearently not handle the ELF sections
correctly. If yaboot was compiled in
/usr/src/packages/BUILD/lilo-10.1.1/yaboot, then the stackpointer is
unaligned. But the stackpointer is correct if yaboot is compiled in
/tmp/yaboot.
This bug triggered since 2.6.15, now prom_getprop is an inline
function. gcc clears the lower bits, instead of just clearing the
upper 32 bits.
Signed-off-by: Olaf Hering <olh@suse.de>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-03-23 20:50:59 +00:00
|
|
|
*/
|
2006-03-04 23:00:45 +00:00
|
|
|
rldicr r1,r1,0,59
|
|
|
|
|
|
powerpc: Make the 64-bit kernel as a position-independent executable
This implements CONFIG_RELOCATABLE for 64-bit by making the kernel as
a position-independent executable (PIE) when it is set. This involves
processing the dynamic relocations in the image in the early stages of
booting, even if the kernel is being run at the address it is linked at,
since the linker does not necessarily fill in words in the image for
which there are dynamic relocations. (In fact the linker does fill in
such words for 64-bit executables, though not for 32-bit executables,
so in principle we could avoid calling relocate() entirely when we're
running a 64-bit kernel at the linked address.)
The dynamic relocations are processed by a new function relocate(addr),
where the addr parameter is the virtual address where the image will be
run. In fact we call it twice; once before calling prom_init, and again
when starting the main kernel. This means that reloc_offset() returns
0 in prom_init (since it has been relocated to the address it is running
at), which necessitated a few adjustments.
This also changes __va and __pa to use an equivalent definition that is
simpler. With the relocatable kernel, PAGE_OFFSET and MEMORY_START are
constants (for 64-bit) whereas PHYSICAL_START is a variable (and
KERNELBASE ideally should be too, but isn't yet).
With this, relocatable kernels still copy themselves down to physical
address 0 and run there.
Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-08-30 01:43:47 +00:00
|
|
|
#ifdef CONFIG_RELOCATABLE
|
|
|
|
|
/* Relocate code for where we are now */
|
|
|
|
|
mr r3,r26
|
2014-02-04 05:04:35 +00:00
|
|
|
bl relocate
|
powerpc: Make the 64-bit kernel as a position-independent executable
This implements CONFIG_RELOCATABLE for 64-bit by making the kernel as
a position-independent executable (PIE) when it is set. This involves
processing the dynamic relocations in the image in the early stages of
booting, even if the kernel is being run at the address it is linked at,
since the linker does not necessarily fill in words in the image for
which there are dynamic relocations. (In fact the linker does fill in
such words for 64-bit executables, though not for 32-bit executables,
so in principle we could avoid calling relocate() entirely when we're
running a 64-bit kernel at the linked address.)
The dynamic relocations are processed by a new function relocate(addr),
where the addr parameter is the virtual address where the image will be
run. In fact we call it twice; once before calling prom_init, and again
when starting the main kernel. This means that reloc_offset() returns
0 in prom_init (since it has been relocated to the address it is running
at), which necessitated a few adjustments.
This also changes __va and __pa to use an equivalent definition that is
simpler. With the relocatable kernel, PAGE_OFFSET and MEMORY_START are
constants (for 64-bit) whereas PHYSICAL_START is a variable (and
KERNELBASE ideally should be too, but isn't yet).
With this, relocatable kernels still copy themselves down to physical
address 0 and run there.
Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-08-30 01:43:47 +00:00
|
|
|
#endif
|
|
|
|
|
|
2005-09-26 06:04:21 +00:00
|
|
|
/* Restore parameters */
|
|
|
|
|
mr r3,r31
|
|
|
|
|
mr r4,r30
|
|
|
|
|
mr r5,r29
|
|
|
|
|
mr r6,r28
|
|
|
|
|
mr r7,r27
|
|
|
|
|
|
|
|
|
|
/* Do all of the interaction with OF client interface */
|
powerpc: Make the 64-bit kernel as a position-independent executable
This implements CONFIG_RELOCATABLE for 64-bit by making the kernel as
a position-independent executable (PIE) when it is set. This involves
processing the dynamic relocations in the image in the early stages of
booting, even if the kernel is being run at the address it is linked at,
since the linker does not necessarily fill in words in the image for
which there are dynamic relocations. (In fact the linker does fill in
such words for 64-bit executables, though not for 32-bit executables,
so in principle we could avoid calling relocate() entirely when we're
running a 64-bit kernel at the linked address.)
The dynamic relocations are processed by a new function relocate(addr),
where the addr parameter is the virtual address where the image will be
run. In fact we call it twice; once before calling prom_init, and again
when starting the main kernel. This means that reloc_offset() returns
0 in prom_init (since it has been relocated to the address it is running
at), which necessitated a few adjustments.
This also changes __va and __pa to use an equivalent definition that is
simpler. With the relocatable kernel, PAGE_OFFSET and MEMORY_START are
constants (for 64-bit) whereas PHYSICAL_START is a variable (and
KERNELBASE ideally should be too, but isn't yet).
With this, relocatable kernels still copy themselves down to physical
address 0 and run there.
Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-08-30 01:43:47 +00:00
|
|
|
mr r8,r26
|
2014-02-04 05:04:35 +00:00
|
|
|
bl prom_init
|
2009-03-10 17:53:27 +00:00
|
|
|
#endif /* #CONFIG_PPC_OF_BOOT_TRAMPOLINE */
|
|
|
|
|
|
|
|
|
|
/* We never return. We also hit that trap if trying to boot
|
|
|
|
|
* from OF while CONFIG_PPC_OF_BOOT_TRAMPOLINE isn't selected */
|
2005-09-26 06:04:21 +00:00
|
|
|
trap
|
powerpc/64s: Fix section mismatch warnings from boot code
We currently have two section mismatch warnings:
The function __boot_from_prom() references
the function __init prom_init().
The function start_here_common() references
the function __init start_kernel().
The warnings are correct, we do have branches from non-init code into
init code, which is freed after boot. But we don't expect to ever
execute any of that early boot code after boot, if we did that would
be a bug. In particular calling into OF after boot would be fatal
because OF is no longer resident.
So for now fix the warnings by marking the relevant functions as
__REF, which puts them in the ".ref.text" section.
This causes some reordering of the functions in the final link:
@@ -217,10 +217,9 @@
c00000000000b088 t generic_secondary_common_init
c00000000000b124 t __mmu_off
c00000000000b14c t __start_initialization_multiplatform
-c00000000000b1ac t __boot_from_prom
-c00000000000b1ec t __after_prom_start
-c00000000000b260 t p_end
-c00000000000b27c T copy_and_flush
+c00000000000b1ac t __after_prom_start
+c00000000000b220 t p_end
+c00000000000b23c T copy_and_flush
c00000000000b300 T __secondary_start
c00000000000b300 t copy_to_here
c00000000000b344 t start_secondary_prolog
@@ -228,8 +227,9 @@
c00000000000b36c t enable_64b_mode
c00000000000b388 T relative_toc
c00000000000b3a8 t p_toc
-c00000000000b3b0 t start_here_common
-c00000000000b3d0 t start_here_multiplatform
+c00000000000b3b0 t __boot_from_prom
+c00000000000b3f0 t start_here_multiplatform
+c00000000000b480 t start_here_common
c00000000000b880 T system_call_common
c00000000000b974 t system_call
c00000000000b9dc t system_call_exit
In particular __boot_from_prom moves after copy_to_here, which means
it's not copied to zero in the first stage of copy of the kernel to
zero.
But that's OK, because we only call __boot_from_prom before we do the
copy, so it makes no difference when it's copied. The call sequence
is:
__start
-> __start_initialization_multiplatform
-> __boot_from_prom
-> __start
-> __start_initialization_multiplatform
-> __after_prom_start
-> copy_and_flush
-> copy_and_flush (relocated to 0)
-> start_here_multiplatform
-> early_setup
Reported-by: Mauricio Faria de Oliveira <mauricfo@linux.ibm.com>
Reported-by: Roman Bolshakov <r.bolshakov@yadro.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200225031328.14676-1-mpe@ellerman.id.au
2020-02-25 03:13:28 +00:00
|
|
|
.previous
|
2005-09-26 06:04:21 +00:00
|
|
|
|
2014-02-04 05:06:11 +00:00
|
|
|
__after_prom_start:
|
powerpc: Make the 64-bit kernel as a position-independent executable
This implements CONFIG_RELOCATABLE for 64-bit by making the kernel as
a position-independent executable (PIE) when it is set. This involves
processing the dynamic relocations in the image in the early stages of
booting, even if the kernel is being run at the address it is linked at,
since the linker does not necessarily fill in words in the image for
which there are dynamic relocations. (In fact the linker does fill in
such words for 64-bit executables, though not for 32-bit executables,
so in principle we could avoid calling relocate() entirely when we're
running a 64-bit kernel at the linked address.)
The dynamic relocations are processed by a new function relocate(addr),
where the addr parameter is the virtual address where the image will be
run. In fact we call it twice; once before calling prom_init, and again
when starting the main kernel. This means that reloc_offset() returns
0 in prom_init (since it has been relocated to the address it is running
at), which necessitated a few adjustments.
This also changes __va and __pa to use an equivalent definition that is
simpler. With the relocatable kernel, PAGE_OFFSET and MEMORY_START are
constants (for 64-bit) whereas PHYSICAL_START is a variable (and
KERNELBASE ideally should be too, but isn't yet).
With this, relocatable kernels still copy themselves down to physical
address 0 and run there.
Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-08-30 01:43:47 +00:00
|
|
|
#ifdef CONFIG_RELOCATABLE
|
|
|
|
|
/* process relocations for the final address of the kernel */
|
|
|
|
|
lis r25,PAGE_OFFSET@highest /* compute virtual base of kernel */
|
|
|
|
|
sldi r25,r25,32
|
2015-10-07 03:48:15 +00:00
|
|
|
#if defined(CONFIG_PPC_BOOK3E)
|
|
|
|
|
tovirt(r26,r26) /* on booke, we already run at PAGE_OFFSET */
|
|
|
|
|
#endif
|
2016-09-28 01:31:48 +00:00
|
|
|
lwz r7,(FIXED_SYMBOL_ABS_ADDR(__run_at_load))(r26)
|
2015-10-07 03:48:15 +00:00
|
|
|
#if defined(CONFIG_PPC_BOOK3E)
|
|
|
|
|
tophys(r26,r26)
|
|
|
|
|
#endif
|
2010-11-18 00:35:07 +00:00
|
|
|
cmplwi cr0,r7,1 /* flagged to stay where we are ? */
|
2008-10-21 17:38:10 +00:00
|
|
|
bne 1f
|
|
|
|
|
add r25,r25,r26
|
|
|
|
|
1: mr r3,r25
|
2014-02-04 05:04:35 +00:00
|
|
|
bl relocate
|
2015-10-07 03:48:15 +00:00
|
|
|
#if defined(CONFIG_PPC_BOOK3E)
|
|
|
|
|
/* IVPR needs to be set after relocation. */
|
|
|
|
|
bl init_core_book3e
|
|
|
|
|
#endif
|
powerpc: Make the 64-bit kernel as a position-independent executable
This implements CONFIG_RELOCATABLE for 64-bit by making the kernel as
a position-independent executable (PIE) when it is set. This involves
processing the dynamic relocations in the image in the early stages of
booting, even if the kernel is being run at the address it is linked at,
since the linker does not necessarily fill in words in the image for
which there are dynamic relocations. (In fact the linker does fill in
such words for 64-bit executables, though not for 32-bit executables,
so in principle we could avoid calling relocate() entirely when we're
running a 64-bit kernel at the linked address.)
The dynamic relocations are processed by a new function relocate(addr),
where the addr parameter is the virtual address where the image will be
run. In fact we call it twice; once before calling prom_init, and again
when starting the main kernel. This means that reloc_offset() returns
0 in prom_init (since it has been relocated to the address it is running
at), which necessitated a few adjustments.
This also changes __va and __pa to use an equivalent definition that is
simpler. With the relocatable kernel, PAGE_OFFSET and MEMORY_START are
constants (for 64-bit) whereas PHYSICAL_START is a variable (and
KERNELBASE ideally should be too, but isn't yet).
With this, relocatable kernels still copy themselves down to physical
address 0 and run there.
Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-08-30 01:43:47 +00:00
|
|
|
#endif
|
2005-09-26 06:04:21 +00:00
|
|
|
|
|
|
|
|
/*
|
2008-08-30 01:41:12 +00:00
|
|
|
* We need to run with _stext at physical address PHYSICAL_START.
|
2005-09-26 06:04:21 +00:00
|
|
|
* This will leave some code in the first 256B of
|
|
|
|
|
* real memory, which are reserved for software use.
|
|
|
|
|
*
|
|
|
|
|
* Note: This process overwrites the OF exception vectors.
|
|
|
|
|
*/
|
powerpc: Make the 64-bit kernel as a position-independent executable
This implements CONFIG_RELOCATABLE for 64-bit by making the kernel as
a position-independent executable (PIE) when it is set. This involves
processing the dynamic relocations in the image in the early stages of
booting, even if the kernel is being run at the address it is linked at,
since the linker does not necessarily fill in words in the image for
which there are dynamic relocations. (In fact the linker does fill in
such words for 64-bit executables, though not for 32-bit executables,
so in principle we could avoid calling relocate() entirely when we're
running a 64-bit kernel at the linked address.)
The dynamic relocations are processed by a new function relocate(addr),
where the addr parameter is the virtual address where the image will be
run. In fact we call it twice; once before calling prom_init, and again
when starting the main kernel. This means that reloc_offset() returns
0 in prom_init (since it has been relocated to the address it is running
at), which necessitated a few adjustments.
This also changes __va and __pa to use an equivalent definition that is
simpler. With the relocatable kernel, PAGE_OFFSET and MEMORY_START are
constants (for 64-bit) whereas PHYSICAL_START is a variable (and
KERNELBASE ideally should be too, but isn't yet).
With this, relocatable kernels still copy themselves down to physical
address 0 and run there.
Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-08-30 01:43:47 +00:00
|
|
|
li r3,0 /* target addr */
|
2009-07-23 23:15:59 +00:00
|
|
|
#ifdef CONFIG_PPC_BOOK3E
|
2015-10-07 03:48:14 +00:00
|
|
|
tovirt(r3,r3) /* on booke, we already run at PAGE_OFFSET */
|
2009-07-23 23:15:59 +00:00
|
|
|
#endif
|
powerpc: Make the 64-bit kernel as a position-independent executable
This implements CONFIG_RELOCATABLE for 64-bit by making the kernel as
a position-independent executable (PIE) when it is set. This involves
processing the dynamic relocations in the image in the early stages of
booting, even if the kernel is being run at the address it is linked at,
since the linker does not necessarily fill in words in the image for
which there are dynamic relocations. (In fact the linker does fill in
such words for 64-bit executables, though not for 32-bit executables,
so in principle we could avoid calling relocate() entirely when we're
running a 64-bit kernel at the linked address.)
The dynamic relocations are processed by a new function relocate(addr),
where the addr parameter is the virtual address where the image will be
run. In fact we call it twice; once before calling prom_init, and again
when starting the main kernel. This means that reloc_offset() returns
0 in prom_init (since it has been relocated to the address it is running
at), which necessitated a few adjustments.
This also changes __va and __pa to use an equivalent definition that is
simpler. With the relocatable kernel, PAGE_OFFSET and MEMORY_START are
constants (for 64-bit) whereas PHYSICAL_START is a variable (and
KERNELBASE ideally should be too, but isn't yet).
With this, relocatable kernels still copy themselves down to physical
address 0 and run there.
Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-08-30 01:43:47 +00:00
|
|
|
mr. r4,r26 /* In some cases the loader may */
|
2015-10-07 03:48:14 +00:00
|
|
|
#if defined(CONFIG_PPC_BOOK3E)
|
|
|
|
|
tovirt(r4,r4)
|
|
|
|
|
#endif
|
2008-08-30 01:41:12 +00:00
|
|
|
beq 9f /* have already put us at zero */
|
2005-09-26 06:04:21 +00:00
|
|
|
li r6,0x100 /* Start offset, the first 0x100 */
|
|
|
|
|
/* bytes were copied earlier. */
|
|
|
|
|
|
2012-11-11 19:01:05 +00:00
|
|
|
#ifdef CONFIG_RELOCATABLE
|
2008-10-21 17:38:10 +00:00
|
|
|
/*
|
|
|
|
|
* Check if the kernel has to be running as relocatable kernel based on the
|
2008-10-23 18:41:09 +00:00
|
|
|
* variable __run_at_load, if it is set the kernel is treated as relocatable
|
2008-10-21 17:38:10 +00:00
|
|
|
* kernel, otherwise it will be moved to PHYSICAL_START
|
|
|
|
|
*/
|
2015-10-07 03:48:15 +00:00
|
|
|
#if defined(CONFIG_PPC_BOOK3E)
|
|
|
|
|
tovirt(r26,r26) /* on booke, we already run at PAGE_OFFSET */
|
|
|
|
|
#endif
|
2016-09-28 01:31:48 +00:00
|
|
|
lwz r7,(FIXED_SYMBOL_ABS_ADDR(__run_at_load))(r26)
|
2008-10-23 18:41:09 +00:00
|
|
|
cmplwi cr0,r7,1
|
2008-10-21 17:38:10 +00:00
|
|
|
bne 3f
|
|
|
|
|
|
2015-10-07 03:48:15 +00:00
|
|
|
#ifdef CONFIG_PPC_BOOK3E
|
|
|
|
|
LOAD_REG_ADDR(r5, __end_interrupts)
|
|
|
|
|
LOAD_REG_ADDR(r11, _stext)
|
|
|
|
|
sub r5,r5,r11
|
|
|
|
|
#else
|
2012-11-02 06:21:43 +00:00
|
|
|
/* just copy interrupts */
|
2019-08-20 14:34:14 +00:00
|
|
|
LOAD_REG_IMMEDIATE_SYM(r5, r11, FIXED_SYMBOL_ABS_ADDR(__end_interrupts))
|
2015-10-07 03:48:15 +00:00
|
|
|
#endif
|
2008-10-21 17:38:10 +00:00
|
|
|
b 5f
|
|
|
|
|
3:
|
|
|
|
|
#endif
|
2016-09-28 01:31:48 +00:00
|
|
|
/* # bytes of memory to copy */
|
|
|
|
|
lis r5,(ABS_ADDR(copy_to_here))@ha
|
|
|
|
|
addi r5,r5,(ABS_ADDR(copy_to_here))@l
|
2008-10-21 17:38:10 +00:00
|
|
|
|
2014-02-04 05:04:35 +00:00
|
|
|
bl copy_and_flush /* copy the first n bytes */
|
2005-09-26 06:04:21 +00:00
|
|
|
/* this includes the code being */
|
|
|
|
|
/* executed here. */
|
2016-09-28 01:31:48 +00:00
|
|
|
/* Jump to the copy of this code that we just made */
|
|
|
|
|
addis r8,r3,(ABS_ADDR(4f))@ha
|
|
|
|
|
addi r12,r8,(ABS_ADDR(4f))@l
|
2014-02-04 05:07:47 +00:00
|
|
|
mtctr r12
|
2005-09-26 06:04:21 +00:00
|
|
|
bctr
|
|
|
|
|
|
2013-12-23 01:19:51 +00:00
|
|
|
.balign 8
|
2017-03-09 05:42:12 +00:00
|
|
|
p_end: .8byte _end - copy_to_here
|
2008-10-21 17:38:10 +00:00
|
|
|
|
2016-09-28 01:31:47 +00:00
|
|
|
4:
|
|
|
|
|
/*
|
|
|
|
|
* Now copy the rest of the kernel up to _end, add
|
|
|
|
|
* _end - copy_to_here to the copy limit and run again.
|
|
|
|
|
*/
|
2016-09-28 01:31:48 +00:00
|
|
|
addis r8,r26,(ABS_ADDR(p_end))@ha
|
|
|
|
|
ld r8,(ABS_ADDR(p_end))@l(r8)
|
2016-09-28 01:31:47 +00:00
|
|
|
add r5,r5,r8
|
2014-02-04 05:04:35 +00:00
|
|
|
5: bl copy_and_flush /* copy the rest */
|
2008-08-30 01:41:12 +00:00
|
|
|
|
2014-02-04 05:04:35 +00:00
|
|
|
9: b start_here_multiplatform
|
2008-08-30 01:41:12 +00:00
|
|
|
|
2005-09-26 06:04:21 +00:00
|
|
|
/*
|
|
|
|
|
* Copy routine used to copy the kernel to start at physical address 0
|
|
|
|
|
* and flush and invalidate the caches as needed.
|
|
|
|
|
* r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset
|
|
|
|
|
* on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5.
|
|
|
|
|
*
|
|
|
|
|
* Note: this routine *only* clobbers r0, r6 and lr
|
|
|
|
|
*/
|
|
|
|
|
_GLOBAL(copy_and_flush)
|
|
|
|
|
addi r5,r5,-8
|
|
|
|
|
addi r6,r6,-8
|
2006-09-06 19:34:41 +00:00
|
|
|
4: li r0,8 /* Use the smallest common */
|
2005-09-26 06:04:21 +00:00
|
|
|
/* denominator cache line */
|
|
|
|
|
/* size. This results in */
|
|
|
|
|
/* extra cache line flushes */
|
|
|
|
|
/* but operation is correct. */
|
|
|
|
|
/* Can't get cache line size */
|
|
|
|
|
/* from NACA as it is being */
|
|
|
|
|
/* moved too. */
|
|
|
|
|
|
|
|
|
|
mtctr r0 /* put # words/line in ctr */
|
|
|
|
|
3: addi r6,r6,8 /* copy a cache line */
|
|
|
|
|
ldx r0,r6,r4
|
|
|
|
|
stdx r0,r6,r3
|
|
|
|
|
bdnz 3b
|
|
|
|
|
dcbst r6,r3 /* write it to memory */
|
|
|
|
|
sync
|
|
|
|
|
icbi r6,r3 /* flush the icache line */
|
|
|
|
|
cmpld 0,r6,r5
|
|
|
|
|
blt 4b
|
|
|
|
|
sync
|
|
|
|
|
addi r5,r5,8
|
|
|
|
|
addi r6,r6,8
|
2013-04-24 00:30:09 +00:00
|
|
|
isync
|
2005-09-26 06:04:21 +00:00
|
|
|
blr
|
|
|
|
|
|
|
|
|
|
.align 8
|
|
|
|
|
copy_to_here:
|
|
|
|
|
|
|
|
|
|
#ifdef CONFIG_SMP
|
|
|
|
|
#ifdef CONFIG_PPC_PMAC
|
|
|
|
|
/*
|
|
|
|
|
* On PowerMac, secondary processors starts from the reset vector, which
|
|
|
|
|
* is temporarily turned into a call to one of the functions below.
|
|
|
|
|
*/
|
|
|
|
|
.section ".text";
|
|
|
|
|
.align 2 ;
|
|
|
|
|
|
2005-10-22 06:02:39 +00:00
|
|
|
.globl __secondary_start_pmac_0
|
|
|
|
|
__secondary_start_pmac_0:
|
|
|
|
|
/* NB the entries for cpus 0, 1, 2 must each occupy 8 bytes. */
|
|
|
|
|
li r24,0
|
|
|
|
|
b 1f
|
|
|
|
|
li r24,1
|
|
|
|
|
b 1f
|
|
|
|
|
li r24,2
|
|
|
|
|
b 1f
|
|
|
|
|
li r24,3
|
|
|
|
|
1:
|
2005-09-26 06:04:21 +00:00
|
|
|
|
|
|
|
|
_GLOBAL(pmac_secondary_start)
|
|
|
|
|
/* turn on 64-bit mode */
|
2014-02-04 05:04:35 +00:00
|
|
|
bl enable_64b_mode
|
2005-09-26 06:04:21 +00:00
|
|
|
|
2009-01-11 19:03:45 +00:00
|
|
|
li r0,0
|
|
|
|
|
mfspr r3,SPRN_HID4
|
|
|
|
|
rldimi r3,r0,40,23 /* clear bit 23 (rm_ci) */
|
|
|
|
|
sync
|
|
|
|
|
mtspr SPRN_HID4,r3
|
|
|
|
|
isync
|
|
|
|
|
sync
|
|
|
|
|
slbia
|
|
|
|
|
|
2008-08-30 01:41:12 +00:00
|
|
|
/* get TOC pointer (real address) */
|
2014-02-04 05:04:35 +00:00
|
|
|
bl relative_toc
|
2012-11-26 17:41:08 +00:00
|
|
|
tovirt(r2,r2)
|
2008-08-30 01:41:12 +00:00
|
|
|
|
2005-09-26 06:04:21 +00:00
|
|
|
/* Copy some CPU settings from CPU 0 */
|
2014-02-04 05:04:35 +00:00
|
|
|
bl __restore_cpu_ppc970
|
2005-09-26 06:04:21 +00:00
|
|
|
|
|
|
|
|
/* pSeries do that early though I don't think we really need it */
|
|
|
|
|
mfmsr r3
|
|
|
|
|
ori r3,r3,MSR_RI
|
|
|
|
|
mtmsrd r3 /* RI on */
|
|
|
|
|
|
|
|
|
|
/* Set up a paca value for this processor. */
|
2018-02-13 15:08:12 +00:00
|
|
|
LOAD_REG_ADDR(r4,paca_ptrs) /* Load paca pointer */
|
|
|
|
|
ld r4,0(r4) /* Get base vaddr of paca_ptrs array */
|
|
|
|
|
sldi r5,r24,3 /* get paca_ptrs[] index from cpu id */
|
|
|
|
|
ldx r13,r5,r4 /* r13 = paca_ptrs[cpu id] */
|
2011-01-20 06:50:21 +00:00
|
|
|
SET_PACA(r13) /* Save vaddr of paca in an SPRG*/
|
2005-09-26 06:04:21 +00:00
|
|
|
|
2011-02-21 05:49:58 +00:00
|
|
|
/* Mark interrupts soft and hard disabled (they might be enabled
|
|
|
|
|
* in the PACA when doing hotplug)
|
|
|
|
|
*/
|
2017-12-20 03:55:42 +00:00
|
|
|
li r0,IRQS_DISABLED
|
2017-12-20 03:55:50 +00:00
|
|
|
stb r0,PACAIRQSOFTMASK(r13)
|
powerpc: Rework lazy-interrupt handling
The current implementation of lazy interrupts handling has some
issues that this tries to address.
We don't do the various workarounds we need to do when re-enabling
interrupts in some cases such as when returning from an interrupt
and thus we may still lose or get delayed decrementer or doorbell
interrupts.
The current scheme also makes it much harder to handle the external
"edge" interrupts provided by some BookE processors when using the
EPR facility (External Proxy) and the Freescale Hypervisor.
Additionally, we tend to keep interrupts hard disabled in a number
of cases, such as decrementer interrupts, external interrupts, or
when a masked decrementer interrupt is pending. This is sub-optimal.
This is an attempt at fixing it all in one go by reworking the way
we do the lazy interrupt disabling from the ground up.
The base idea is to replace the "hard_enabled" field with a
"irq_happened" field in which we store a bit mask of what interrupt
occurred while soft-disabled.
When re-enabling, either via arch_local_irq_restore() or when returning
from an interrupt, we can now decide what to do by testing bits in that
field.
We then implement replaying of the missed interrupts either by
re-using the existing exception frame (in exception exit case) or via
the creation of a new one from an assembly trampoline (in the
arch_local_irq_enable case).
This removes the need to play with the decrementer to try to create
fake interrupts, among others.
In addition, this adds a few refinements:
- We no longer hard disable decrementer interrupts that occur
while soft-disabled. We now simply bump the decrementer back to max
(on BookS) or leave it stopped (on BookE) and continue with hard interrupts
enabled, which means that we'll potentially get better sample quality from
performance monitor interrupts.
- Timer, decrementer and doorbell interrupts now hard-enable
shortly after removing the source of the interrupt, which means
they no longer run entirely hard disabled. Again, this will improve
perf sample quality.
- On Book3E 64-bit, we now make the performance monitor interrupt
act as an NMI like Book3S (the necessary C code for that to work
appear to already be present in the FSL perf code, notably calling
nmi_enter instead of irq_enter). (This also fixes a bug where BookE
perfmon interrupts could clobber r14 ... oops)
- We could make "masked" decrementer interrupts act as NMIs when doing
timer-based perf sampling to improve the sample quality.
Signed-off-by-yet: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
v2:
- Add hard-enable to decrementer, timer and doorbells
- Fix CR clobber in masked irq handling on BookE
- Make embedded perf interrupt act as an NMI
- Add a PACA_HAPPENED_EE_EDGE for use by FSL if they want
to retrigger an interrupt without preventing hard-enable
v3:
- Fix or vs. ori bug on Book3E
- Fix enabling of interrupts for some exceptions on Book3E
v4:
- Fix resend of doorbells on return from interrupt on Book3E
v5:
- Rebased on top of my latest series, which involves some significant
rework of some aspects of the patch.
v6:
- 32-bit compile fix
- more compile fixes with various .config combos
- factor out the asm code to soft-disable interrupts
- remove the C wrapper around preempt_schedule_irq
v7:
- Fix a bug with hard irq state tracking on native power7
2012-03-06 07:27:59 +00:00
|
|
|
li r0,PACA_IRQ_HARD_DIS
|
|
|
|
|
stb r0,PACAIRQHAPPENED(r13)
|
2011-02-21 05:49:58 +00:00
|
|
|
|
2005-09-26 06:04:21 +00:00
|
|
|
/* Create a temp kernel stack for use before relocation is on. */
|
|
|
|
|
ld r1,PACAEMERGSP(r13)
|
|
|
|
|
subi r1,r1,STACK_FRAME_OVERHEAD
|
|
|
|
|
|
2006-11-27 03:59:50 +00:00
|
|
|
b __secondary_start
|
2005-09-26 06:04:21 +00:00
|
|
|
|
|
|
|
|
#endif /* CONFIG_PPC_PMAC */
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* This function is called after the master CPU has released the
|
|
|
|
|
* secondary processors. The execution environment is relocation off.
|
|
|
|
|
* The paca for this processor has the following fields initialized at
|
|
|
|
|
* this point:
|
|
|
|
|
* 1. Processor number
|
|
|
|
|
* 2. Segment table pointer (virtual address)
|
|
|
|
|
* On entry the following are set:
|
2012-02-28 02:44:58 +00:00
|
|
|
* r1 = stack pointer (real addr of temp stack)
|
2009-07-14 20:52:54 +00:00
|
|
|
* r24 = cpu# (in Linux terms)
|
|
|
|
|
* r13 = paca virtual address
|
|
|
|
|
* SPRG_PACA = paca virtual address
|
2005-09-26 06:04:21 +00:00
|
|
|
*/
|
2009-07-23 23:15:59 +00:00
|
|
|
.section ".text";
|
|
|
|
|
.align 2 ;
|
|
|
|
|
|
2007-08-22 03:44:58 +00:00
|
|
|
.globl __secondary_start
|
2006-11-27 03:59:50 +00:00
|
|
|
__secondary_start:
|
2005-11-10 02:37:51 +00:00
|
|
|
/* Set thread priority to MEDIUM */
|
|
|
|
|
HMT_MEDIUM
|
2005-09-26 06:04:21 +00:00
|
|
|
|
2019-02-22 12:58:21 +00:00
|
|
|
/*
|
|
|
|
|
* Do early setup for this CPU, in particular initialising the MMU so we
|
|
|
|
|
* can turn it on below. This is a call to C, which is OK, we're still
|
|
|
|
|
* running on the emergency stack.
|
|
|
|
|
*/
|
2014-02-04 05:04:35 +00:00
|
|
|
bl early_setup_secondary
|
2010-08-12 20:58:28 +00:00
|
|
|
|
2010-08-25 21:04:25 +00:00
|
|
|
/*
|
2019-02-22 12:58:21 +00:00
|
|
|
* The primary has initialized our kernel stack for us in the paca, grab
|
|
|
|
|
* it and put it in r1. We must *not* use it until we turn on the MMU
|
|
|
|
|
* below, because it may not be inside the RMO.
|
2010-08-25 21:04:25 +00:00
|
|
|
*/
|
2019-02-22 12:58:21 +00:00
|
|
|
ld r1, PACAKSAVE(r13)
|
2010-08-25 21:04:25 +00:00
|
|
|
|
2005-11-10 02:37:51 +00:00
|
|
|
/* Clear backchain so we get nice backtraces */
|
2005-09-26 06:04:21 +00:00
|
|
|
li r7,0
|
|
|
|
|
mtlr r7
|
|
|
|
|
|
powerpc: Rework lazy-interrupt handling
The current implementation of lazy interrupts handling has some
issues that this tries to address.
We don't do the various workarounds we need to do when re-enabling
interrupts in some cases such as when returning from an interrupt
and thus we may still lose or get delayed decrementer or doorbell
interrupts.
The current scheme also makes it much harder to handle the external
"edge" interrupts provided by some BookE processors when using the
EPR facility (External Proxy) and the Freescale Hypervisor.
Additionally, we tend to keep interrupts hard disabled in a number
of cases, such as decrementer interrupts, external interrupts, or
when a masked decrementer interrupt is pending. This is sub-optimal.
This is an attempt at fixing it all in one go by reworking the way
we do the lazy interrupt disabling from the ground up.
The base idea is to replace the "hard_enabled" field with a
"irq_happened" field in which we store a bit mask of what interrupt
occurred while soft-disabled.
When re-enabling, either via arch_local_irq_restore() or when returning
from an interrupt, we can now decide what to do by testing bits in that
field.
We then implement replaying of the missed interrupts either by
re-using the existing exception frame (in exception exit case) or via
the creation of a new one from an assembly trampoline (in the
arch_local_irq_enable case).
This removes the need to play with the decrementer to try to create
fake interrupts, among others.
In addition, this adds a few refinements:
- We no longer hard disable decrementer interrupts that occur
while soft-disabled. We now simply bump the decrementer back to max
(on BookS) or leave it stopped (on BookE) and continue with hard interrupts
enabled, which means that we'll potentially get better sample quality from
performance monitor interrupts.
- Timer, decrementer and doorbell interrupts now hard-enable
shortly after removing the source of the interrupt, which means
they no longer run entirely hard disabled. Again, this will improve
perf sample quality.
- On Book3E 64-bit, we now make the performance monitor interrupt
act as an NMI like Book3S (the necessary C code for that to work
appear to already be present in the FSL perf code, notably calling
nmi_enter instead of irq_enter). (This also fixes a bug where BookE
perfmon interrupts could clobber r14 ... oops)
- We could make "masked" decrementer interrupts act as NMIs when doing
timer-based perf sampling to improve the sample quality.
Signed-off-by-yet: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
v2:
- Add hard-enable to decrementer, timer and doorbells
- Fix CR clobber in masked irq handling on BookE
- Make embedded perf interrupt act as an NMI
- Add a PACA_HAPPENED_EE_EDGE for use by FSL if they want
to retrigger an interrupt without preventing hard-enable
v3:
- Fix or vs. ori bug on Book3E
- Fix enabling of interrupts for some exceptions on Book3E
v4:
- Fix resend of doorbells on return from interrupt on Book3E
v5:
- Rebased on top of my latest series, which involves some significant
rework of some aspects of the patch.
v6:
- 32-bit compile fix
- more compile fixes with various .config combos
- factor out the asm code to soft-disable interrupts
- remove the C wrapper around preempt_schedule_irq
v7:
- Fix a bug with hard irq state tracking on native power7
2012-03-06 07:27:59 +00:00
|
|
|
/* Mark interrupts soft and hard disabled (they might be enabled
|
|
|
|
|
* in the PACA when doing hotplug)
|
|
|
|
|
*/
|
2017-12-20 03:55:42 +00:00
|
|
|
li r7,IRQS_DISABLED
|
2017-12-20 03:55:50 +00:00
|
|
|
stb r7,PACAIRQSOFTMASK(r13)
|
powerpc: Rework lazy-interrupt handling
The current implementation of lazy interrupts handling has some
issues that this tries to address.
We don't do the various workarounds we need to do when re-enabling
interrupts in some cases such as when returning from an interrupt
and thus we may still lose or get delayed decrementer or doorbell
interrupts.
The current scheme also makes it much harder to handle the external
"edge" interrupts provided by some BookE processors when using the
EPR facility (External Proxy) and the Freescale Hypervisor.
Additionally, we tend to keep interrupts hard disabled in a number
of cases, such as decrementer interrupts, external interrupts, or
when a masked decrementer interrupt is pending. This is sub-optimal.
This is an attempt at fixing it all in one go by reworking the way
we do the lazy interrupt disabling from the ground up.
The base idea is to replace the "hard_enabled" field with a
"irq_happened" field in which we store a bit mask of what interrupt
occurred while soft-disabled.
When re-enabling, either via arch_local_irq_restore() or when returning
from an interrupt, we can now decide what to do by testing bits in that
field.
We then implement replaying of the missed interrupts either by
re-using the existing exception frame (in exception exit case) or via
the creation of a new one from an assembly trampoline (in the
arch_local_irq_enable case).
This removes the need to play with the decrementer to try to create
fake interrupts, among others.
In addition, this adds a few refinements:
- We no longer hard disable decrementer interrupts that occur
while soft-disabled. We now simply bump the decrementer back to max
(on BookS) or leave it stopped (on BookE) and continue with hard interrupts
enabled, which means that we'll potentially get better sample quality from
performance monitor interrupts.
- Timer, decrementer and doorbell interrupts now hard-enable
shortly after removing the source of the interrupt, which means
they no longer run entirely hard disabled. Again, this will improve
perf sample quality.
- On Book3E 64-bit, we now make the performance monitor interrupt
act as an NMI like Book3S (the necessary C code for that to work
appear to already be present in the FSL perf code, notably calling
nmi_enter instead of irq_enter). (This also fixes a bug where BookE
perfmon interrupts could clobber r14 ... oops)
- We could make "masked" decrementer interrupts act as NMIs when doing
timer-based perf sampling to improve the sample quality.
Signed-off-by-yet: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
v2:
- Add hard-enable to decrementer, timer and doorbells
- Fix CR clobber in masked irq handling on BookE
- Make embedded perf interrupt act as an NMI
- Add a PACA_HAPPENED_EE_EDGE for use by FSL if they want
to retrigger an interrupt without preventing hard-enable
v3:
- Fix or vs. ori bug on Book3E
- Fix enabling of interrupts for some exceptions on Book3E
v4:
- Fix resend of doorbells on return from interrupt on Book3E
v5:
- Rebased on top of my latest series, which involves some significant
rework of some aspects of the patch.
v6:
- 32-bit compile fix
- more compile fixes with various .config combos
- factor out the asm code to soft-disable interrupts
- remove the C wrapper around preempt_schedule_irq
v7:
- Fix a bug with hard irq state tracking on native power7
2012-03-06 07:27:59 +00:00
|
|
|
li r0,PACA_IRQ_HARD_DIS
|
|
|
|
|
stb r0,PACAIRQHAPPENED(r13)
|
2012-02-28 02:44:58 +00:00
|
|
|
|
2005-09-26 06:04:21 +00:00
|
|
|
/* enable MMU and jump to start_secondary */
|
2014-02-04 05:04:52 +00:00
|
|
|
LOAD_REG_ADDR(r3, start_secondary_prolog)
|
2006-01-13 03:56:25 +00:00
|
|
|
LOAD_REG_IMMEDIATE(r4, MSR_KERNEL)
|
[POWERPC] Lazy interrupt disabling for 64-bit machines
This implements a lazy strategy for disabling interrupts. This means
that local_irq_disable() et al. just clear the 'interrupts are
enabled' flag in the paca. If an interrupt comes along, the interrupt
entry code notices that interrupts are supposed to be disabled, and
clears the EE bit in SRR1, clears the 'interrupts are hard-enabled'
flag in the paca, and returns. This means that interrupts only
actually get disabled in the processor when an interrupt comes along.
When interrupts are enabled by local_irq_enable() et al., the code
sets the interrupts-enabled flag in the paca, and then checks whether
interrupts got hard-disabled. If so, it also sets the EE bit in the
MSR to hard-enable the interrupts.
This has the potential to improve performance, and also makes it
easier to make a kernel that can boot on iSeries and on other 64-bit
machines, since this lazy-disable strategy is very similar to the
soft-disable strategy that iSeries already uses.
This version renames paca->proc_enabled to paca->soft_enabled, and
changes a couple of soft-disables in the kexec code to hard-disables,
which should fix the crash that Michael Ellerman saw. This doesn't
yet use a reserved CR field for the soft_enabled and hard_enabled
flags. This applies on top of Stephen Rothwell's patches to make it
possible to build a combined iSeries/other kernel.
Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-10-04 06:47:49 +00:00
|
|
|
|
2005-10-10 04:01:07 +00:00
|
|
|
mtspr SPRN_SRR0,r3
|
|
|
|
|
mtspr SPRN_SRR1,r4
|
2009-07-23 23:15:59 +00:00
|
|
|
RFI
|
2005-09-26 06:04:21 +00:00
|
|
|
b . /* prevent speculative execution */
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Running with relocation on at this point. All we want to do is
|
2008-08-30 01:41:12 +00:00
|
|
|
* zero the stack back-chain pointer and get the TOC virtual address
|
|
|
|
|
* before going into C code.
|
2005-09-26 06:04:21 +00:00
|
|
|
*/
|
2014-02-04 05:04:52 +00:00
|
|
|
start_secondary_prolog:
|
2008-08-30 01:41:12 +00:00
|
|
|
ld r2,PACATOC(r13)
|
2005-09-26 06:04:21 +00:00
|
|
|
li r3,0
|
|
|
|
|
std r3,0(r1) /* Zero the stack frame pointer */
|
2014-02-04 05:04:35 +00:00
|
|
|
bl start_secondary
|
2005-11-10 02:37:51 +00:00
|
|
|
b .
|
2010-03-01 02:58:09 +00:00
|
|
|
/*
|
|
|
|
|
* Reset stack pointer and call start_secondary
|
|
|
|
|
* to continue with online operation when woken up
|
|
|
|
|
* from cede in cpu offline.
|
|
|
|
|
*/
|
|
|
|
|
_GLOBAL(start_secondary_resume)
|
|
|
|
|
ld r1,PACAKSAVE(r13) /* Reload kernel stack pointer */
|
|
|
|
|
li r3,0
|
|
|
|
|
std r3,0(r1) /* Zero the stack frame pointer */
|
2014-02-04 05:04:35 +00:00
|
|
|
bl start_secondary
|
2010-03-01 02:58:09 +00:00
|
|
|
b .
|
2005-09-26 06:04:21 +00:00
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* This subroutine clobbers r11 and r12
|
|
|
|
|
*/
|
2014-02-04 05:06:11 +00:00
|
|
|
enable_64b_mode:
|
2005-09-26 06:04:21 +00:00
|
|
|
mfmsr r11 /* grab the current MSR */
|
2009-07-23 23:15:59 +00:00
|
|
|
#ifdef CONFIG_PPC_BOOK3E
|
|
|
|
|
oris r11,r11,0x8000 /* CM bit set, we'll set ICM later */
|
|
|
|
|
mtmsr r11
|
|
|
|
|
#else /* CONFIG_PPC_BOOK3E */
|
2011-04-07 21:56:03 +00:00
|
|
|
li r12,(MSR_64BIT | MSR_ISF)@highest
|
2008-08-30 01:41:12 +00:00
|
|
|
sldi r12,r12,48
|
2005-09-26 06:04:21 +00:00
|
|
|
or r11,r11,r12
|
|
|
|
|
mtmsrd r11
|
|
|
|
|
isync
|
2009-07-23 23:15:59 +00:00
|
|
|
#endif
|
2005-09-26 06:04:21 +00:00
|
|
|
blr
|
|
|
|
|
|
2008-08-30 01:41:12 +00:00
|
|
|
/*
|
|
|
|
|
* This puts the TOC pointer into r2, offset by 0x8000 (as expected
|
|
|
|
|
* by the toolchain). It computes the correct value for wherever we
|
|
|
|
|
* are running at the moment, using position-independent code.
|
2012-11-26 17:41:08 +00:00
|
|
|
*
|
|
|
|
|
* Note: The compiler constructs pointers using offsets from the
|
|
|
|
|
* TOC in -mcmodel=medium mode. After we relocate to 0 but before
|
|
|
|
|
* the MMU is on we need our TOC to be a virtual address otherwise
|
|
|
|
|
* these pointers will be real addresses which may get stored and
|
|
|
|
|
* accessed later with the MMU on. We use tovirt() at the call
|
|
|
|
|
* sites to handle this.
|
2008-08-30 01:41:12 +00:00
|
|
|
*/
|
|
|
|
|
_GLOBAL(relative_toc)
|
|
|
|
|
mflr r0
|
|
|
|
|
bcl 20,31,$+4
|
2011-09-19 17:44:51 +00:00
|
|
|
0: mflr r11
|
|
|
|
|
ld r2,(p_toc - 0b)(r11)
|
|
|
|
|
add r2,r2,r11
|
2008-08-30 01:41:12 +00:00
|
|
|
mtlr r0
|
|
|
|
|
blr
|
|
|
|
|
|
2013-08-06 16:01:18 +00:00
|
|
|
.balign 8
|
2017-03-09 05:42:12 +00:00
|
|
|
p_toc: .8byte __toc_start + 0x8000 - 0b
|
2008-08-30 01:41:12 +00:00
|
|
|
|
2005-09-26 06:04:21 +00:00
|
|
|
/*
|
|
|
|
|
* This is where the main kernel code starts.
|
|
|
|
|
*/
|
2019-05-10 06:31:28 +00:00
|
|
|
__REF
|
2014-02-04 05:06:11 +00:00
|
|
|
start_here_multiplatform:
|
2012-11-26 17:41:08 +00:00
|
|
|
/* set up the TOC */
|
2014-02-04 05:04:35 +00:00
|
|
|
bl relative_toc
|
2012-11-26 17:41:08 +00:00
|
|
|
tovirt(r2,r2)
|
2005-09-26 06:04:21 +00:00
|
|
|
|
|
|
|
|
/* Clear out the BSS. It may have been done in prom_init,
|
|
|
|
|
* already but that's irrelevant since prom_init will soon
|
|
|
|
|
* be detached from the kernel completely. Besides, we need
|
|
|
|
|
* to clear it now for kexec-style entry.
|
|
|
|
|
*/
|
2008-08-30 01:41:12 +00:00
|
|
|
LOAD_REG_ADDR(r11,__bss_stop)
|
|
|
|
|
LOAD_REG_ADDR(r8,__bss_start)
|
2005-09-26 06:04:21 +00:00
|
|
|
sub r11,r11,r8 /* bss size */
|
|
|
|
|
addi r11,r11,7 /* round up to an even double word */
|
2008-08-30 01:41:12 +00:00
|
|
|
srdi. r11,r11,3 /* shift right by 3 */
|
2005-09-26 06:04:21 +00:00
|
|
|
beq 4f
|
|
|
|
|
addi r8,r8,-8
|
|
|
|
|
li r0,0
|
|
|
|
|
mtctr r11 /* zero this many doublewords */
|
|
|
|
|
3: stdu r0,8(r8)
|
|
|
|
|
bdnz 3b
|
|
|
|
|
4:
|
|
|
|
|
|
2011-09-19 17:44:59 +00:00
|
|
|
#ifdef CONFIG_PPC_EARLY_DEBUG_OPAL
|
|
|
|
|
/* Setup OPAL entry */
|
2012-10-21 14:30:52 +00:00
|
|
|
LOAD_REG_ADDR(r11, opal)
|
2011-09-19 17:44:59 +00:00
|
|
|
std r28,0(r11);
|
|
|
|
|
std r29,8(r11);
|
|
|
|
|
#endif
|
|
|
|
|
|
2009-07-23 23:15:59 +00:00
|
|
|
#ifndef CONFIG_PPC_BOOK3E
|
2005-09-26 06:04:21 +00:00
|
|
|
mfmsr r6
|
|
|
|
|
ori r6,r6,MSR_RI
|
|
|
|
|
mtmsrd r6 /* RI on */
|
2009-07-23 23:15:59 +00:00
|
|
|
#endif
|
2005-09-26 06:04:21 +00:00
|
|
|
|
powerpc: Make the 64-bit kernel as a position-independent executable
This implements CONFIG_RELOCATABLE for 64-bit by making the kernel as
a position-independent executable (PIE) when it is set. This involves
processing the dynamic relocations in the image in the early stages of
booting, even if the kernel is being run at the address it is linked at,
since the linker does not necessarily fill in words in the image for
which there are dynamic relocations. (In fact the linker does fill in
such words for 64-bit executables, though not for 32-bit executables,
so in principle we could avoid calling relocate() entirely when we're
running a 64-bit kernel at the linked address.)
The dynamic relocations are processed by a new function relocate(addr),
where the addr parameter is the virtual address where the image will be
run. In fact we call it twice; once before calling prom_init, and again
when starting the main kernel. This means that reloc_offset() returns
0 in prom_init (since it has been relocated to the address it is running
at), which necessitated a few adjustments.
This also changes __va and __pa to use an equivalent definition that is
simpler. With the relocatable kernel, PAGE_OFFSET and MEMORY_START are
constants (for 64-bit) whereas PHYSICAL_START is a variable (and
KERNELBASE ideally should be too, but isn't yet).
With this, relocatable kernels still copy themselves down to physical
address 0 and run there.
Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-08-30 01:43:47 +00:00
|
|
|
#ifdef CONFIG_RELOCATABLE
|
|
|
|
|
/* Save the physical address we're running at in kernstart_addr */
|
|
|
|
|
LOAD_REG_ADDR(r4, kernstart_addr)
|
|
|
|
|
clrldi r0,r25,2
|
|
|
|
|
std r0,0(r4)
|
|
|
|
|
#endif
|
|
|
|
|
|
2008-08-30 01:41:12 +00:00
|
|
|
/* set up a stack pointer */
|
powerpc/64: Don't initialise init_task->thread.regs
Aneesh increased the size of struct pt_regs by 16 bytes and started
seeing this WARN_ON:
smp: Bringing up secondary CPUs ...
------------[ cut here ]------------
WARNING: CPU: 0 PID: 0 at arch/powerpc/kernel/process.c:455 giveup_all+0xb4/0x110
Modules linked in:
CPU: 0 PID: 0 Comm: swapper/0 Not tainted 5.7.0-rc2-gcc-8.2.0-1.g8f6a41f-default+ #318
NIP: c00000000001a2b4 LR: c00000000001a29c CTR: c0000000031d0000
REGS: c0000000026d3980 TRAP: 0700 Not tainted (5.7.0-rc2-gcc-8.2.0-1.g8f6a41f-default+)
MSR: 800000000282b033 <SF,VEC,VSX,EE,FP,ME,IR,DR,RI,LE> CR: 48048224 XER: 00000000
CFAR: c000000000019cc8 IRQMASK: 1
GPR00: c00000000001a264 c0000000026d3c20 c0000000026d7200 800000000280b033
GPR04: 0000000000000001 0000000000000000 0000000000000077 30206d7372203164
GPR08: 0000000000002000 0000000002002000 800000000280b033 3230303030303030
GPR12: 0000000000008800 c0000000031d0000 0000000000800050 0000000002000066
GPR16: 000000000309a1a0 000000000309a4b0 000000000309a2d8 000000000309a890
GPR20: 00000000030d0098 c00000000264da40 00000000fd620000 c0000000ff798080
GPR24: c00000000264edf0 c0000001007469f0 00000000fd620000 c0000000020e5e90
GPR28: c00000000264edf0 c00000000264d200 000000001db60000 c00000000264d200
NIP [c00000000001a2b4] giveup_all+0xb4/0x110
LR [c00000000001a29c] giveup_all+0x9c/0x110
Call Trace:
[c0000000026d3c20] [c00000000001a264] giveup_all+0x64/0x110 (unreliable)
[c0000000026d3c90] [c00000000001ae34] __switch_to+0x104/0x480
[c0000000026d3cf0] [c000000000e0b8a0] __schedule+0x320/0x970
[c0000000026d3dd0] [c000000000e0c518] schedule_idle+0x38/0x70
[c0000000026d3df0] [c00000000019c7c8] do_idle+0x248/0x3f0
[c0000000026d3e70] [c00000000019cbb8] cpu_startup_entry+0x38/0x40
[c0000000026d3ea0] [c000000000011bb0] rest_init+0xe0/0xf8
[c0000000026d3ed0] [c000000002004820] start_kernel+0x990/0x9e0
[c0000000026d3f90] [c00000000000c49c] start_here_common+0x1c/0x400
Which was unexpected. The warning is checking the thread.regs->msr
value of the task we are switching from:
usermsr = tsk->thread.regs->msr;
...
WARN_ON((usermsr & MSR_VSX) && !((usermsr & MSR_FP) && (usermsr & MSR_VEC)));
ie. if MSR_VSX is set then both of MSR_FP and MSR_VEC are also set.
Dumping tsk->thread.regs->msr we see that it's: 0x1db60000
Which is not a normal looking MSR, in fact the only valid bit is
MSR_VSX, all the other bits are reserved in the current definition of
the MSR.
We can see from the oops that it was swapper/0 that we were switching
from when we hit the warning, ie. init_task. So its thread.regs points
to the base (high addresses) in init_stack.
Dumping the content of init_task->thread.regs, with the members of
pt_regs annotated (the 16 bytes larger version), we see:
0000000000000000 c000000002780080 gpr[0] gpr[1]
0000000000000000 c000000002666008 gpr[2] gpr[3]
c0000000026d3ed0 0000000000000078 gpr[4] gpr[5]
c000000000011b68 c000000002780080 gpr[6] gpr[7]
0000000000000000 0000000000000000 gpr[8] gpr[9]
c0000000026d3f90 0000800000002200 gpr[10] gpr[11]
c000000002004820 c0000000026d7200 gpr[12] gpr[13]
000000001db60000 c0000000010aabe8 gpr[14] gpr[15]
c0000000010aabe8 c0000000010aabe8 gpr[16] gpr[17]
c00000000294d598 0000000000000000 gpr[18] gpr[19]
0000000000000000 0000000000001ff8 gpr[20] gpr[21]
0000000000000000 c00000000206d608 gpr[22] gpr[23]
c00000000278e0cc 0000000000000000 gpr[24] gpr[25]
000000002fff0000 c000000000000000 gpr[26] gpr[27]
0000000002000000 0000000000000028 gpr[28] gpr[29]
000000001db60000 0000000004750000 gpr[30] gpr[31]
0000000002000000 000000001db60000 nip msr
0000000000000000 0000000000000000 orig_r3 ctr
c00000000000c49c 0000000000000000 link xer
0000000000000000 0000000000000000 ccr softe
0000000000000000 0000000000000000 trap dar
0000000000000000 0000000000000000 dsisr result
0000000000000000 0000000000000000 ppr kuap
0000000000000000 0000000000000000 pad[2] pad[3]
This looks suspiciously like stack frames, not a pt_regs. If we look
closely we can see return addresses from the stack trace above,
c000000002004820 (start_kernel) and c00000000000c49c (start_here_common).
init_task->thread.regs is setup at build time in processor.h:
#define INIT_THREAD { \
.ksp = INIT_SP, \
.regs = (struct pt_regs *)INIT_SP - 1, /* XXX bogus, I think */ \
The early boot code where we setup the initial stack is:
LOAD_REG_ADDR(r3,init_thread_union)
/* set up a stack pointer */
LOAD_REG_IMMEDIATE(r1,THREAD_SIZE)
add r1,r3,r1
li r0,0
stdu r0,-STACK_FRAME_OVERHEAD(r1)
Which creates a stack frame of size 112 bytes (STACK_FRAME_OVERHEAD).
Which is far too small to contain a pt_regs.
So the result is init_task->thread.regs is pointing at some stack
frames on the init stack, not at a pt_regs.
We have gotten away with this for so long because with pt_regs at its
current size the MSR happens to point into the first frame, at a
location that is not written to by the early asm. With the 16 byte
expansion the MSR falls into the second frame, which is used by the
compiler, and collides with a saved register that tends to be
non-zero.
As far as I can see this has been wrong since the original merge of
64-bit ppc support, back in 2002.
Conceptually swapper should have no regs, it never entered from
userspace, and in fact that's what we do on 32-bit. It's also
presumably what the "bogus" comment is referring to.
So I think the right fix is to just not-initialise regs at all. I'm
slightly worried this will break some code that isn't prepared for a
NULL regs, but we'll have to see.
Remove the comment in head_64.S which refers to us setting up the
regs (even though we never did), and is otherwise not really accurate
any more.
Reported-by: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200428123130.73078-1-mpe@ellerman.id.au
2020-04-28 12:31:30 +00:00
|
|
|
LOAD_REG_ADDR(r3,init_thread_union)
|
2017-02-24 00:52:10 +00:00
|
|
|
LOAD_REG_IMMEDIATE(r1,THREAD_SIZE)
|
|
|
|
|
add r1,r3,r1
|
2005-09-26 06:04:21 +00:00
|
|
|
li r0,0
|
|
|
|
|
stdu r0,-STACK_FRAME_OVERHEAD(r1)
|
|
|
|
|
|
2014-07-10 02:29:19 +00:00
|
|
|
/*
|
|
|
|
|
* Do very early kernel initializations, including initial hash table
|
|
|
|
|
* and SLB setup before we turn on relocation.
|
|
|
|
|
*/
|
2005-09-26 06:04:21 +00:00
|
|
|
|
|
|
|
|
/* Restore parameters passed from prom_init/kexec */
|
|
|
|
|
mr r3,r31
|
2019-03-27 03:35:54 +00:00
|
|
|
LOAD_REG_ADDR(r12, DOTSYM(early_setup))
|
|
|
|
|
mtctr r12
|
|
|
|
|
bctrl /* also sets r13 and SPRG_PACA */
|
2005-09-26 06:04:21 +00:00
|
|
|
|
2014-02-04 05:04:52 +00:00
|
|
|
LOAD_REG_ADDR(r3, start_here_common)
|
2008-08-30 01:41:12 +00:00
|
|
|
ld r4,PACAKMSR(r13)
|
2005-10-10 04:01:07 +00:00
|
|
|
mtspr SPRN_SRR0,r3
|
|
|
|
|
mtspr SPRN_SRR1,r4
|
2009-07-23 23:15:59 +00:00
|
|
|
RFI
|
2005-09-26 06:04:21 +00:00
|
|
|
b . /* prevent speculative execution */
|
2016-07-05 05:04:09 +00:00
|
|
|
|
2005-09-26 06:04:21 +00:00
|
|
|
/* This is where all platforms converge execution */
|
2014-02-04 05:04:52 +00:00
|
|
|
|
|
|
|
|
start_here_common:
|
2005-09-26 06:04:21 +00:00
|
|
|
/* relocation is on at this point */
|
2008-08-30 01:41:12 +00:00
|
|
|
std r1,PACAKSAVE(r13)
|
2005-09-26 06:04:21 +00:00
|
|
|
|
2008-08-30 01:41:12 +00:00
|
|
|
/* Load the TOC (virtual address) */
|
2005-09-26 06:04:21 +00:00
|
|
|
ld r2,PACATOC(r13)
|
|
|
|
|
|
powerpc: Rework lazy-interrupt handling
The current implementation of lazy interrupts handling has some
issues that this tries to address.
We don't do the various workarounds we need to do when re-enabling
interrupts in some cases such as when returning from an interrupt
and thus we may still lose or get delayed decrementer or doorbell
interrupts.
The current scheme also makes it much harder to handle the external
"edge" interrupts provided by some BookE processors when using the
EPR facility (External Proxy) and the Freescale Hypervisor.
Additionally, we tend to keep interrupts hard disabled in a number
of cases, such as decrementer interrupts, external interrupts, or
when a masked decrementer interrupt is pending. This is sub-optimal.
This is an attempt at fixing it all in one go by reworking the way
we do the lazy interrupt disabling from the ground up.
The base idea is to replace the "hard_enabled" field with a
"irq_happened" field in which we store a bit mask of what interrupt
occurred while soft-disabled.
When re-enabling, either via arch_local_irq_restore() or when returning
from an interrupt, we can now decide what to do by testing bits in that
field.
We then implement replaying of the missed interrupts either by
re-using the existing exception frame (in exception exit case) or via
the creation of a new one from an assembly trampoline (in the
arch_local_irq_enable case).
This removes the need to play with the decrementer to try to create
fake interrupts, among others.
In addition, this adds a few refinements:
- We no longer hard disable decrementer interrupts that occur
while soft-disabled. We now simply bump the decrementer back to max
(on BookS) or leave it stopped (on BookE) and continue with hard interrupts
enabled, which means that we'll potentially get better sample quality from
performance monitor interrupts.
- Timer, decrementer and doorbell interrupts now hard-enable
shortly after removing the source of the interrupt, which means
they no longer run entirely hard disabled. Again, this will improve
perf sample quality.
- On Book3E 64-bit, we now make the performance monitor interrupt
act as an NMI like Book3S (the necessary C code for that to work
appear to already be present in the FSL perf code, notably calling
nmi_enter instead of irq_enter). (This also fixes a bug where BookE
perfmon interrupts could clobber r14 ... oops)
- We could make "masked" decrementer interrupts act as NMIs when doing
timer-based perf sampling to improve the sample quality.
Signed-off-by-yet: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
v2:
- Add hard-enable to decrementer, timer and doorbells
- Fix CR clobber in masked irq handling on BookE
- Make embedded perf interrupt act as an NMI
- Add a PACA_HAPPENED_EE_EDGE for use by FSL if they want
to retrigger an interrupt without preventing hard-enable
v3:
- Fix or vs. ori bug on Book3E
- Fix enabling of interrupts for some exceptions on Book3E
v4:
- Fix resend of doorbells on return from interrupt on Book3E
v5:
- Rebased on top of my latest series, which involves some significant
rework of some aspects of the patch.
v6:
- 32-bit compile fix
- more compile fixes with various .config combos
- factor out the asm code to soft-disable interrupts
- remove the C wrapper around preempt_schedule_irq
v7:
- Fix a bug with hard irq state tracking on native power7
2012-03-06 07:27:59 +00:00
|
|
|
/* Mark interrupts soft and hard disabled (they might be enabled
|
|
|
|
|
* in the PACA when doing hotplug)
|
|
|
|
|
*/
|
2017-12-20 03:55:42 +00:00
|
|
|
li r0,IRQS_DISABLED
|
2017-12-20 03:55:50 +00:00
|
|
|
stb r0,PACAIRQSOFTMASK(r13)
|
powerpc: Rework lazy-interrupt handling
The current implementation of lazy interrupts handling has some
issues that this tries to address.
We don't do the various workarounds we need to do when re-enabling
interrupts in some cases such as when returning from an interrupt
and thus we may still lose or get delayed decrementer or doorbell
interrupts.
The current scheme also makes it much harder to handle the external
"edge" interrupts provided by some BookE processors when using the
EPR facility (External Proxy) and the Freescale Hypervisor.
Additionally, we tend to keep interrupts hard disabled in a number
of cases, such as decrementer interrupts, external interrupts, or
when a masked decrementer interrupt is pending. This is sub-optimal.
This is an attempt at fixing it all in one go by reworking the way
we do the lazy interrupt disabling from the ground up.
The base idea is to replace the "hard_enabled" field with a
"irq_happened" field in which we store a bit mask of what interrupt
occurred while soft-disabled.
When re-enabling, either via arch_local_irq_restore() or when returning
from an interrupt, we can now decide what to do by testing bits in that
field.
We then implement replaying of the missed interrupts either by
re-using the existing exception frame (in exception exit case) or via
the creation of a new one from an assembly trampoline (in the
arch_local_irq_enable case).
This removes the need to play with the decrementer to try to create
fake interrupts, among others.
In addition, this adds a few refinements:
- We no longer hard disable decrementer interrupts that occur
while soft-disabled. We now simply bump the decrementer back to max
(on BookS) or leave it stopped (on BookE) and continue with hard interrupts
enabled, which means that we'll potentially get better sample quality from
performance monitor interrupts.
- Timer, decrementer and doorbell interrupts now hard-enable
shortly after removing the source of the interrupt, which means
they no longer run entirely hard disabled. Again, this will improve
perf sample quality.
- On Book3E 64-bit, we now make the performance monitor interrupt
act as an NMI like Book3S (the necessary C code for that to work
appear to already be present in the FSL perf code, notably calling
nmi_enter instead of irq_enter). (This also fixes a bug where BookE
perfmon interrupts could clobber r14 ... oops)
- We could make "masked" decrementer interrupts act as NMIs when doing
timer-based perf sampling to improve the sample quality.
Signed-off-by-yet: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
v2:
- Add hard-enable to decrementer, timer and doorbells
- Fix CR clobber in masked irq handling on BookE
- Make embedded perf interrupt act as an NMI
- Add a PACA_HAPPENED_EE_EDGE for use by FSL if they want
to retrigger an interrupt without preventing hard-enable
v3:
- Fix or vs. ori bug on Book3E
- Fix enabling of interrupts for some exceptions on Book3E
v4:
- Fix resend of doorbells on return from interrupt on Book3E
v5:
- Rebased on top of my latest series, which involves some significant
rework of some aspects of the patch.
v6:
- 32-bit compile fix
- more compile fixes with various .config combos
- factor out the asm code to soft-disable interrupts
- remove the C wrapper around preempt_schedule_irq
v7:
- Fix a bug with hard irq state tracking on native power7
2012-03-06 07:27:59 +00:00
|
|
|
li r0,PACA_IRQ_HARD_DIS
|
|
|
|
|
stb r0,PACAIRQHAPPENED(r13)
|
2005-09-26 06:04:21 +00:00
|
|
|
|
powerpc: Rework lazy-interrupt handling
The current implementation of lazy interrupts handling has some
issues that this tries to address.
We don't do the various workarounds we need to do when re-enabling
interrupts in some cases such as when returning from an interrupt
and thus we may still lose or get delayed decrementer or doorbell
interrupts.
The current scheme also makes it much harder to handle the external
"edge" interrupts provided by some BookE processors when using the
EPR facility (External Proxy) and the Freescale Hypervisor.
Additionally, we tend to keep interrupts hard disabled in a number
of cases, such as decrementer interrupts, external interrupts, or
when a masked decrementer interrupt is pending. This is sub-optimal.
This is an attempt at fixing it all in one go by reworking the way
we do the lazy interrupt disabling from the ground up.
The base idea is to replace the "hard_enabled" field with a
"irq_happened" field in which we store a bit mask of what interrupt
occurred while soft-disabled.
When re-enabling, either via arch_local_irq_restore() or when returning
from an interrupt, we can now decide what to do by testing bits in that
field.
We then implement replaying of the missed interrupts either by
re-using the existing exception frame (in exception exit case) or via
the creation of a new one from an assembly trampoline (in the
arch_local_irq_enable case).
This removes the need to play with the decrementer to try to create
fake interrupts, among others.
In addition, this adds a few refinements:
- We no longer hard disable decrementer interrupts that occur
while soft-disabled. We now simply bump the decrementer back to max
(on BookS) or leave it stopped (on BookE) and continue with hard interrupts
enabled, which means that we'll potentially get better sample quality from
performance monitor interrupts.
- Timer, decrementer and doorbell interrupts now hard-enable
shortly after removing the source of the interrupt, which means
they no longer run entirely hard disabled. Again, this will improve
perf sample quality.
- On Book3E 64-bit, we now make the performance monitor interrupt
act as an NMI like Book3S (the necessary C code for that to work
appear to already be present in the FSL perf code, notably calling
nmi_enter instead of irq_enter). (This also fixes a bug where BookE
perfmon interrupts could clobber r14 ... oops)
- We could make "masked" decrementer interrupts act as NMIs when doing
timer-based perf sampling to improve the sample quality.
Signed-off-by-yet: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
v2:
- Add hard-enable to decrementer, timer and doorbells
- Fix CR clobber in masked irq handling on BookE
- Make embedded perf interrupt act as an NMI
- Add a PACA_HAPPENED_EE_EDGE for use by FSL if they want
to retrigger an interrupt without preventing hard-enable
v3:
- Fix or vs. ori bug on Book3E
- Fix enabling of interrupts for some exceptions on Book3E
v4:
- Fix resend of doorbells on return from interrupt on Book3E
v5:
- Rebased on top of my latest series, which involves some significant
rework of some aspects of the patch.
v6:
- 32-bit compile fix
- more compile fixes with various .config combos
- factor out the asm code to soft-disable interrupts
- remove the C wrapper around preempt_schedule_irq
v7:
- Fix a bug with hard irq state tracking on native power7
2012-03-06 07:27:59 +00:00
|
|
|
/* Generic kernel entry */
|
2014-02-04 05:04:35 +00:00
|
|
|
bl start_kernel
|
2005-09-26 06:04:21 +00:00
|
|
|
|
2006-02-13 07:11:13 +00:00
|
|
|
/* Not reached */
|
2019-08-26 11:10:23 +00:00
|
|
|
trap
|
|
|
|
|
EMIT_BUG_ENTRY 0b, __FILE__, __LINE__, 0
|
powerpc/64s: Fix section mismatch warnings from boot code
We currently have two section mismatch warnings:
The function __boot_from_prom() references
the function __init prom_init().
The function start_here_common() references
the function __init start_kernel().
The warnings are correct, we do have branches from non-init code into
init code, which is freed after boot. But we don't expect to ever
execute any of that early boot code after boot, if we did that would
be a bug. In particular calling into OF after boot would be fatal
because OF is no longer resident.
So for now fix the warnings by marking the relevant functions as
__REF, which puts them in the ".ref.text" section.
This causes some reordering of the functions in the final link:
@@ -217,10 +217,9 @@
c00000000000b088 t generic_secondary_common_init
c00000000000b124 t __mmu_off
c00000000000b14c t __start_initialization_multiplatform
-c00000000000b1ac t __boot_from_prom
-c00000000000b1ec t __after_prom_start
-c00000000000b260 t p_end
-c00000000000b27c T copy_and_flush
+c00000000000b1ac t __after_prom_start
+c00000000000b220 t p_end
+c00000000000b23c T copy_and_flush
c00000000000b300 T __secondary_start
c00000000000b300 t copy_to_here
c00000000000b344 t start_secondary_prolog
@@ -228,8 +227,9 @@
c00000000000b36c t enable_64b_mode
c00000000000b388 T relative_toc
c00000000000b3a8 t p_toc
-c00000000000b3b0 t start_here_common
-c00000000000b3d0 t start_here_multiplatform
+c00000000000b3b0 t __boot_from_prom
+c00000000000b3f0 t start_here_multiplatform
+c00000000000b480 t start_here_common
c00000000000b880 T system_call_common
c00000000000b974 t system_call
c00000000000b9dc t system_call_exit
In particular __boot_from_prom moves after copy_to_here, which means
it's not copied to zero in the first stage of copy of the kernel to
zero.
But that's OK, because we only call __boot_from_prom before we do the
copy, so it makes no difference when it's copied. The call sequence
is:
__start
-> __start_initialization_multiplatform
-> __boot_from_prom
-> __start
-> __start_initialization_multiplatform
-> __after_prom_start
-> copy_and_flush
-> copy_and_flush (relocated to 0)
-> start_here_multiplatform
-> early_setup
Reported-by: Mauricio Faria de Oliveira <mauricfo@linux.ibm.com>
Reported-by: Roman Bolshakov <r.bolshakov@yadro.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200225031328.14676-1-mpe@ellerman.id.au
2020-02-25 03:13:28 +00:00
|
|
|
.previous
|
2005-09-26 06:04:21 +00:00
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* We put a few things here that have to be page-aligned.
|
|
|
|
|
* This stuff goes at the beginning of the bss, which is page-aligned.
|
|
|
|
|
*/
|
|
|
|
|
.section ".bss"
|
2016-04-29 13:26:26 +00:00
|
|
|
/*
|
|
|
|
|
* pgd dir should be aligned to PGD_TABLE_SIZE which is 64K.
|
|
|
|
|
* We will need to find a better way to fix this
|
|
|
|
|
*/
|
|
|
|
|
.align 16
|
2005-09-26 06:04:21 +00:00
|
|
|
|
2016-04-29 13:26:26 +00:00
|
|
|
.globl swapper_pg_dir
|
|
|
|
|
swapper_pg_dir:
|
|
|
|
|
.space PGD_TABLE_SIZE
|
2005-09-26 06:04:21 +00:00
|
|
|
|
|
|
|
|
.globl empty_zero_page
|
|
|
|
|
empty_zero_page:
|
|
|
|
|
.space PAGE_SIZE
|
2016-01-14 04:33:46 +00:00
|
|
|
EXPORT_SYMBOL(empty_zero_page)
|
