2017-01-24 22:57:52 +00:00
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/*
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* Copyright (C) 2016 Intel Corporation
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* Authors: Sailaja Bandarupalli <sailaja.bandarupalli@intel.com>
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* Ramesh Babu K V <ramesh.babu@intel.com>
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* Vaibhav Agarwal <vaibhav.agarwal@intel.com>
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* Jerome Anand <jerome.anand@intel.com>
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files
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* (the "Software"), to deal in the Software without restriction,
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* including without limitation the rights to use, copy, modify, merge,
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* publish, distribute, sublicense, and/or sell copies of the Software,
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* and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial
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* portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#ifndef _INTEL_HDMI_AUDIO_H_
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#define _INTEL_HDMI_AUDIO_H_
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#include "intel_hdmi_lpe_audio.h"
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#define PCM_INDEX 0
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#define MAX_PB_STREAMS 1
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#define MAX_CAP_STREAMS 0
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2017-01-31 20:16:52 +00:00
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#define HDMI_INFO_FRAME_WORD1 0x000a0184
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#define DP_INFO_FRAME_WORD1 0x00441b84
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2017-01-24 22:57:52 +00:00
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#define FIFO_THRESHOLD 0xFE
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#define DMA_FIFO_THRESHOLD 0x7
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#define BYTES_PER_WORD 0x4
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/* Sampling rate as per IEC60958 Ver 3 */
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#define CH_STATUS_MAP_32KHZ 0x3
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#define CH_STATUS_MAP_44KHZ 0x0
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#define CH_STATUS_MAP_48KHZ 0x2
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#define CH_STATUS_MAP_88KHZ 0x8
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#define CH_STATUS_MAP_96KHZ 0xA
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#define CH_STATUS_MAP_176KHZ 0xC
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#define CH_STATUS_MAP_192KHZ 0xE
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#define MAX_SMPL_WIDTH_20 0x0
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#define MAX_SMPL_WIDTH_24 0x1
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#define SMPL_WIDTH_16BITS 0x1
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#define SMPL_WIDTH_24BITS 0x5
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#define CHANNEL_ALLOCATION 0x1F
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#define VALID_DIP_WORDS 3
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#define LAYOUT0 0
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#define LAYOUT1 1
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#define SWAP_LFE_CENTER 0x00fac4c8
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2017-01-31 17:14:15 +00:00
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#define AUD_CONFIG_CH_MASK 0x70
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2017-01-24 22:57:52 +00:00
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struct pcm_stream_info {
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2017-02-02 12:00:12 +00:00
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struct snd_pcm_substream *substream;
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int substream_refcount;
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2017-02-02 13:57:22 +00:00
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bool running;
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2017-01-24 22:57:52 +00:00
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};
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2017-02-02 15:19:03 +00:00
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/*
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2017-01-24 22:57:52 +00:00
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* struct snd_intelhad - intelhad driver structure
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*
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* @card: ptr to hold card details
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2017-02-02 16:46:49 +00:00
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* @connected: the monitor connection status
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2017-01-24 22:57:52 +00:00
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* @stream_info: stream information
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2017-01-31 12:52:22 +00:00
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* @eld: holds ELD info
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2017-01-24 22:57:52 +00:00
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* @curr_buf: pointer to hold current active ring buf
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* @valid_buf_cnt: ring buffer count for stream
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* @had_spinlock: driver lock
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* @aes_bits: IEC958 status bits
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* @buff_done: id of current buffer done intr
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* @dev: platoform device handle
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* @chmap: holds channel map info
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*/
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struct snd_intelhad {
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struct snd_card *card;
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2017-02-02 16:46:49 +00:00
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bool connected;
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2017-01-24 22:57:52 +00:00
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struct pcm_stream_info stream_info;
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2017-02-02 14:37:11 +00:00
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unsigned char eld[HDMI_MAX_ELD_BYTES];
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2017-01-31 20:16:52 +00:00
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bool dp_output;
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2017-01-24 22:57:52 +00:00
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unsigned int aes_bits;
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spinlock_t had_spinlock;
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struct device *dev;
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struct snd_pcm_chmap *chmap;
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2017-01-31 12:52:22 +00:00
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int tmds_clock_speed;
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int link_rate;
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ALSA: x86: Refactor PCM process engine
This is again a big rewrite of the driver; now it touches the code to
process PCM stream transfers.
The most fundamental change is that the driver may support more than
four periods. Instead of keeping the same index between both the ring
buffer (with the fixed four buffer descriptors) and the PCM buffer
periods, we keep difference indices for both (bd_head and pcm_head
fields). In addition, when the periods are more than four, we need to
track both head and next indices. That is, we now have three indices:
bd_head, pcm_head and pcm_filled.
Also, the driver works better for periods < 4, too: the remaining BDs
out of four are marked as invalid, so that the hardware skips those
BDs in its loop.
By this flexibility, we can use even ALSA-lib dmix plugin, which
requires 16 periods as default.
The buffer size could be up to 20bit, so the max buffer size was
increased accordingly. However, the buffer pre-allocation is kept as
the old value (600kB) as default. The reason is the limited number of
BDs: since it doesn't suffice for the useful SG page management that
can fit with the usual page allocator like some other drivers, we have
to still allocate continuous pages, hence we shouldn't take too big
memories there.
Signed-off-by: Takashi Iwai <tiwai@suse.de>
2017-02-02 23:01:18 +00:00
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/* ring buffer (BD) position index */
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unsigned int bd_head;
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/* PCM buffer position indices */
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unsigned int pcmbuf_head; /* being processed */
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unsigned int pcmbuf_filled; /* to be filled */
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unsigned int num_bds; /* number of BDs */
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unsigned int period_bytes; /* PCM period size in bytes */
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2017-01-31 12:52:22 +00:00
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/* internal stuff */
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int irq;
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void __iomem *mmio_start;
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unsigned int had_config_offset;
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struct work_struct hdmi_audio_wq;
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2017-02-01 16:53:19 +00:00
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struct mutex mutex; /* for protecting chmap and eld */
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2017-01-24 22:57:52 +00:00
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};
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#endif /* _INTEL_HDMI_AUDIO_ */
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