2017-10-04 18:13:41 +00:00
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/*
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* Copyright © 2014-2017 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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*/
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#include "intel_guc.h"
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#include "i915_drv.h"
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2017-10-31 22:53:09 +00:00
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#include "i915_guc_submission.h"
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2017-10-04 18:13:41 +00:00
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static void gen8_guc_raise_irq(struct intel_guc *guc)
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{
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struct drm_i915_private *dev_priv = guc_to_i915(guc);
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I915_WRITE(GUC_SEND_INTERRUPT, GUC_SEND_TRIGGER);
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}
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static inline i915_reg_t guc_send_reg(struct intel_guc *guc, u32 i)
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{
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GEM_BUG_ON(!guc->send_regs.base);
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GEM_BUG_ON(!guc->send_regs.count);
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GEM_BUG_ON(i >= guc->send_regs.count);
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return _MMIO(guc->send_regs.base + 4 * i);
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}
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void intel_guc_init_send_regs(struct intel_guc *guc)
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{
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struct drm_i915_private *dev_priv = guc_to_i915(guc);
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enum forcewake_domains fw_domains = 0;
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unsigned int i;
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guc->send_regs.base = i915_mmio_reg_offset(SOFT_SCRATCH(0));
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guc->send_regs.count = SOFT_SCRATCH_COUNT - 1;
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for (i = 0; i < guc->send_regs.count; i++) {
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fw_domains |= intel_uncore_forcewake_for_reg(dev_priv,
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guc_send_reg(guc, i),
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FW_REG_READ | FW_REG_WRITE);
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}
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guc->send_regs.fw_domains = fw_domains;
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}
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void intel_guc_init_early(struct intel_guc *guc)
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{
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intel_guc_ct_init_early(&guc->ct);
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mutex_init(&guc->send_mutex);
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guc->send = intel_guc_send_nop;
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guc->notify = gen8_guc_raise_irq;
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}
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2017-10-16 14:47:12 +00:00
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static u32 get_gt_type(struct drm_i915_private *dev_priv)
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2017-10-16 14:47:11 +00:00
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{
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/* XXX: GT type based on PCI device ID? field seems unused by fw */
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return 0;
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}
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static u32 get_core_family(struct drm_i915_private *dev_priv)
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{
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u32 gen = INTEL_GEN(dev_priv);
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switch (gen) {
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case 9:
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return GUC_CORE_FAMILY_GEN9;
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default:
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MISSING_CASE(gen);
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return GUC_CORE_FAMILY_UNKNOWN;
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}
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}
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/*
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* Initialise the GuC parameter block before starting the firmware
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* transfer. These parameters are read by the firmware on startup
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* and cannot be changed thereafter.
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*/
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void intel_guc_init_params(struct intel_guc *guc)
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{
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struct drm_i915_private *dev_priv = guc_to_i915(guc);
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u32 params[GUC_CTL_MAX_DWORDS];
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int i;
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2017-10-16 14:47:12 +00:00
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memset(params, 0, sizeof(params));
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2017-10-16 14:47:11 +00:00
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params[GUC_CTL_DEVICE_INFO] |=
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2017-10-16 14:47:12 +00:00
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(get_gt_type(dev_priv) << GUC_CTL_GT_TYPE_SHIFT) |
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(get_core_family(dev_priv) << GUC_CTL_CORE_FAMILY_SHIFT);
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2017-10-16 14:47:11 +00:00
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/*
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* GuC ARAT increment is 10 ns. GuC default scheduler quantum is one
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* second. This ARAR is calculated by:
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* Scheduler-Quantum-in-ns / ARAT-increment-in-ns = 1000000000 / 10
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*/
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params[GUC_CTL_ARAT_HIGH] = 0;
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params[GUC_CTL_ARAT_LOW] = 100000000;
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params[GUC_CTL_WA] |= GUC_CTL_WA_UK_BY_DRIVER;
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params[GUC_CTL_FEATURE] |= GUC_CTL_DISABLE_SCHEDULER |
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GUC_CTL_VCS2_ENABLED;
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params[GUC_CTL_LOG_PARAMS] = guc->log.flags;
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if (i915_modparams.guc_log_level >= 0) {
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params[GUC_CTL_DEBUG] =
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i915_modparams.guc_log_level << GUC_LOG_VERBOSITY_SHIFT;
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2017-10-16 14:47:12 +00:00
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} else {
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2017-10-16 14:47:11 +00:00
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params[GUC_CTL_DEBUG] = GUC_LOG_DISABLED;
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2017-10-16 14:47:12 +00:00
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}
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2017-10-16 14:47:11 +00:00
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/* If GuC submission is enabled, set up additional parameters here */
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if (i915_modparams.enable_guc_submission) {
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u32 ads = guc_ggtt_offset(guc->ads_vma) >> PAGE_SHIFT;
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u32 pgs = guc_ggtt_offset(dev_priv->guc.stage_desc_pool);
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u32 ctx_in_16 = GUC_MAX_STAGE_DESCRIPTORS / 16;
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params[GUC_CTL_DEBUG] |= ads << GUC_ADS_ADDR_SHIFT;
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params[GUC_CTL_DEBUG] |= GUC_ADS_ENABLED;
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pgs >>= PAGE_SHIFT;
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params[GUC_CTL_CTXINFO] = (pgs << GUC_CTL_BASE_ADDR_SHIFT) |
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(ctx_in_16 << GUC_CTL_CTXNUM_IN16_SHIFT);
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params[GUC_CTL_FEATURE] |= GUC_CTL_KERNEL_SUBMISSIONS;
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/* Unmask this bit to enable the GuC's internal scheduler */
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params[GUC_CTL_FEATURE] &= ~GUC_CTL_DISABLE_SCHEDULER;
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}
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/*
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* All SOFT_SCRATCH registers are in FORCEWAKE_BLITTER domain and
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* they are power context saved so it's ok to release forcewake
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* when we are done here and take it again at xfer time.
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*/
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intel_uncore_forcewake_get(dev_priv, FORCEWAKE_BLITTER);
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I915_WRITE(SOFT_SCRATCH(0), 0);
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for (i = 0; i < GUC_CTL_MAX_DWORDS; i++)
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I915_WRITE(SOFT_SCRATCH(1 + i), params[i]);
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intel_uncore_forcewake_put(dev_priv, FORCEWAKE_BLITTER);
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}
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2017-10-04 18:13:41 +00:00
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int intel_guc_send_nop(struct intel_guc *guc, const u32 *action, u32 len)
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{
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WARN(1, "Unexpected send: action=%#x\n", *action);
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return -ENODEV;
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}
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/*
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* This function implements the MMIO based host to GuC interface.
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*/
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int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len)
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{
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struct drm_i915_private *dev_priv = guc_to_i915(guc);
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u32 status;
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int i;
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int ret;
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GEM_BUG_ON(!len);
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GEM_BUG_ON(len > guc->send_regs.count);
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/* If CT is available, we expect to use MMIO only during init/fini */
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GEM_BUG_ON(HAS_GUC_CT(dev_priv) &&
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*action != INTEL_GUC_ACTION_REGISTER_COMMAND_TRANSPORT_BUFFER &&
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*action != INTEL_GUC_ACTION_DEREGISTER_COMMAND_TRANSPORT_BUFFER);
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mutex_lock(&guc->send_mutex);
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intel_uncore_forcewake_get(dev_priv, guc->send_regs.fw_domains);
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for (i = 0; i < len; i++)
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I915_WRITE(guc_send_reg(guc, i), action[i]);
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POSTING_READ(guc_send_reg(guc, i - 1));
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intel_guc_notify(guc);
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/*
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* No GuC command should ever take longer than 10ms.
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* Fast commands should still complete in 10us.
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*/
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ret = __intel_wait_for_register_fw(dev_priv,
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guc_send_reg(guc, 0),
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INTEL_GUC_RECV_MASK,
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INTEL_GUC_RECV_MASK,
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10, 10, &status);
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if (status != INTEL_GUC_STATUS_SUCCESS) {
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/*
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* Either the GuC explicitly returned an error (which
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* we convert to -EIO here) or no response at all was
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* received within the timeout limit (-ETIMEDOUT)
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*/
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if (ret != -ETIMEDOUT)
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ret = -EIO;
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DRM_WARN("INTEL_GUC_SEND: Action 0x%X failed;"
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" ret=%d status=0x%08X response=0x%08X\n",
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action[0], ret, status, I915_READ(SOFT_SCRATCH(15)));
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}
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intel_uncore_forcewake_put(dev_priv, guc->send_regs.fw_domains);
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mutex_unlock(&guc->send_mutex);
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return ret;
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}
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int intel_guc_sample_forcewake(struct intel_guc *guc)
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{
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struct drm_i915_private *dev_priv = guc_to_i915(guc);
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u32 action[2];
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action[0] = INTEL_GUC_ACTION_SAMPLE_FORCEWAKE;
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/* WaRsDisableCoarsePowerGating:skl,bxt */
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2017-10-10 21:30:07 +00:00
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if (!intel_rc6_enabled() ||
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NEEDS_WaRsDisableCoarsePowerGating(dev_priv))
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2017-10-04 18:13:41 +00:00
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action[1] = 0;
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else
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/* bit 0 and 1 are for Render and Media domain separately */
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action[1] = GUC_FORCEWAKE_RENDER | GUC_FORCEWAKE_MEDIA;
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return intel_guc_send(guc, action, ARRAY_SIZE(action));
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}
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/**
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* intel_guc_auth_huc() - Send action to GuC to authenticate HuC ucode
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* @guc: intel_guc structure
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* @rsa_offset: rsa offset w.r.t ggtt base of huc vma
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*
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* Triggers a HuC firmware authentication request to the GuC via intel_guc_send
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* INTEL_GUC_ACTION_AUTHENTICATE_HUC interface. This function is invoked by
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* intel_huc_auth().
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*
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* Return: non-zero code on error
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*/
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int intel_guc_auth_huc(struct intel_guc *guc, u32 rsa_offset)
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{
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u32 action[] = {
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INTEL_GUC_ACTION_AUTHENTICATE_HUC,
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rsa_offset
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};
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return intel_guc_send(guc, action, ARRAY_SIZE(action));
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}
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/**
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* intel_guc_suspend() - notify GuC entering suspend state
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* @dev_priv: i915 device private
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*/
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int intel_guc_suspend(struct drm_i915_private *dev_priv)
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{
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struct intel_guc *guc = &dev_priv->guc;
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u32 data[3];
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if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
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return 0;
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gen9_disable_guc_interrupts(dev_priv);
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data[0] = INTEL_GUC_ACTION_ENTER_S_STATE;
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/* any value greater than GUC_POWER_D0 */
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data[1] = GUC_POWER_D1;
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2017-10-25 20:00:11 +00:00
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data[2] = guc_ggtt_offset(guc->shared_data);
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2017-10-04 18:13:41 +00:00
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return intel_guc_send(guc, data, ARRAY_SIZE(data));
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}
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2017-10-31 22:53:09 +00:00
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/**
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* intel_guc_reset_engine() - ask GuC to reset an engine
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* @guc: intel_guc structure
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* @engine: engine to be reset
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*/
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int intel_guc_reset_engine(struct intel_guc *guc,
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struct intel_engine_cs *engine)
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{
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u32 data[7];
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GEM_BUG_ON(!guc->execbuf_client);
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data[0] = INTEL_GUC_ACTION_REQUEST_ENGINE_RESET;
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data[1] = engine->guc_id;
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data[2] = 0;
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data[3] = 0;
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data[4] = 0;
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data[5] = guc->execbuf_client->stage_id;
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data[6] = guc_ggtt_offset(guc->shared_data);
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return intel_guc_send(guc, data, ARRAY_SIZE(data));
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}
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2017-10-04 18:13:41 +00:00
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/**
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* intel_guc_resume() - notify GuC resuming from suspend state
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* @dev_priv: i915 device private
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*/
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int intel_guc_resume(struct drm_i915_private *dev_priv)
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{
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struct intel_guc *guc = &dev_priv->guc;
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u32 data[3];
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if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
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return 0;
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if (i915_modparams.guc_log_level >= 0)
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gen9_enable_guc_interrupts(dev_priv);
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data[0] = INTEL_GUC_ACTION_EXIT_S_STATE;
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data[1] = GUC_POWER_D0;
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2017-10-25 20:00:11 +00:00
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data[2] = guc_ggtt_offset(guc->shared_data);
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2017-10-04 18:13:41 +00:00
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return intel_guc_send(guc, data, ARRAY_SIZE(data));
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}
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/**
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* intel_guc_allocate_vma() - Allocate a GGTT VMA for GuC usage
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* @guc: the guc
|
|
|
|
* @size: size of area to allocate (both virtual space and memory)
|
|
|
|
*
|
|
|
|
* This is a wrapper to create an object for use with the GuC. In order to
|
|
|
|
* use it inside the GuC, an object needs to be pinned lifetime, so we allocate
|
|
|
|
* both some backing storage and a range inside the Global GTT. We must pin
|
|
|
|
* it in the GGTT somewhere other than than [0, GUC_WOPCM_TOP) because that
|
|
|
|
* range is reserved inside GuC.
|
|
|
|
*
|
|
|
|
* Return: A i915_vma if successful, otherwise an ERR_PTR.
|
|
|
|
*/
|
|
|
|
struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = guc_to_i915(guc);
|
|
|
|
struct drm_i915_gem_object *obj;
|
|
|
|
struct i915_vma *vma;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
obj = i915_gem_object_create(dev_priv, size);
|
|
|
|
if (IS_ERR(obj))
|
|
|
|
return ERR_CAST(obj);
|
|
|
|
|
|
|
|
vma = i915_vma_instance(obj, &dev_priv->ggtt.base, NULL);
|
|
|
|
if (IS_ERR(vma))
|
|
|
|
goto err;
|
|
|
|
|
|
|
|
ret = i915_vma_pin(vma, 0, PAGE_SIZE,
|
|
|
|
PIN_GLOBAL | PIN_OFFSET_BIAS | GUC_WOPCM_TOP);
|
|
|
|
if (ret) {
|
|
|
|
vma = ERR_PTR(ret);
|
|
|
|
goto err;
|
|
|
|
}
|
|
|
|
|
|
|
|
return vma;
|
|
|
|
|
|
|
|
err:
|
|
|
|
i915_gem_object_put(obj);
|
|
|
|
return vma;
|
|
|
|
}
|
2017-10-16 14:47:10 +00:00
|
|
|
|
|
|
|
u32 intel_guc_wopcm_size(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
|
|
|
u32 wopcm_size = GUC_WOPCM_TOP;
|
|
|
|
|
|
|
|
/* On BXT, the top of WOPCM is reserved for RC6 context */
|
|
|
|
if (IS_GEN9_LP(dev_priv))
|
|
|
|
wopcm_size -= BXT_GUC_WOPCM_RC6_RESERVED;
|
|
|
|
|
|
|
|
return wopcm_size;
|
|
|
|
}
|