linux/arch/arm/plat-samsung/include/plat/regs-s3c2412-iis.h

/* linux/include/asm-arm/plat-s3c24xx/regs-s3c2412-iis.h
 *
 * Copyright 2007 Simtec Electronics <linux@simtec.co.uk>
 *	http://armlinux.simtec.co.uk/
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * S3C2412 IIS register definition
*/

#ifndef __ASM_ARCH_REGS_S3C2412_IIS_H
#define __ASM_ARCH_REGS_S3C2412_IIS_H

#define S3C2412_IISCON			(0x00)
#define S3C2412_IISMOD			(0x04)
#define S3C2412_IISFIC			(0x08)
#define S3C2412_IISPSR			(0x0C)
#define S3C2412_IISTXD			(0x10)
#define S3C2412_IISRXD			(0x14)

#define S3C2412_IISCON_LRINDEX		(1 << 11)
#define S3C2412_IISCON_TXFIFO_EMPTY	(1 << 10)
#define S3C2412_IISCON_RXFIFO_EMPTY	(1 << 9)
#define S3C2412_IISCON_TXFIFO_FULL	(1 << 8)
#define S3C2412_IISCON_RXFIFO_FULL	(1 << 7)
#define S3C2412_IISCON_TXDMA_PAUSE	(1 << 6)
#define S3C2412_IISCON_RXDMA_PAUSE	(1 << 5)
#define S3C2412_IISCON_TXCH_PAUSE	(1 << 4)
#define S3C2412_IISCON_RXCH_PAUSE	(1 << 3)
#define S3C2412_IISCON_TXDMA_ACTIVE	(1 << 2)
#define S3C2412_IISCON_RXDMA_ACTIVE	(1 << 1)
#define S3C2412_IISCON_IIS_ACTIVE	(1 << 0)

#define S3C64XX_IISMOD_BLC_16BIT	(0 << 13)
#define S3C64XX_IISMOD_BLC_8BIT		(1 << 13)
#define S3C64XX_IISMOD_BLC_24BIT	(2 << 13)
#define S3C64XX_IISMOD_BLC_MASK		(3 << 13)

#define S3C64XX_IISMOD_IMS_PCLK		(0 << 10)
#define S3C64XX_IISMOD_IMS_SYSMUX	(1 << 10)

#define S3C2412_IISMOD_MASTER_INTERNAL	(0 << 10)
#define S3C2412_IISMOD_MASTER_EXTERNAL	(1 << 10)
#define S3C2412_IISMOD_SLAVE		(2 << 10)
#define S3C2412_IISMOD_MASTER_MASK	(3 << 10)
#define S3C2412_IISMOD_MODE_TXONLY	(0 << 8)
#define S3C2412_IISMOD_MODE_RXONLY	(1 << 8)
#define S3C2412_IISMOD_MODE_TXRX	(2 << 8)
#define S3C2412_IISMOD_MODE_MASK	(3 << 8)
#define S3C2412_IISMOD_LR_LLOW		(0 << 7)
#define S3C2412_IISMOD_LR_RLOW		(1 << 7)
#define S3C2412_IISMOD_SDF_IIS		(0 << 5)
#define S3C2412_IISMOD_SDF_MSB		(1 << 5)
#define S3C2412_IISMOD_SDF_LSB		(2 << 5)
#define S3C2412_IISMOD_SDF_MASK		(3 << 5)
#define S3C2412_IISMOD_RCLK_256FS	(0 << 3)
#define S3C2412_IISMOD_RCLK_512FS	(1 << 3)
#define S3C2412_IISMOD_RCLK_384FS	(2 << 3)
#define S3C2412_IISMOD_RCLK_768FS	(3 << 3)
#define S3C2412_IISMOD_RCLK_MASK 	(3 << 3)
#define S3C2412_IISMOD_BCLK_32FS	(0 << 1)
#define S3C2412_IISMOD_BCLK_48FS	(1 << 1)
#define S3C2412_IISMOD_BCLK_16FS	(2 << 1)
#define S3C2412_IISMOD_BCLK_24FS	(3 << 1)
#define S3C2412_IISMOD_BCLK_MASK	(3 << 1)
#define S3C2412_IISMOD_8BIT		(1 << 0)

#define S3C64XX_IISMOD_CDCLKCON		(1 << 12)

#define S3C2412_IISPSR_PSREN		(1 << 15)

#define S3C2412_IISFIC_TXFLUSH		(1 << 15)
#define S3C2412_IISFIC_RXFLUSH		(1 << 7)
#define S3C2412_IISFIC_TXCOUNT(x)	(((x) >>  8) & 0xf)
#define S3C2412_IISFIC_RXCOUNT(x)	(((x) >>  0) & 0xf)


#endif /* __ASM_ARCH_REGS_S3C2412_IIS_H */
[ARM] 4726/1: S3C2412: IIS register definitions The S3C2412 IIS engine differs from the previous SoC in the range, so add a set of register definitions in a seperate file for it. Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> 2007-12-23 02:09:39 +00:00			`/* linux/include/asm-arm/plat-s3c24xx/regs-s3c2412-iis.h`
			`*`
			`* Copyright 2007 Simtec Electronics <linux@simtec.co.uk>`
			`* http://armlinux.simtec.co.uk/`
			`*`
			`* This program is free software; you can redistribute it and/or modify`
			`* it under the terms of the GNU General Public License version 2 as`
			`* published by the Free Software Foundation.`
			`*`
			`* S3C2412 IIS register definition`
			`*/`

			`#ifndef __ASM_ARCH_REGS_S3C2412_IIS_H`
			`#define __ASM_ARCH_REGS_S3C2412_IIS_H`

			`#define S3C2412_IISCON (0x00)`
			`#define S3C2412_IISMOD (0x04)`
			`#define S3C2412_IISFIC (0x08)`
			`#define S3C2412_IISPSR (0x0C)`
			`#define S3C2412_IISTXD (0x10)`
			`#define S3C2412_IISRXD (0x14)`

			`#define S3C2412_IISCON_LRINDEX (1 << 11)`
			`#define S3C2412_IISCON_TXFIFO_EMPTY (1 << 10)`
			`#define S3C2412_IISCON_RXFIFO_EMPTY (1 << 9)`
			`#define S3C2412_IISCON_TXFIFO_FULL (1 << 8)`
			`#define S3C2412_IISCON_RXFIFO_FULL (1 << 7)`
			`#define S3C2412_IISCON_TXDMA_PAUSE (1 << 6)`
			`#define S3C2412_IISCON_RXDMA_PAUSE (1 << 5)`
			`#define S3C2412_IISCON_TXCH_PAUSE (1 << 4)`
			`#define S3C2412_IISCON_RXCH_PAUSE (1 << 3)`
			`#define S3C2412_IISCON_TXDMA_ACTIVE (1 << 2)`
			`#define S3C2412_IISCON_RXDMA_ACTIVE (1 << 1)`
			`#define S3C2412_IISCON_IIS_ACTIVE (1 << 0)`

ASoC: Fix data format configuration for S3C64XX IISv2 The data format configuration for S3C64xx IISv2 was hardcoded for IISMOD register. This patch changes to the defined values it. And instead of bits 9 and 10 of IISMOD we should clear bits 13 and 14. Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> 2009-08-18 12:56:19 +00:00			`#define S3C64XX_IISMOD_BLC_16BIT (0 << 13)`
			`#define S3C64XX_IISMOD_BLC_8BIT (1 << 13)`
			`#define S3C64XX_IISMOD_BLC_24BIT (2 << 13)`
			`#define S3C64XX_IISMOD_BLC_MASK (3 << 13)`

ASoC: Add s3c64xx-i2s support Add the initial code to support the S3C64XX I2S hardware using the s3c-i2s-v2 core code. Signed-off-by: Ben Dooks <ben@simtec.co.uk> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> 2009-03-04 00:49:31 +00:00			`#define S3C64XX_IISMOD_IMS_PCLK (0 << 10)`
			`#define S3C64XX_IISMOD_IMS_SYSMUX (1 << 10)`

[ARM] 4726/1: S3C2412: IIS register definitions The S3C2412 IIS engine differs from the previous SoC in the range, so add a set of register definitions in a seperate file for it. Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> 2007-12-23 02:09:39 +00:00			`#define S3C2412_IISMOD_MASTER_INTERNAL (0 << 10)`
			`#define S3C2412_IISMOD_MASTER_EXTERNAL (1 << 10)`
			`#define S3C2412_IISMOD_SLAVE (2 << 10)`
			`#define S3C2412_IISMOD_MASTER_MASK (3 << 10)`
			`#define S3C2412_IISMOD_MODE_TXONLY (0 << 8)`
			`#define S3C2412_IISMOD_MODE_RXONLY (1 << 8)`
			`#define S3C2412_IISMOD_MODE_TXRX (2 << 8)`
			`#define S3C2412_IISMOD_MODE_MASK (3 << 8)`
			`#define S3C2412_IISMOD_LR_LLOW (0 << 7)`
			`#define S3C2412_IISMOD_LR_RLOW (1 << 7)`
			`#define S3C2412_IISMOD_SDF_IIS (0 << 5)`
ASoC: Fix Samsung S3C2412_IISMOD_SDF_{MSB,LSB} definitions The definitions of S3C2412_IISMOD_SDF_MSB and S3C2412_IISMOD_SDF_LSB are incorrect, being the same S3C2412_IISMOD_SDF_IIS which is the only correct one in this series. Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> 2009-03-09 17:47:13 +00:00			`#define S3C2412_IISMOD_SDF_MSB (1 << 5)`
			`#define S3C2412_IISMOD_SDF_LSB (2 << 5)`
[ARM] 4726/1: S3C2412: IIS register definitions The S3C2412 IIS engine differs from the previous SoC in the range, so add a set of register definitions in a seperate file for it. Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> 2007-12-23 02:09:39 +00:00			`#define S3C2412_IISMOD_SDF_MASK (3 << 5)`
			`#define S3C2412_IISMOD_RCLK_256FS (0 << 3)`
			`#define S3C2412_IISMOD_RCLK_512FS (1 << 3)`
			`#define S3C2412_IISMOD_RCLK_384FS (2 << 3)`
			`#define S3C2412_IISMOD_RCLK_768FS (3 << 3)`
			`#define S3C2412_IISMOD_RCLK_MASK (3 << 3)`
			`#define S3C2412_IISMOD_BCLK_32FS (0 << 1)`
			`#define S3C2412_IISMOD_BCLK_48FS (1 << 1)`
			`#define S3C2412_IISMOD_BCLK_16FS (2 << 1)`
			`#define S3C2412_IISMOD_BCLK_24FS (3 << 1)`
			`#define S3C2412_IISMOD_BCLK_MASK (3 << 1)`
			`#define S3C2412_IISMOD_8BIT (1 << 0)`

ASoC: Add S3C64xx IIS CDCLK source selection CDCLK can either be an output generated by the CPU, intended for use as the CODEC master clock, or an input (probably from the CODEC) providing a master clock for the IIS block. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> 2009-09-16 18:38:53 +00:00			`#define S3C64XX_IISMOD_CDCLKCON (1 << 12)`

[ARM] 4726/1: S3C2412: IIS register definitions The S3C2412 IIS engine differs from the previous SoC in the range, so add a set of register definitions in a seperate file for it. Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> 2007-12-23 02:09:39 +00:00			`#define S3C2412_IISPSR_PSREN (1 << 15)`

			`#define S3C2412_IISFIC_TXFLUSH (1 << 15)`
			`#define S3C2412_IISFIC_RXFLUSH (1 << 7)`
			`#define S3C2412_IISFIC_TXCOUNT(x) (((x) >> 8) & 0xf)`
			`#define S3C2412_IISFIC_RXCOUNT(x) (((x) >> 0) & 0xf)`



			`#endif /* __ASM_ARCH_REGS_S3C2412_IIS_H */`