2015-10-29 08:36:23 +00:00
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/*
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* Copyright (C) 2015 Free Electrons
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* Copyright (C) 2015 NextThing Co
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*
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* Maxime Ripard <maxime.ripard@free-electrons.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*/
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#include <drm/drmP.h>
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#include <drm/drm_atomic_helper.h>
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#include <drm/drm_crtc.h>
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#include <drm/drm_crtc_helper.h>
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#include <drm/drm_modes.h>
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2017-03-29 18:55:46 +00:00
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#include <drm/drm_of.h>
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2015-10-29 08:36:23 +00:00
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#include <linux/component.h>
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#include <linux/ioport.h>
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#include <linux/of_address.h>
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2016-10-20 03:43:39 +00:00
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#include <linux/of_device.h>
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2015-10-29 08:36:23 +00:00
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#include <linux/of_irq.h>
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#include <linux/regmap.h>
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#include <linux/reset.h>
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#include "sun4i_crtc.h"
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#include "sun4i_dotclock.h"
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#include "sun4i_drv.h"
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2015-10-29 08:37:32 +00:00
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#include "sun4i_rgb.h"
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2015-10-29 08:36:23 +00:00
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#include "sun4i_tcon.h"
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void sun4i_tcon_disable(struct sun4i_tcon *tcon)
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{
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DRM_DEBUG_DRIVER("Disabling TCON\n");
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/* Disable the TCON */
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regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG,
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SUN4I_TCON_GCTL_TCON_ENABLE, 0);
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}
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EXPORT_SYMBOL(sun4i_tcon_disable);
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void sun4i_tcon_enable(struct sun4i_tcon *tcon)
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{
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DRM_DEBUG_DRIVER("Enabling TCON\n");
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/* Enable the TCON */
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regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG,
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SUN4I_TCON_GCTL_TCON_ENABLE,
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SUN4I_TCON_GCTL_TCON_ENABLE);
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}
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EXPORT_SYMBOL(sun4i_tcon_enable);
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void sun4i_tcon_channel_disable(struct sun4i_tcon *tcon, int channel)
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{
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/* Disable the TCON's channel */
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if (channel == 0) {
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regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG,
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SUN4I_TCON0_CTL_TCON_ENABLE, 0);
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clk_disable_unprepare(tcon->dclk);
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2016-01-07 11:32:07 +00:00
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return;
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2015-10-29 08:36:23 +00:00
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}
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2016-01-07 11:32:07 +00:00
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2016-10-20 03:43:39 +00:00
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WARN_ON(!tcon->quirks->has_channel_1);
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2016-01-07 11:32:07 +00:00
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regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG,
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SUN4I_TCON1_CTL_TCON_ENABLE, 0);
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clk_disable_unprepare(tcon->sclk1);
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2015-10-29 08:36:23 +00:00
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}
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EXPORT_SYMBOL(sun4i_tcon_channel_disable);
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void sun4i_tcon_channel_enable(struct sun4i_tcon *tcon, int channel)
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{
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/* Enable the TCON's channel */
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if (channel == 0) {
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regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG,
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SUN4I_TCON0_CTL_TCON_ENABLE,
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SUN4I_TCON0_CTL_TCON_ENABLE);
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clk_prepare_enable(tcon->dclk);
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2016-01-07 11:32:07 +00:00
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return;
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2015-10-29 08:36:23 +00:00
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}
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2016-01-07 11:32:07 +00:00
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2016-10-20 03:43:39 +00:00
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WARN_ON(!tcon->quirks->has_channel_1);
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2016-01-07 11:32:07 +00:00
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regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG,
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SUN4I_TCON1_CTL_TCON_ENABLE,
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SUN4I_TCON1_CTL_TCON_ENABLE);
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clk_prepare_enable(tcon->sclk1);
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2015-10-29 08:36:23 +00:00
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}
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EXPORT_SYMBOL(sun4i_tcon_channel_enable);
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void sun4i_tcon_enable_vblank(struct sun4i_tcon *tcon, bool enable)
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{
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u32 mask, val = 0;
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DRM_DEBUG_DRIVER("%sabling VBLANK interrupt\n", enable ? "En" : "Dis");
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mask = SUN4I_TCON_GINT0_VBLANK_ENABLE(0) |
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SUN4I_TCON_GINT0_VBLANK_ENABLE(1);
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if (enable)
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val = mask;
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regmap_update_bits(tcon->regs, SUN4I_TCON_GINT0_REG, mask, val);
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}
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EXPORT_SYMBOL(sun4i_tcon_enable_vblank);
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static int sun4i_tcon_get_clk_delay(struct drm_display_mode *mode,
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int channel)
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{
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int delay = mode->vtotal - mode->vdisplay;
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if (mode->flags & DRM_MODE_FLAG_INTERLACE)
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delay /= 2;
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if (channel == 1)
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delay -= 2;
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delay = min(delay, 30);
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DRM_DEBUG_DRIVER("TCON %d clock delay %u\n", channel, delay);
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return delay;
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}
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void sun4i_tcon0_mode_set(struct sun4i_tcon *tcon,
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struct drm_display_mode *mode)
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{
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unsigned int bp, hsync, vsync;
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u8 clk_delay;
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u32 val = 0;
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/* Adjust clock delay */
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clk_delay = sun4i_tcon_get_clk_delay(mode, 0);
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regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG,
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SUN4I_TCON0_CTL_CLK_DELAY_MASK,
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SUN4I_TCON0_CTL_CLK_DELAY(clk_delay));
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/* Set the resolution */
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regmap_write(tcon->regs, SUN4I_TCON0_BASIC0_REG,
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SUN4I_TCON0_BASIC0_X(mode->crtc_hdisplay) |
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SUN4I_TCON0_BASIC0_Y(mode->crtc_vdisplay));
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/*
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* This is called a backporch in the register documentation,
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2017-03-09 10:05:25 +00:00
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* but it really is the back porch + hsync
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2015-10-29 08:36:23 +00:00
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*/
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bp = mode->crtc_htotal - mode->crtc_hsync_start;
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DRM_DEBUG_DRIVER("Setting horizontal total %d, backporch %d\n",
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mode->crtc_htotal, bp);
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/* Set horizontal display timings */
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regmap_write(tcon->regs, SUN4I_TCON0_BASIC1_REG,
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SUN4I_TCON0_BASIC1_H_TOTAL(mode->crtc_htotal) |
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SUN4I_TCON0_BASIC1_H_BACKPORCH(bp));
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/*
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* This is called a backporch in the register documentation,
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2017-03-09 10:05:25 +00:00
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* but it really is the back porch + hsync
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2015-10-29 08:36:23 +00:00
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*/
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bp = mode->crtc_vtotal - mode->crtc_vsync_start;
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DRM_DEBUG_DRIVER("Setting vertical total %d, backporch %d\n",
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mode->crtc_vtotal, bp);
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/* Set vertical display timings */
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regmap_write(tcon->regs, SUN4I_TCON0_BASIC2_REG,
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SUN4I_TCON0_BASIC2_V_TOTAL(mode->crtc_vtotal) |
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SUN4I_TCON0_BASIC2_V_BACKPORCH(bp));
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/* Set Hsync and Vsync length */
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hsync = mode->crtc_hsync_end - mode->crtc_hsync_start;
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vsync = mode->crtc_vsync_end - mode->crtc_vsync_start;
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DRM_DEBUG_DRIVER("Setting HSYNC %d, VSYNC %d\n", hsync, vsync);
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regmap_write(tcon->regs, SUN4I_TCON0_BASIC3_REG,
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SUN4I_TCON0_BASIC3_V_SYNC(vsync) |
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SUN4I_TCON0_BASIC3_H_SYNC(hsync));
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/* Setup the polarity of the various signals */
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if (!(mode->flags & DRM_MODE_FLAG_PHSYNC))
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val |= SUN4I_TCON0_IO_POL_HSYNC_POSITIVE;
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if (!(mode->flags & DRM_MODE_FLAG_PVSYNC))
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val |= SUN4I_TCON0_IO_POL_VSYNC_POSITIVE;
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regmap_update_bits(tcon->regs, SUN4I_TCON0_IO_POL_REG,
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SUN4I_TCON0_IO_POL_HSYNC_POSITIVE | SUN4I_TCON0_IO_POL_VSYNC_POSITIVE,
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val);
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/* Map output pins to channel 0 */
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regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG,
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SUN4I_TCON_GCTL_IOMAP_MASK,
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SUN4I_TCON_GCTL_IOMAP_TCON0);
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/* Enable the output on the pins */
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regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG, 0);
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}
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EXPORT_SYMBOL(sun4i_tcon0_mode_set);
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void sun4i_tcon1_mode_set(struct sun4i_tcon *tcon,
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struct drm_display_mode *mode)
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{
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unsigned int bp, hsync, vsync;
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u8 clk_delay;
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u32 val;
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2016-10-20 03:43:39 +00:00
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WARN_ON(!tcon->quirks->has_channel_1);
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2016-01-07 11:32:07 +00:00
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2015-10-29 08:36:23 +00:00
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/* Adjust clock delay */
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clk_delay = sun4i_tcon_get_clk_delay(mode, 1);
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regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG,
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SUN4I_TCON1_CTL_CLK_DELAY_MASK,
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SUN4I_TCON1_CTL_CLK_DELAY(clk_delay));
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/* Set interlaced mode */
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if (mode->flags & DRM_MODE_FLAG_INTERLACE)
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val = SUN4I_TCON1_CTL_INTERLACE_ENABLE;
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else
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val = 0;
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regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG,
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SUN4I_TCON1_CTL_INTERLACE_ENABLE,
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val);
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/* Set the input resolution */
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regmap_write(tcon->regs, SUN4I_TCON1_BASIC0_REG,
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SUN4I_TCON1_BASIC0_X(mode->crtc_hdisplay) |
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SUN4I_TCON1_BASIC0_Y(mode->crtc_vdisplay));
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/* Set the upscaling resolution */
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regmap_write(tcon->regs, SUN4I_TCON1_BASIC1_REG,
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SUN4I_TCON1_BASIC1_X(mode->crtc_hdisplay) |
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SUN4I_TCON1_BASIC1_Y(mode->crtc_vdisplay));
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/* Set the output resolution */
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regmap_write(tcon->regs, SUN4I_TCON1_BASIC2_REG,
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SUN4I_TCON1_BASIC2_X(mode->crtc_hdisplay) |
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SUN4I_TCON1_BASIC2_Y(mode->crtc_vdisplay));
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/* Set horizontal display timings */
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bp = mode->crtc_htotal - mode->crtc_hsync_end;
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DRM_DEBUG_DRIVER("Setting horizontal total %d, backporch %d\n",
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mode->htotal, bp);
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regmap_write(tcon->regs, SUN4I_TCON1_BASIC3_REG,
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SUN4I_TCON1_BASIC3_H_TOTAL(mode->crtc_htotal) |
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SUN4I_TCON1_BASIC3_H_BACKPORCH(bp));
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/* Set vertical display timings */
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bp = mode->crtc_vtotal - mode->crtc_vsync_end;
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DRM_DEBUG_DRIVER("Setting vertical total %d, backporch %d\n",
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mode->vtotal, bp);
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regmap_write(tcon->regs, SUN4I_TCON1_BASIC4_REG,
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SUN4I_TCON1_BASIC4_V_TOTAL(mode->vtotal) |
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SUN4I_TCON1_BASIC4_V_BACKPORCH(bp));
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/* Set Hsync and Vsync length */
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hsync = mode->crtc_hsync_end - mode->crtc_hsync_start;
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vsync = mode->crtc_vsync_end - mode->crtc_vsync_start;
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DRM_DEBUG_DRIVER("Setting HSYNC %d, VSYNC %d\n", hsync, vsync);
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regmap_write(tcon->regs, SUN4I_TCON1_BASIC5_REG,
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SUN4I_TCON1_BASIC5_V_SYNC(vsync) |
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SUN4I_TCON1_BASIC5_H_SYNC(hsync));
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/* Map output pins to channel 1 */
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regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG,
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SUN4I_TCON_GCTL_IOMAP_MASK,
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SUN4I_TCON_GCTL_IOMAP_TCON1);
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/*
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* FIXME: Undocumented bits
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*/
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2016-10-20 03:43:39 +00:00
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if (tcon->quirks->has_unknown_mux)
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2015-10-29 08:36:23 +00:00
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regmap_write(tcon->regs, SUN4I_TCON_MUX_CTRL_REG, 1);
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}
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EXPORT_SYMBOL(sun4i_tcon1_mode_set);
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static void sun4i_tcon_finish_page_flip(struct drm_device *dev,
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struct sun4i_crtc *scrtc)
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{
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unsigned long flags;
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spin_lock_irqsave(&dev->event_lock, flags);
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if (scrtc->event) {
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drm_crtc_send_vblank_event(&scrtc->crtc, scrtc->event);
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drm_crtc_vblank_put(&scrtc->crtc);
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scrtc->event = NULL;
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}
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spin_unlock_irqrestore(&dev->event_lock, flags);
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}
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static irqreturn_t sun4i_tcon_handler(int irq, void *private)
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{
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struct sun4i_tcon *tcon = private;
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struct drm_device *drm = tcon->drm;
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drm/sun4i: Initialize crtc from tcon bind function
The tcon provides part of the functionality of the crtc, and also
provides the device node for the output port of the crtc. To be able
to use drm_of_find_possible_crtcs(), all crtc must be initialized before
any downstream encoders. The other part of the crtc is the display
backend.
The Rockchip DRM driver does this by first binding all vops, which is
their crtc, and this step also creates the crtc objects. Then all
remaining hardware components are bound. With the Allwinner display
pipeline, we have multiple components comprising the crtc, and varying
depths of the display pipeline. Since components are added with a depth
first search of the of_graph, we can initialize the crtc object within
the tcon bind function. Since the backend precedes the tcon, and the
backends cannot be muxed or switched around, we can be sure that the
associated backend is already initialized.
This patch also moves the crtc pointer from the main drm_device data to
the tcon device data. Besides the crtc callbacks, the crtc structure is
only used within the tcon driver to signal vblank events from its
interrupt handler.
As the crtc and layer bits are now called from the tcon bits, we must
move them from the sun4i-drm module to the sun4i-tcon module to avoid
circular dependencies between the two modules. This is because sun4i-drm
also calls into sun4i-tcon.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-02-23 08:05:37 +00:00
|
|
|
struct sun4i_crtc *scrtc = tcon->crtc;
|
2015-10-29 08:36:23 +00:00
|
|
|
unsigned int status;
|
|
|
|
|
|
|
|
regmap_read(tcon->regs, SUN4I_TCON_GINT0_REG, &status);
|
|
|
|
|
|
|
|
if (!(status & (SUN4I_TCON_GINT0_VBLANK_INT(0) |
|
|
|
|
SUN4I_TCON_GINT0_VBLANK_INT(1))))
|
|
|
|
return IRQ_NONE;
|
|
|
|
|
|
|
|
drm_crtc_handle_vblank(&scrtc->crtc);
|
|
|
|
sun4i_tcon_finish_page_flip(drm, scrtc);
|
|
|
|
|
|
|
|
/* Acknowledge the interrupt */
|
|
|
|
regmap_update_bits(tcon->regs, SUN4I_TCON_GINT0_REG,
|
|
|
|
SUN4I_TCON_GINT0_VBLANK_INT(0) |
|
|
|
|
SUN4I_TCON_GINT0_VBLANK_INT(1),
|
|
|
|
0);
|
|
|
|
|
|
|
|
return IRQ_HANDLED;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int sun4i_tcon_init_clocks(struct device *dev,
|
|
|
|
struct sun4i_tcon *tcon)
|
|
|
|
{
|
|
|
|
tcon->clk = devm_clk_get(dev, "ahb");
|
|
|
|
if (IS_ERR(tcon->clk)) {
|
|
|
|
dev_err(dev, "Couldn't get the TCON bus clock\n");
|
|
|
|
return PTR_ERR(tcon->clk);
|
|
|
|
}
|
|
|
|
clk_prepare_enable(tcon->clk);
|
|
|
|
|
|
|
|
tcon->sclk0 = devm_clk_get(dev, "tcon-ch0");
|
|
|
|
if (IS_ERR(tcon->sclk0)) {
|
|
|
|
dev_err(dev, "Couldn't get the TCON channel 0 clock\n");
|
|
|
|
return PTR_ERR(tcon->sclk0);
|
|
|
|
}
|
|
|
|
|
2016-10-20 03:43:39 +00:00
|
|
|
if (tcon->quirks->has_channel_1) {
|
2016-01-07 11:32:07 +00:00
|
|
|
tcon->sclk1 = devm_clk_get(dev, "tcon-ch1");
|
|
|
|
if (IS_ERR(tcon->sclk1)) {
|
|
|
|
dev_err(dev, "Couldn't get the TCON channel 1 clock\n");
|
|
|
|
return PTR_ERR(tcon->sclk1);
|
|
|
|
}
|
2015-10-29 08:36:23 +00:00
|
|
|
}
|
|
|
|
|
2017-03-09 10:05:24 +00:00
|
|
|
return 0;
|
2015-10-29 08:36:23 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static void sun4i_tcon_free_clocks(struct sun4i_tcon *tcon)
|
|
|
|
{
|
|
|
|
clk_disable_unprepare(tcon->clk);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int sun4i_tcon_init_irq(struct device *dev,
|
|
|
|
struct sun4i_tcon *tcon)
|
|
|
|
{
|
|
|
|
struct platform_device *pdev = to_platform_device(dev);
|
|
|
|
int irq, ret;
|
|
|
|
|
|
|
|
irq = platform_get_irq(pdev, 0);
|
|
|
|
if (irq < 0) {
|
|
|
|
dev_err(dev, "Couldn't retrieve the TCON interrupt\n");
|
|
|
|
return irq;
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = devm_request_irq(dev, irq, sun4i_tcon_handler, 0,
|
|
|
|
dev_name(dev), tcon);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(dev, "Couldn't request the IRQ\n");
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct regmap_config sun4i_tcon_regmap_config = {
|
|
|
|
.reg_bits = 32,
|
|
|
|
.val_bits = 32,
|
|
|
|
.reg_stride = 4,
|
|
|
|
.max_register = 0x800,
|
|
|
|
};
|
|
|
|
|
|
|
|
static int sun4i_tcon_init_regmap(struct device *dev,
|
|
|
|
struct sun4i_tcon *tcon)
|
|
|
|
{
|
|
|
|
struct platform_device *pdev = to_platform_device(dev);
|
|
|
|
struct resource *res;
|
|
|
|
void __iomem *regs;
|
|
|
|
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
|
|
regs = devm_ioremap_resource(dev, res);
|
2016-08-26 14:25:25 +00:00
|
|
|
if (IS_ERR(regs))
|
2015-10-29 08:36:23 +00:00
|
|
|
return PTR_ERR(regs);
|
|
|
|
|
|
|
|
tcon->regs = devm_regmap_init_mmio(dev, regs,
|
|
|
|
&sun4i_tcon_regmap_config);
|
|
|
|
if (IS_ERR(tcon->regs)) {
|
|
|
|
dev_err(dev, "Couldn't create the TCON regmap\n");
|
|
|
|
return PTR_ERR(tcon->regs);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Make sure the TCON is disabled and all IRQs are off */
|
|
|
|
regmap_write(tcon->regs, SUN4I_TCON_GCTL_REG, 0);
|
|
|
|
regmap_write(tcon->regs, SUN4I_TCON_GINT0_REG, 0);
|
|
|
|
regmap_write(tcon->regs, SUN4I_TCON_GINT1_REG, 0);
|
|
|
|
|
|
|
|
/* Disable IO lines and set them to tristate */
|
|
|
|
regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG, ~0);
|
|
|
|
regmap_write(tcon->regs, SUN4I_TCON1_IO_TRI_REG, ~0);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int sun4i_tcon_bind(struct device *dev, struct device *master,
|
|
|
|
void *data)
|
|
|
|
{
|
|
|
|
struct drm_device *drm = data;
|
|
|
|
struct sun4i_drv *drv = drm->dev_private;
|
|
|
|
struct sun4i_tcon *tcon;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
tcon = devm_kzalloc(dev, sizeof(*tcon), GFP_KERNEL);
|
|
|
|
if (!tcon)
|
|
|
|
return -ENOMEM;
|
|
|
|
dev_set_drvdata(dev, tcon);
|
|
|
|
drv->tcon = tcon;
|
|
|
|
tcon->drm = drm;
|
2016-07-19 13:17:27 +00:00
|
|
|
tcon->dev = dev;
|
2016-10-20 03:43:39 +00:00
|
|
|
tcon->quirks = of_device_get_match_data(dev);
|
2015-10-29 08:36:23 +00:00
|
|
|
|
|
|
|
tcon->lcd_rst = devm_reset_control_get(dev, "lcd");
|
|
|
|
if (IS_ERR(tcon->lcd_rst)) {
|
|
|
|
dev_err(dev, "Couldn't get our reset line\n");
|
|
|
|
return PTR_ERR(tcon->lcd_rst);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Make sure our TCON is reset */
|
|
|
|
if (!reset_control_status(tcon->lcd_rst))
|
|
|
|
reset_control_assert(tcon->lcd_rst);
|
|
|
|
|
|
|
|
ret = reset_control_deassert(tcon->lcd_rst);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(dev, "Couldn't deassert our reset line\n");
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2017-03-09 10:05:24 +00:00
|
|
|
ret = sun4i_tcon_init_clocks(dev, tcon);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(dev, "Couldn't init our TCON clocks\n");
|
|
|
|
goto err_assert_reset;
|
|
|
|
}
|
|
|
|
|
2015-10-29 08:36:23 +00:00
|
|
|
ret = sun4i_tcon_init_regmap(dev, tcon);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(dev, "Couldn't init our TCON regmap\n");
|
2017-03-09 10:05:24 +00:00
|
|
|
goto err_free_clocks;
|
2015-10-29 08:36:23 +00:00
|
|
|
}
|
|
|
|
|
2017-03-09 10:05:24 +00:00
|
|
|
ret = sun4i_dclk_create(dev, tcon);
|
2015-10-29 08:36:23 +00:00
|
|
|
if (ret) {
|
2017-03-09 10:05:24 +00:00
|
|
|
dev_err(dev, "Couldn't create our TCON dot clock\n");
|
|
|
|
goto err_free_clocks;
|
2015-10-29 08:36:23 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
ret = sun4i_tcon_init_irq(dev, tcon);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(dev, "Couldn't init our TCON interrupts\n");
|
2017-03-09 10:05:24 +00:00
|
|
|
goto err_free_dotclock;
|
2015-10-29 08:36:23 +00:00
|
|
|
}
|
|
|
|
|
2017-03-09 10:05:28 +00:00
|
|
|
tcon->crtc = sun4i_crtc_init(drm, drv->backend, tcon);
|
drm/sun4i: Initialize crtc from tcon bind function
The tcon provides part of the functionality of the crtc, and also
provides the device node for the output port of the crtc. To be able
to use drm_of_find_possible_crtcs(), all crtc must be initialized before
any downstream encoders. The other part of the crtc is the display
backend.
The Rockchip DRM driver does this by first binding all vops, which is
their crtc, and this step also creates the crtc objects. Then all
remaining hardware components are bound. With the Allwinner display
pipeline, we have multiple components comprising the crtc, and varying
depths of the display pipeline. Since components are added with a depth
first search of the of_graph, we can initialize the crtc object within
the tcon bind function. Since the backend precedes the tcon, and the
backends cannot be muxed or switched around, we can be sure that the
associated backend is already initialized.
This patch also moves the crtc pointer from the main drm_device data to
the tcon device data. Besides the crtc callbacks, the crtc structure is
only used within the tcon driver to signal vblank events from its
interrupt handler.
As the crtc and layer bits are now called from the tcon bits, we must
move them from the sun4i-drm module to the sun4i-tcon module to avoid
circular dependencies between the two modules. This is because sun4i-drm
also calls into sun4i-tcon.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-02-23 08:05:37 +00:00
|
|
|
if (IS_ERR(tcon->crtc)) {
|
|
|
|
dev_err(dev, "Couldn't create our CRTC\n");
|
|
|
|
ret = PTR_ERR(tcon->crtc);
|
2015-10-29 08:36:23 +00:00
|
|
|
goto err_free_clocks;
|
|
|
|
}
|
|
|
|
|
2017-02-23 08:05:41 +00:00
|
|
|
ret = sun4i_rgb_init(drm, tcon);
|
2016-05-17 15:56:06 +00:00
|
|
|
if (ret < 0)
|
|
|
|
goto err_free_clocks;
|
|
|
|
|
|
|
|
return 0;
|
2015-10-29 08:36:23 +00:00
|
|
|
|
2017-03-09 10:05:24 +00:00
|
|
|
err_free_dotclock:
|
|
|
|
sun4i_dclk_free(tcon);
|
2015-10-29 08:36:23 +00:00
|
|
|
err_free_clocks:
|
|
|
|
sun4i_tcon_free_clocks(tcon);
|
|
|
|
err_assert_reset:
|
|
|
|
reset_control_assert(tcon->lcd_rst);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void sun4i_tcon_unbind(struct device *dev, struct device *master,
|
|
|
|
void *data)
|
|
|
|
{
|
|
|
|
struct sun4i_tcon *tcon = dev_get_drvdata(dev);
|
|
|
|
|
2017-03-09 10:05:24 +00:00
|
|
|
sun4i_dclk_free(tcon);
|
2015-10-29 08:36:23 +00:00
|
|
|
sun4i_tcon_free_clocks(tcon);
|
|
|
|
}
|
|
|
|
|
2016-11-12 17:19:58 +00:00
|
|
|
static const struct component_ops sun4i_tcon_ops = {
|
2015-10-29 08:36:23 +00:00
|
|
|
.bind = sun4i_tcon_bind,
|
|
|
|
.unbind = sun4i_tcon_unbind,
|
|
|
|
};
|
|
|
|
|
|
|
|
static int sun4i_tcon_probe(struct platform_device *pdev)
|
|
|
|
{
|
2015-10-29 08:37:32 +00:00
|
|
|
struct device_node *node = pdev->dev.of_node;
|
2016-04-11 10:16:33 +00:00
|
|
|
struct drm_bridge *bridge;
|
2015-10-29 08:37:32 +00:00
|
|
|
struct drm_panel *panel;
|
2017-03-29 18:55:46 +00:00
|
|
|
int ret;
|
2015-10-29 08:37:32 +00:00
|
|
|
|
2017-03-29 18:55:46 +00:00
|
|
|
ret = drm_of_find_panel_or_bridge(node, 1, 0, &panel, &bridge);
|
|
|
|
if (ret == -EPROBE_DEFER)
|
|
|
|
return ret;
|
2015-10-29 08:37:32 +00:00
|
|
|
|
2015-10-29 08:36:23 +00:00
|
|
|
return component_add(&pdev->dev, &sun4i_tcon_ops);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int sun4i_tcon_remove(struct platform_device *pdev)
|
|
|
|
{
|
|
|
|
component_del(&pdev->dev, &sun4i_tcon_ops);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2016-10-20 03:43:39 +00:00
|
|
|
static const struct sun4i_tcon_quirks sun5i_a13_quirks = {
|
|
|
|
.has_unknown_mux = true,
|
|
|
|
.has_channel_1 = true,
|
|
|
|
};
|
|
|
|
|
2016-10-20 03:43:40 +00:00
|
|
|
static const struct sun4i_tcon_quirks sun6i_a31_quirks = {
|
|
|
|
.has_channel_1 = true,
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct sun4i_tcon_quirks sun6i_a31s_quirks = {
|
|
|
|
.has_channel_1 = true,
|
|
|
|
};
|
|
|
|
|
2016-10-20 03:43:39 +00:00
|
|
|
static const struct sun4i_tcon_quirks sun8i_a33_quirks = {
|
|
|
|
/* nothing is supported */
|
|
|
|
};
|
|
|
|
|
2015-10-29 08:36:23 +00:00
|
|
|
static const struct of_device_id sun4i_tcon_of_table[] = {
|
2016-10-20 03:43:39 +00:00
|
|
|
{ .compatible = "allwinner,sun5i-a13-tcon", .data = &sun5i_a13_quirks },
|
2016-10-20 03:43:40 +00:00
|
|
|
{ .compatible = "allwinner,sun6i-a31-tcon", .data = &sun6i_a31_quirks },
|
|
|
|
{ .compatible = "allwinner,sun6i-a31s-tcon", .data = &sun6i_a31s_quirks },
|
2016-10-20 03:43:39 +00:00
|
|
|
{ .compatible = "allwinner,sun8i-a33-tcon", .data = &sun8i_a33_quirks },
|
2015-10-29 08:36:23 +00:00
|
|
|
{ }
|
|
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(of, sun4i_tcon_of_table);
|
|
|
|
|
|
|
|
static struct platform_driver sun4i_tcon_platform_driver = {
|
|
|
|
.probe = sun4i_tcon_probe,
|
|
|
|
.remove = sun4i_tcon_remove,
|
|
|
|
.driver = {
|
|
|
|
.name = "sun4i-tcon",
|
|
|
|
.of_match_table = sun4i_tcon_of_table,
|
|
|
|
},
|
|
|
|
};
|
|
|
|
module_platform_driver(sun4i_tcon_platform_driver);
|
|
|
|
|
|
|
|
MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
|
|
|
|
MODULE_DESCRIPTION("Allwinner A10 Timing Controller Driver");
|
|
|
|
MODULE_LICENSE("GPL");
|