2018-05-04 19:05:35 +00:00
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/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright (c) 2018 Chen-Yu Tsai
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* Copyright (c) 2018 Bootlin
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*
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* Chen-Yu Tsai <wens@csie.org>
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* Mylène Josserand <mylene.josserand@bootlin.com>
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*
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* SMP support for sunxi based systems with Cortex A7/A15
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*
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*/
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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#include <asm/cputype.h>
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ENTRY(sunxi_mc_smp_cluster_cache_enable)
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.arch armv7-a
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/*
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* Enable cluster-level coherency, in preparation for turning on the MMU.
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*
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* Also enable regional clock gating and L2 data latency settings for
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* Cortex-A15. These settings are from the vendor kernel.
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*/
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mrc p15, 0, r1, c0, c0, 0
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movw r2, #(ARM_CPU_PART_MASK & 0xffff)
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movt r2, #(ARM_CPU_PART_MASK >> 16)
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and r1, r1, r2
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movw r2, #(ARM_CPU_PART_CORTEX_A15 & 0xffff)
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movt r2, #(ARM_CPU_PART_CORTEX_A15 >> 16)
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cmp r1, r2
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bne not_a15
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/* The following is Cortex-A15 specific */
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/* ACTLR2: Enable CPU regional clock gates */
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mrc p15, 1, r1, c15, c0, 4
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orr r1, r1, #(0x1 << 31)
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mcr p15, 1, r1, c15, c0, 4
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/* L2ACTLR */
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mrc p15, 1, r1, c15, c0, 0
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/* Enable L2, GIC, and Timer regional clock gates */
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orr r1, r1, #(0x1 << 26)
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/* Disable clean/evict from being pushed to external */
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orr r1, r1, #(0x1<<3)
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mcr p15, 1, r1, c15, c0, 0
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/* L2CTRL: L2 data RAM latency */
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mrc p15, 1, r1, c9, c0, 2
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bic r1, r1, #(0x7 << 0)
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orr r1, r1, #(0x3 << 0)
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mcr p15, 1, r1, c9, c0, 2
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/* End of Cortex-A15 specific setup */
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not_a15:
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/* Get value of sunxi_mc_smp_first_comer */
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adr r1, first
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ldr r0, [r1]
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ldr r0, [r1, r0]
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/* Skip cci_enable_port_for_self if not first comer */
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cmp r0, #0
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bxeq lr
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b cci_enable_port_for_self
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.align 2
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first: .word sunxi_mc_smp_first_comer - .
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ENDPROC(sunxi_mc_smp_cluster_cache_enable)
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ENTRY(sunxi_mc_smp_secondary_startup)
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bl sunxi_mc_smp_cluster_cache_enable
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2018-05-04 19:05:40 +00:00
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bl secure_cntvoff_init
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2018-05-04 19:05:35 +00:00
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b secondary_startup
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ENDPROC(sunxi_mc_smp_secondary_startup)
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ENTRY(sunxi_mc_smp_resume)
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bl sunxi_mc_smp_cluster_cache_enable
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b cpu_resume
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ENDPROC(sunxi_mc_smp_resume)
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