2013-03-12 00:48:01 +00:00
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/*
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* pci.c - DesignWare HS OTG Controller PCI driver
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*
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* Copyright (C) 2004-2013 Synopsys, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions, and the following disclaimer,
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* without modification.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The names of the above-listed copyright holders may not be used
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* to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* ALTERNATIVELY, this software may be distributed under the terms of the
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* GNU General Public License ("GPL") as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option) any
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* later version.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
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* IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Provides the initialization and cleanup entry points for the DWC_otg PCI
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* driver
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <linux/spinlock.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/slab.h>
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#include <linux/pci.h>
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#include <linux/usb.h>
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#include <linux/usb/hcd.h>
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#include <linux/usb/ch11.h>
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#include "core.h"
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#include "hcd.h"
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#define PCI_PRODUCT_ID_HAPS_HSOTG 0xabc0
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2013-04-11 16:43:46 +00:00
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static const char dwc2_driver_name[] = "dwc2";
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2013-03-12 00:48:01 +00:00
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2013-04-29 19:49:08 +00:00
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static const struct dwc2_core_params dwc2_module_params = {
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2013-03-12 00:48:01 +00:00
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.otg_cap = -1,
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.otg_ver = -1,
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.dma_enable = -1,
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.dma_desc_enable = 0,
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.speed = -1,
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.enable_dynamic_fifo = -1,
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.en_multiple_tx_fifo = -1,
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.host_rx_fifo_size = 1024,
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.host_nperio_tx_fifo_size = 256,
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.host_perio_tx_fifo_size = 1024,
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.max_transfer_size = 65535,
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.max_packet_count = 511,
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.host_channels = -1,
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.phy_type = -1,
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2013-08-30 16:45:22 +00:00
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.phy_utmi_width = -1,
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2013-03-12 00:48:01 +00:00
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.phy_ulpi_ddr = -1,
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.phy_ulpi_ext_vbus = -1,
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.i2c_enable = -1,
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.ulpi_fs_ls = -1,
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.host_support_fs_ls_low_power = -1,
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.host_ls_low_power_phy_clk = -1,
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.ts_dline = -1,
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.reload_ctl = -1,
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2013-07-16 19:22:12 +00:00
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.ahbcfg = -1,
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staging: dwc2: add microframe scheduler from downstream Pi kernel
The transfer scheduler in the dwc2 driver is pretty basic, not to
mention buggy. It works fairly well with just a couple of devices
plugged in, but if you add, say, multiple devices with periodic
endpoints, the scheduler breaks down and can't even enumerate all
the devices.
To improve this, import the "microframe scheduler" patch from the
driver in the downstream Raspberry Pi kernel, which is based on
the Synopsys vendor driver. The original patch came from Denx
(http://git.denx.de/?p=linux-denx.git) and was commited to the
raspberrypi.org git tree by "popcornmix" (Dom Cobley).
I have added a driver parameter for this, enabled by default, in
case anyone has problems with it and needs to disable it. I don't
think we should add a DT binding for that, though, since I plan
to remove the option once any bugs are fixed.
[raspberrypi.org patch from Dom Cobley]
Signed-off-by: Dom Cobley <popcornmix@gmail.com>
[adapted to dwc2 driver by Paul Zimmerman]
Signed-off-by: Paul Zimmerman <paulz@synopsys.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2013-09-23 21:23:34 +00:00
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.uframe_sched = -1,
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2013-03-12 00:48:01 +00:00
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};
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/**
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* dwc2_driver_remove() - Called when the DWC_otg core is unregistered with the
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* DWC_otg driver
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*
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* @dev: Bus device
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*
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* This routine is called, for example, when the rmmod command is executed. The
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* device may or may not be electrically present. If it is present, the driver
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* stops device processing. Any resources used on behalf of this device are
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* freed.
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*/
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static void dwc2_driver_remove(struct pci_dev *dev)
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{
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struct dwc2_hsotg *hsotg = pci_get_drvdata(dev);
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2013-03-26 00:03:35 +00:00
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dwc2_hcd_remove(hsotg);
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2013-03-12 00:48:01 +00:00
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pci_disable_device(dev);
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}
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/**
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* dwc2_driver_probe() - Called when the DWC_otg core is bound to the DWC_otg
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* driver
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*
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* @dev: Bus device
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*
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* This routine creates the driver components required to control the device
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* (core, HCD, and PCD) and initializes the device. The driver components are
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* stored in a dwc2_hsotg structure. A reference to the dwc2_hsotg is saved
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* in the device private data. This allows the driver to access the dwc2_hsotg
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* structure on subsequent calls to driver methods for this device.
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*/
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static int dwc2_driver_probe(struct pci_dev *dev,
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const struct pci_device_id *id)
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{
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struct dwc2_hsotg *hsotg;
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int retval;
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hsotg = devm_kzalloc(&dev->dev, sizeof(*hsotg), GFP_KERNEL);
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if (!hsotg)
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return -ENOMEM;
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2013-03-26 00:03:35 +00:00
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hsotg->dev = &dev->dev;
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2013-05-02 11:23:17 +00:00
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hsotg->regs = devm_ioremap_resource(&dev->dev, &dev->resource[0]);
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if (IS_ERR(hsotg->regs))
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return PTR_ERR(hsotg->regs);
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2013-03-12 00:48:01 +00:00
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dev_dbg(&dev->dev, "mapped PA %08lx to VA %p\n",
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(unsigned long)pci_resource_start(dev, 0), hsotg->regs);
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if (pci_enable_device(dev) < 0)
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return -ENODEV;
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pci_set_master(dev);
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2014-11-11 17:13:37 +00:00
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retval = devm_request_irq(hsotg->dev, dev->irq,
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dwc2_handle_common_intr, IRQF_SHARED,
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dev_name(hsotg->dev), hsotg);
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if (retval)
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return retval;
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2014-11-11 17:13:34 +00:00
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spin_lock_init(&hsotg->lock);
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2013-03-26 00:03:35 +00:00
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retval = dwc2_hcd_init(hsotg, dev->irq, &dwc2_module_params);
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2013-03-12 00:48:01 +00:00
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if (retval) {
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pci_disable_device(dev);
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return retval;
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}
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pci_set_drvdata(dev, hsotg);
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return retval;
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}
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2013-12-02 23:26:00 +00:00
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static const struct pci_device_id dwc2_pci_ids[] = {
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2013-03-12 00:48:01 +00:00
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{
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PCI_DEVICE(PCI_VENDOR_ID_SYNOPSYS, PCI_PRODUCT_ID_HAPS_HSOTG),
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},
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2013-05-13 17:54:12 +00:00
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{
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PCI_DEVICE(PCI_VENDOR_ID_STMICRO,
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PCI_DEVICE_ID_STMICRO_USB_OTG),
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},
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2013-03-12 00:48:01 +00:00
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{ /* end: all zeroes */ }
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};
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MODULE_DEVICE_TABLE(pci, dwc2_pci_ids);
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static struct pci_driver dwc2_pci_driver = {
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.name = dwc2_driver_name,
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.id_table = dwc2_pci_ids,
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.probe = dwc2_driver_probe,
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.remove = dwc2_driver_remove,
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};
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module_pci_driver(dwc2_pci_driver);
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MODULE_DESCRIPTION("DESIGNWARE HS OTG PCI Bus Glue");
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MODULE_AUTHOR("Synopsys, Inc.");
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MODULE_LICENSE("Dual BSD/GPL");
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