linux/include/clocksource/timer-riscv.h

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Copyright (C) 2019 Western Digital Corporation or its affiliates.
 *
 * Authors:
 *	Atish Patra <atish.patra@wdc.com>
 */

#ifndef __TIMER_RISCV_H
#define __TIMER_RISCV_H

#include <linux/types.h>

extern void riscv_cs_get_mult_shift(u32 *mult, u32 *shift);

#endif
RISC-V: KVM: Add timer functionality The RISC-V hypervisor specification doesn't have any virtual timer feature. Due to this, the guest VCPU timer will be programmed via SBI calls. The host will use a separate hrtimer event for each guest VCPU to provide timer functionality. We inject a virtual timer interrupt to the guest VCPU whenever the guest VCPU hrtimer event expires. This patch adds guest VCPU timer implementation along with ONE_REG interface to access VCPU timer state from user space. Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Anup Patel <anup.patel@wdc.com> Acked-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org> Acked-by: Palmer Dabbelt <palmerdabbelt@google.com> 2021-09-27 11:40:11 +00:00			`/* SPDX-License-Identifier: GPL-2.0-only */`
			`/*`
			`* Copyright (C) 2019 Western Digital Corporation or its affiliates.`
			`*`
			`* Authors:`
			`* Atish Patra <atish.patra@wdc.com>`
			`*/`

			`#ifndef __TIMER_RISCV_H`
			`#define __TIMER_RISCV_H`

			`#include <linux/types.h>`

			`extern void riscv_cs_get_mult_shift(u32 mult, u32 shift);`

			`#endif`