c2681ce7d9
Signed-off-by: Ivaylo Ivanov <ivo.ivanov@null.net> Cc: Bingxing Wang <hi@imbushuo.net> (nice email)
94 lines
4.2 KiB
C
94 lines
4.2 KiB
C
/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* * Neither the name of The Linux Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __MSM8916_CLOCK_H
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#define __MSM8916_CLOCK_H
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#include <Chipset/clock.h>
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#include <Chipset/clock_lib2.h>
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#define UART_DM_CLK_RX_TX_BIT_RATE 0xCC
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#define REG_MM(off) (CLK_CTL_BASE + (off))
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#define MDP_GDSCR REG_MM(0x4D078)
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#define GDSC_POWER_ON_BIT BIT(31)
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#define GDSC_POWER_ON_STATUS_BIT BIT(29)
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#define GDSC_EN_FEW_WAIT_MASK (0x0F << 16)
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#define GDSC_EN_FEW_WAIT_256_MASK BIT(19)
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#define VSYNC_CMD_RCGR REG_MM(0x4D02C)
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#define VSYNC_CFG_RCGR REG_MM(0x4D030)
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#define MDSS_VSYNC_CBCR REG_MM(0x4D090)
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#define MDP_CMD_RCGR REG_MM(0x4D014)
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#define MDP_CFG_RCGR REG_MM(0x4D018)
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#define MDP_CBCR REG_MM(0x4D088)
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#define MDP_AHB_CBCR REG_MM(0x4D07C)
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#define MDP_AXI_CBCR REG_MM(0x4D080)
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#define DSI_BYTE0_CMD_RCGR REG_MM(0x4D044)
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#define DSI_BYTE0_CFG_RCGR REG_MM(0x4D048)
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#define DSI_BYTE0_CBCR REG_MM(0x4D094)
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#define DSI_ESC0_CMD_RCGR REG_MM(0x4D05C)
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#define DSI_ESC0_CFG_RCGR REG_MM(0x4D060)
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#define DSI_ESC0_CBCR REG_MM(0x4D098)
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#define DSI_PIXEL0_CMD_RCGR REG_MM(0x4D000)
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#define DSI_PIXEL0_CFG_RCGR REG_MM(0x4D004)
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#define DSI_PIXEL0_CBCR REG_MM(0x4D084)
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#define DSI_PIXEL0_M REG_MM(0x4D008)
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#define DSI_PIXEL0_N REG_MM(0x4D00C)
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#define DSI_PIXEL0_D REG_MM(0x4D010)
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#define DSI_BYTE1_CMD_RCGR REG_MM(0x4D0B0)
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#define DSI_BYTE1_CFG_RCGR REG_MM(0x4D0B4)
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#define DSI_BYTE1_CBCR REG_MM(0x4D0A0)
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#define DSI_ESC1_CMD_RCGR REG_MM(0x4D0A8)
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#define DSI_ESC1_CFG_RCGR REG_MM(0x4D0AC)
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#define DSI_ESC1_CBCR REG_MM(0x4D09C)
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#define DSI_PIXEL1_CMD_RCGR REG_MM(0x4D0B8)
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#define DSI_PIXEL1_CFG_RCGR REG_MM(0x4D0BC)
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#define DSI_PIXEL1_CBCR REG_MM(0x4D0A4)
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#define DSI_PIXEL1_M REG_MM(0x4D0C0)
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#define DSI_PIXEL1_N REG_MM(0x4D0C4)
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#define DSI_PIXEL1_D REG_MM(0x4D0C8)
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void platform_clock_init(void);
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void clock_init_mmc(uint32_t interface);
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void clock_config_mmc(uint32_t interface, uint32_t freq);
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void clock_config_uart_dm(uint8_t id);
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void hsusb_clock_init(void);
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void clock_config_ce(uint8_t instance);
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void mdp_clock_init(void);
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void mdp_gdsc_ctrl(uint8_t enable);
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void clock_ce_enable(uint8_t instance);
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void clock_ce_disable(uint8_t instance);
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void clock_config_blsp_i2c(uint8_t blsp_id, uint8_t qup_id);
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#endif
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