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Remove most of the ACPI tables for Pixel 3XL

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This commit is contained in:
Zhuowei Zhang 2019-02-24 17:57:20 -08:00
parent f7e339bc43
commit d55e135511
5 changed files with 26 additions and 115 deletions
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2
Pixel3XL/AcpiTables/AcpiTables.inf
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@ -28,7 +28,7 @@
Fadt.aslc Fadt.aslc
Gtdt.aslc Gtdt.aslc
Madt.aslc Madt.aslc
AcpiSsdtRootPci.asl # Juno R1 specific #AcpiSsdtRootPci.asl # Juno R1 specific
[Packages] [Packages]
ArmPkg/ArmPkg.dec ArmPkg/ArmPkg.dec

4
Pixel3XL/AcpiTables/Dbg2.aslc
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@ -22,7 +22,7 @@
#pragma pack(1) #pragma pack(1)
#define DBG2_NUM_DEBUG_PORTS 1 #define DBG2_NUM_DEBUG_PORTS 0
#define DBG2_NUMBER_OF_GENERIC_ADDRESS_REGISTERS 1 #define DBG2_NUMBER_OF_GENERIC_ADDRESS_REGISTERS 1
#define DBG2_NAMESPACESTRING_FIELD_SIZE 8 #define DBG2_NAMESPACESTRING_FIELD_SIZE 8
#define PL011_UART_LENGTH 0x1000 #define PL011_UART_LENGTH 0x1000
@ -72,6 +72,7 @@ STATIC DBG2_TABLE Dbg2 = {
DBG2_NUM_DEBUG_PORTS /* UINT32 NumberDbgDeviceInfo */ DBG2_NUM_DEBUG_PORTS /* UINT32 NumberDbgDeviceInfo */
}, },
{ {
#if 0
/* /*
* Kernel Debug Port * Kernel Debug Port
*/ */
@ -80,6 +81,7 @@ STATIC DBG2_TABLE Dbg2 = {
FixedPcdGet64 (PcdSerialDbgRegisterBase), FixedPcdGet64 (PcdSerialDbgRegisterBase),
PL011_UART_LENGTH, PL011_UART_LENGTH,
NAME_STR_UART1), NAME_STR_UART1),
#endif
} }
}; };

14
Pixel3XL/AcpiTables/Dsdt.asl
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@ -22,6 +22,7 @@ DefinitionBlock("DsdtTable.aml", "DSDT", 1, "ARMLTD", "ARM-JUNO", EFI_ACPI_ARM_O
Method (_OSC, 4, Serialized) { // _OSC: Operating System Capabilities Method (_OSC, 4, Serialized) { // _OSC: Operating System Capabilities
CreateDWordField (Arg3, 0x00, STS0) CreateDWordField (Arg3, 0x00, STS0)
CreateDWordField (Arg3, 0x04, CAP0) CreateDWordField (Arg3, 0x04, CAP0)
#if 0
If ((Arg0 == ToUUID ("0811b06e-4a27-44f9-8d60-3cbbc22e7b48") /* Platform-wide Capabilities */)) { If ((Arg0 == ToUUID ("0811b06e-4a27-44f9-8d60-3cbbc22e7b48") /* Platform-wide Capabilities */)) {
If (!(Arg1 == One)) { If (!(Arg1 == One)) {
STS0 &= ~0x1F STS0 &= ~0x1F
@ -37,11 +38,13 @@ DefinitionBlock("DsdtTable.aml", "DSDT", 1, "ARMLTD", "ARM-JUNO", EFI_ACPI_ARM_O
STS0 &= ~0x1F STS0 &= ~0x1F
STS0 |= 0x06 STS0 |= 0x06
} }
#endif // platformwide
Return (Arg3) Return (Arg3)
} }
Device (CLU0) { // Cluster0 state Device (CLU0) { // Cluster0 state
Name(_HID, "ACPI0010") Name(_HID, "ACPI0010")
Name(_UID, 1) Name(_UID, 1)
#if 0
Name (_LPI, Package() { Name (_LPI, Package() {
0, // Version 0, // Version
0, // Level Index 0, // Level Index
@ -116,13 +119,17 @@ DefinitionBlock("DsdtTable.aml", "DSDT", 1, "ARMLTD", "ARM-JUNO", EFI_ACPI_ARM_O
"CorePwrDn" "CorePwrDn"
}, },
}) })
#endif // power
Device(CPU0) { // A57-0: Cluster 0, Cpu 0 Device(CPU0) { // A57-0: Cluster 0, Cpu 0
Name(_HID, "ACPI0007") Name(_HID, "ACPI0007")
Name(_UID, 4) Name(_UID, 0)
#if 0
Method (_LPI, 0, NotSerialized) { Method (_LPI, 0, NotSerialized) {
return(PLPI) return(PLPI)
} }
#endif
} }
#if 0
Device(CPU1) { // A57-1: Cluster 0, Cpu 1 Device(CPU1) { // A57-1: Cluster 0, Cpu 1
Name(_HID, "ACPI0007") Name(_HID, "ACPI0007")
Name(_UID, 5) Name(_UID, 5)
@ -130,7 +137,9 @@ DefinitionBlock("DsdtTable.aml", "DSDT", 1, "ARMLTD", "ARM-JUNO", EFI_ACPI_ARM_O
return(PLPI) return(PLPI)
} }
} }
#endif // cpu 0
} }
#if 0
Device (CLU1) { // Cluster1 state Device (CLU1) { // Cluster1 state
Name(_HID, "ACPI0010") Name(_HID, "ACPI0010")
Name(_UID, 2) Name(_UID, 2)
@ -237,7 +246,9 @@ DefinitionBlock("DsdtTable.aml", "DSDT", 1, "ARMLTD", "ARM-JUNO", EFI_ACPI_ARM_O
} }
} }
} }
#endif // cluster 1
#if 0
// //
// Keyboard and Mouse // Keyboard and Mouse
// //
@ -384,5 +395,6 @@ DefinitionBlock("DsdtTable.aml", "DSDT", 1, "ARMLTD", "ARM-JUNO", EFI_ACPI_ARM_O
} // USB0_RHUB_HUB1 } // USB0_RHUB_HUB1
} // USB0_RHUB } // USB0_RHUB
} // USB0 } // USB0
#endif
} // Scope(_SB) } // Scope(_SB)
} }

15
Pixel3XL/AcpiTables/Madt.aslc
View File

@ -90,9 +90,8 @@
0, // Flags 0, // Flags
}, },
{ {
#if 0 // Format: EFI_ACPI_5_1_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, MpIdr, Flags, PmuIrq, GicBase, GicVBase, GicHBase,
// Format: EFI_ACPI_5_1_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Flags, PmuIrq, GicBase, GicVBase, GicHBase, // GsivId, GicRBase)
// GsivId, GicRBase, Mpidr)
// Note: The GIC Structure of the primary CPU must be the first entry (see note in 5.2.12.14 GICC Structure of // Note: The GIC Structure of the primary CPU must be the first entry (see note in 5.2.12.14 GICC Structure of
// ACPI v5.1). // ACPI v5.1).
// On Juno we can change the primary CPU changing the SCC register. It is not currently supported in the // On Juno we can change the primary CPU changing the SCC register. It is not currently supported in the
@ -101,8 +100,9 @@
// The cores from a same cluster are kept together. It is not an ACPI requirement but in case the OSPM uses // The cores from a same cluster are kept together. It is not an ACPI requirement but in case the OSPM uses
// the ACPI ARM Parking protocol, it might want to wake up the cores in the order of this table. // the ACPI ARM Parking protocol, it might want to wake up the cores in the order of this table.
EFI_ACPI_5_1_GICC_STRUCTURE_INIT( // A53-0 EFI_ACPI_5_1_GICC_STRUCTURE_INIT( // A53-0
2, 0, GET_MPID(1, 0), EFI_ACPI_5_0_GIC_ENABLED, 50, FixedPcdGet64 (PcdGicInterruptInterfaceBase), 0, 0, GET_MPID(0, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase),
0x2C06F000, 0x2C04F000, 25, 0 /* GicRBase */), 0 /* GicVBase */, 0 /*GicHBase */, 25, 0 /* GicRBase */),
#if 0
EFI_ACPI_5_1_GICC_STRUCTURE_INIT( // A53-1 EFI_ACPI_5_1_GICC_STRUCTURE_INIT( // A53-1
3, 1, GET_MPID(1, 1), EFI_ACPI_5_0_GIC_ENABLED, 54, FixedPcdGet64 (PcdGicInterruptInterfaceBase), 3, 1, GET_MPID(1, 1), EFI_ACPI_5_0_GIC_ENABLED, 54, FixedPcdGet64 (PcdGicInterruptInterfaceBase),
0x2C06F000, 0x2C04F000, 25, 0 /* GicRBase */), 0x2C06F000, 0x2C04F000, 25, 0 /* GicRBase */),
@ -120,9 +120,12 @@
0x2C06F000, 0x2C04F000, 25, 0 /* GicRBase */), 0x2C06F000, 0x2C04F000, 25, 0 /* GicRBase */),
#endif #endif
}, },
EFI_ACPI_6_0_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet64 (PcdGicDistributorBase), 0, 2), // Format: EFI_ACPI_6_0_GIC_DISTRIBUTOR_INIT(GicDistHwId, GicDistBase, GicDistVector, GicVersion)
EFI_ACPI_6_0_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet64 (PcdGicDistributorBase), 0, 3),
// Format: EFI_ACPI_6_0_GIC_MSI_FRAME_INIT(GicMsiFrameId, PhysicalBaseAddress, Flags, SPICount, SPIBase) // Format: EFI_ACPI_6_0_GIC_MSI_FRAME_INIT(GicMsiFrameId, PhysicalBaseAddress, Flags, SPICount, SPIBase)
#if 0
EFI_ACPI_6_0_GIC_MSI_FRAME_INIT(0, ARM_JUNO_GIV2M_MSI_BASE, 0, ARM_JUNO_GIV2M_MSI_SPI_COUNT, ARM_JUNO_GIV2M_MSI_SPI_BASE) EFI_ACPI_6_0_GIC_MSI_FRAME_INIT(0, ARM_JUNO_GIV2M_MSI_BASE, 0, ARM_JUNO_GIV2M_MSI_SPI_COUNT, ARM_JUNO_GIV2M_MSI_SPI_BASE)
#endif
}; };
#endif #endif

106
Pixel3XL/Include/ArmPlatform.h
View File

@ -22,48 +22,6 @@
************************************************************************************/ ************************************************************************************/
// Motherboard Peripheral and On-chip peripheral // Motherboard Peripheral and On-chip peripheral
#define ARM_VE_BOARD_PERIPH_BASE 0x1C010000
#define ARM_VE_BOARD_SYS_ID 0x0000
#define ARM_VE_BOARD_SYS_PCIE_GBE_L 0x0074
#define ARM_VE_BOARD_SYS_PCIE_GBE_H 0x0078
#define ARM_VE_BOARD_SYS_ID_REV(word) ((word >> 28) & 0xff)
// NOR Flash 0
#define ARM_VE_SMB_NOR0_BASE 0x08000000
#define ARM_VE_SMB_NOR0_SZ SIZE_64MB
// Off-Chip peripherals (USB, Ethernet, VRAM)
#define ARM_VE_SMB_PERIPH_BASE 0x18000000
#define ARM_VE_SMB_PERIPH_SZ (SIZE_64MB + SIZE_2MB)
// On-Chip non-secure ROM
#define ARM_JUNO_NON_SECURE_ROM_BASE 0x1F000000
#define ARM_JUNO_NON_SECURE_ROM_SZ SIZE_16MB
// On-Chip Peripherals
#define ARM_JUNO_PERIPHERALS_BASE 0x20000000
#define ARM_JUNO_PERIPHERALS_SZ 0x0E000000
// PCIe MSI address window
#define ARM_JUNO_GIV2M_MSI_BASE 0x2c1c0000
#define ARM_JUNO_GIV2M_MSI_SZ SIZE_256KB
// PCIe MSI to SPI mapping range
#define ARM_JUNO_GIV2M_MSI_SPI_BASE 224
#define ARM_JUNO_GIV2M_MSI_SPI_COUNT 127 //TRM says last SPI is 351, 351-224=127
// On-Chip non-secure SRAM
#define ARM_JUNO_NON_SECURE_SRAM_BASE 0x2E000000
#define ARM_JUNO_NON_SECURE_SRAM_SZ SIZE_16MB
// SOC peripherals (HDLCD, UART, I2C, I2S, USB, SMC-PL354, etc)
#define ARM_JUNO_SOC_PERIPHERALS_BASE 0x7FF50000
#define ARM_JUNO_SOC_PERIPHERALS_SZ (SIZE_64KB * 9)
// 6GB of DRAM from the 64bit address space
#define ARM_JUNO_EXTRA_SYSTEM_MEMORY_BASE 0x0880000000
#define ARM_JUNO_EXTRA_SYSTEM_MEMORY_SZ (SIZE_2GB + SIZE_4GB)
// //
// ACPI table information used to initialize tables. // ACPI table information used to initialize tables.
@ -97,18 +55,6 @@
#define JUNO_REVISION_R2 3 #define JUNO_REVISION_R2 3
#define JUNO_REVISION_UKNOWN 0xFF #define JUNO_REVISION_UKNOWN 0xFF
//
// We detect whether we are running on a Juno r0, r1 or r2
// board at runtime by checking the value of board SYS_ID
//
#define GetJunoRevision(JunoRevision) \
{ \
UINT32 SysId; \
SysId = MmioRead32 (ARM_VE_BOARD_PERIPH_BASE+ARM_VE_BOARD_SYS_ID); \
JunoRevision = ARM_VE_BOARD_SYS_ID_REV( SysId ); \
}
// Define if the exported ACPI Tables are based on ACPI 5.0 spec or latest // Define if the exported ACPI Tables are based on ACPI 5.0 spec or latest
//#define ARM_JUNO_ACPI_5_0 //#define ARM_JUNO_ACPI_5_0
@ -117,64 +63,12 @@
// assigned to the PCI Gigabyte Ethernet device. // assigned to the PCI Gigabyte Ethernet device.
// //
#define ARM_JUNO_SYS_PCIGBE_L (ARM_VE_BOARD_PERIPH_BASE + ARM_VE_BOARD_SYS_PCIE_GBE_L)
#define ARM_JUNO_SYS_PCIGBE_H (ARM_VE_BOARD_PERIPH_BASE + ARM_VE_BOARD_SYS_PCIE_GBE_H)
/*********************************************************************************** /***********************************************************************************
// Motherboard memory-mapped peripherals // Motherboard memory-mapped peripherals
************************************************************************************/ ************************************************************************************/
// Define MotherBoard SYS flags offsets (from ARM_VE_BOARD_PERIPH_BASE) // Define MotherBoard SYS flags offsets (from ARM_VE_BOARD_PERIPH_BASE)
#define ARM_VE_SYS_ID_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00000)
#define ARM_VE_SYS_SW_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00004)
#define ARM_VE_SYS_LED_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00008)
#define ARM_VE_SYS_FLAGS_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00030)
#define ARM_VE_SYS_FLAGS_SET_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00030)
#define ARM_VE_SYS_FLAGS_CLR_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00034)
#define ARM_VE_SYS_FLAGS_NV_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00038)
#define ARM_VE_SYS_FLAGS_NV_SET_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00038)
#define ARM_VE_SYS_FLAGS_NV_CLR_REG (ARM_VE_BOARD_PERIPH_BASE + 0x0003C)
#define ARM_VE_SYS_FLASH (ARM_VE_BOARD_PERIPH_BASE + 0x0004C)
#define ARM_VE_SYS_CFGSWR_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00058)
#define ARM_VE_SYS_MISC (ARM_VE_BOARD_PERIPH_BASE + 0x00060)
#define ARM_VE_SYS_PROCID0_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00084)
#define ARM_VE_SYS_PROCID1_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00088)
#define ARM_VE_SYS_CFGDATA_REG (ARM_VE_BOARD_PERIPH_BASE + 0x000A0)
#define ARM_VE_SYS_CFGCTRL_REG (ARM_VE_BOARD_PERIPH_BASE + 0x000A4)
#define ARM_VE_SYS_CFGSTAT_REG (ARM_VE_BOARD_PERIPH_BASE + 0x000A8)
// //
// Sites where the peripheral is fitted // Sites where the peripheral is fitted
// //
#define ARM_VE_UNSUPPORTED ~0
#define ARM_VE_MOTHERBOARD_SITE 0
#define ARM_VE_DAUGHTERBOARD_1_SITE 1
#define ARM_VE_DAUGHTERBOARD_2_SITE 2
#define VIRTUAL_SYS_CFG(site,func) (((site) << 24) | (func))
//
// System Configuration Control Functions
//
#define SYS_CFG_OSC 1
#define SYS_CFG_VOLT 2
#define SYS_CFG_AMP 3
#define SYS_CFG_TEMP 4
#define SYS_CFG_RESET 5
#define SYS_CFG_SCC 6
#define SYS_CFG_MUXFPGA 7
#define SYS_CFG_SHUTDOWN 8
#define SYS_CFG_REBOOT 9
#define SYS_CFG_DVIMODE 11
#define SYS_CFG_POWER 12
// Oscillator for Site 1
#define SYS_CFG_OSC_SITE1 VIRTUAL_SYS_CFG(ARM_VE_DAUGHTERBOARD_1_SITE, \
SYS_CFG_OSC)
// Oscillator for Site 2
#define SYS_CFG_OSC_SITE2 VIRTUAL_SYS_CFG(ARM_VE_DAUGHTERBOARD_2_SITE, \
SYS_CFG_OSC)
// Can not access the battery backed-up hardware clock on the
// Versatile Express motherboard
#define SYS_CFG_RTC VIRTUAL_SYS_CFG(ARM_VE_UNSUPPORTED,1)
#endif #endif