Nixyri/zig
1
0
Fork 0
mirror of https://github.com/ziglang/zig.git synced 2024-11-22 04:10:13 +00:00
Code Issues Packages Projects Releases Wiki Activity

Add MIR

Emil J 2022-04-13 10:26:06 +02:00
parent c5830aa452
commit d026d4ef00
1 changed files with 5 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
Glossary.md

@ -22,7 +22,7 @@ Intermediate representation. Typically represented as instructions that referenc
* ZIR * ZIR
* AIR * AIR
* MIR (proposed) * MIR (stage2 only)
There is also LLVM IR. There is also LLVM IR.
@ -45,6 +45,10 @@ Does type checking, comptime control flow, and safety-check generation. This is
See `src/Sema.zig`. See `src/Sema.zig`.
### MIR
Machine Intermediate Representation, lowered to from AIR. Each instruction set architecture will have its own MIR dialect as it is designed to closely match available instructions. Designed for stage2+, since LLVM and C backends don't need MIR. Partially implemented. See [the design issue](https://github.com/ziglang/zig/issues/9514).
### ZIR ### ZIR
Zig Intermediate Representation. `src/Astgen.zig` converts AST nodes to these Zig Intermediate Representation. `src/Astgen.zig` converts AST nodes to these